entity ttl74bct8374 is

generic (PHYSICAL_PIN_MAP : string := "DW");

port (CLK:in bit; Q:out bit_vector(1 to 8); D:in bit_vector(1 to 8);
GND, VCC:linkage bit; OC_NEG:in bit; TDO:out bit;
TMS, TDI, TCK:in bit);
--Get IEEE Std 1149.1-2001 attributes and definitions
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of ttl74bct8374: entity is
"STD_1149_1_2001";
attribute PIN_MAP of ttl74bct8374: entity is PHYSICAL_PIN_MAP;
constant DW: PIN_MAP_STRING:="CLK:1, Q:(2,3,4,5,7,8,9,10), " &
"D:(23,22,21,20,19,17,16,15)," &
"GND:6, VCC:18, OC_NEG:24, TDO:11, TMS:12, TCK:13, TDI:14";
constant FK: PIN_MAP_STRING:="CLK:9, Q:(10,11,12,13,16,17,18,19)," &
"D:(6,5,4,3,2,27,26,25)," &
"GND:14, VCC:28, OC_NEG:7, TDO:20, TMS:21, TCK:23, TDI:24";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of ttl74bct8374 : entity is 8;
attribute INSTRUCTION_OPCODE of ttl74bct8374 : entity is
"BYPASS (11111111, 10001000, 00000101, 10000100, 00000001)," &
"EXTEST (00000000, 10000000)," &
"SAMPLE (00000010, 10000010)," &
"PRELOAD(00000010, 10000010),"&
"INTEST (00000011, 10000011)," &
"HIGHZ (00000110, 10000110)," &
"CLAMP (00000111, 10000111)," &
"RUNT (00001001, 10001001)," & -- Boundary run test
"READBN (00001010, 10001010)," & -- Boundary read normal
"READBT (00001011, 10001011)," & -- Boundary read test
"CELLTST(00001100, 10001100)," & -- Boundary self-test normal
"TOPHIP (00001101, 10001101)," & -- Boundary toggle-out test
"SCANCN (00001110, 10001110)," & -- BCR scan normal
"SCANCT (00001111, 10001111)"; -- BCR scan test
attribute INSTRUCTION_CAPTURE of ttl74bct8374 : entity is
"10000001";
attribute REGISTER_ACCESS of ttl74bct8374 : entity is
"BOUNDARY (READBN, READBT, CELLTST)," &
"BYPASS (TOPHIP, RUNT)," &
"BCR[2] (SCANCN, SCANCT)"; -- 2-bit boundary control register
attribute BOUNDARY_LENGTH of ttl74bct8374 : entity is 18;
attribute BOUNDARY_REGISTER of ttl74bct8374 : entity is
-- num cell port function safe [ccell disval rslt]
"17 (BC_1, CLK, input, X)," &
"16 (BC_1, OC_NEG, input, X), " &-- Merged input/
"16 (BC_1, *, control, 1), " &-- control
"15 (BC_1, D(1), input, X)," &
"14 (BC_1, D(2), input, X)," &
"13 (BC_1, D(3), input, X)," &
"12 (BC_1, D(4), input, X)," &
"11 (BC_1, D(5), input, X)," &
"10 (BC_1, D(6), input, X)," &
" 9 (BC_1, D(7), input, X)," &
" 8 (BC_1, D(8), input, X)," & -- cell 16 @ 1 -> Hi-Z
" 7 (BC_1, Q(1), output3, X, 16, 1, Z)," &
" 6 (BC_1, Q(2), output3, X, 16, 1, Z)," &
" 5 (BC_1, Q(3), output3, X, 16, 1, Z)," &
 " 4 (BC_1, Q(4), output3, X, 16, 1, Z)," &
" 3 (BC_1, Q(5), output3, X, 16, 1, Z)," &
" 2 (BC_1, Q(6), output3, X, 16, 1, Z)," &
" 1 (BC_1, Q(7), output3, X, 16, 1, Z)," &
" 0 (BC_1, Q(8), output3, X, 16, 1, Z)";
end ttl74bct8374;