Physics Challenges

Facing the
Semiconductor Industry
Based on the

Alain C. Diebold
Acknowledgements
PY Hung, Hugo Celio, Jimmy Price
Mark Bohr Intel
Novjot Chhabra and Ken Monnig
ITRS Metrology US and International TWGs
References
International Technology Roadmap for Semiconductors
HJ Levinson, Principles of Lithography
C Steinbruchel and BL Chin - Copper Interconnect Technology
SM Sze High Speed Semiconductor Devices
How CMOS works
http://tech-www.informatik.uni-hamburg.de/applets/cmos/cmosdemo.html
Fabrication Process
http://jas.eng.buffalo.edu/education/fab/invFab/
AGENDA

The ITRS Challenge

Litho Processes and Metrology

FEP Processes and Metrology

Interconnect Processes and Metrology

Materials Characterization
Terminology 0.065 m High-performance Micro- Processor

Pitch
pitch = Top
distance between View Side View
closest spaced
metal interconnect
lines at first level
of DRAM

CD
Gate
source drain
Figure courtesy Bryan Tracy

Transistor
CMOS Inverter
Complementary
Metal Oxide Semiconductor Field Effect Transistor
VDD voltage supply

P Channel Transistor - Carriers = holes

Vin Vout

N Channel Transistor Carriers = electrons

Digital -- 0 and 1
At Vin = 0, Vout/VDD = 1
As input voltage Vin goes from 0 to 1 = Vin/VDD Vout/VDD = 1
CMOS
Switching Speed ~ 1/Idsat
governed by Saturation Drive Current
VDD voltage supply

P Channel Transistor - Carriers = holes

Vin Vout

N Channel Transistor Carriers = electrons

Idsat
CMOS
What it looks like

http://jas.eng.buffalo.edu/education/fab/invFab/
See the process in action
Terminology 0.065 m High-performance Micro- Processor

Pitch
pitch = Top
distance between View Side View
closest spaced
metal interconnect
lines at first level
of DRAM

CD
Gate
source drain
Figure courtesy Bryan Tracy

Transistor
 MPU Clock Frequency Actual vs ITRS
Historical <- > 1999 ITRS
2001 ITRS
100,000

Goal: Increase Speed by

2x Speed/2-2.5 years
2X / 4 Years
10,000
Actual Scaling
Acceleration, Or
Frequency (MHz)

Equivalent Scaling
1,000 Innovation
Needed to
2X / 2 Years maintain historical
trend
100
MPU Clock Frequency
Historical Trend:
2X / 2 - 2 Years
Gate Scaling,
Transistor Design
10
contributed
~ 17-19%/year
Architectural Design
innovation contributed
1
additional
1980 1985 1990 1995 2000 2005 2010 2015
~ 21-13%/year
Sources: Sematech, 2001 ITRS ORTC 28
Transistor and Interconnect Delays
SPEED / PERFORMANCE ISSUE The Technical Problem
45
Gate Delay
40 Sum of Delays, Al & SiO2

Sum of Delays, Cu & Low

35
Interconnect Delay, Al & SiO2
30 Interconnect Delay, Cu & Low

25
Delay Gate wi Al & SiO2 Al 3.0 -cm
(ps) Cu 1.7 -cm
20
SiO 2 = 4.0
Gate wi Cu Low = 2.0
15 & Low .8 Thick
Al & Cu
Al & Cu Line 43 Long
10
Gate
5

0
650 500 350 250 180 130 100
Generation (nm)

From ITRS and Mark Bohr (Intel)

Figure from IBM
Speed of Transistor
Transistor Gate Delay, , decreases as CD decreases but Gate
Dielectric must also decrease in thickness.

= Cload Vdd / Idsat Cload = Cox + C

Vdd power supply voltage
Idsat saturation Drive current

Idsat as Lg gate length

Sounds Easy
- Just decrease the Gate length &/or increase mobility

TROUBLE As dielectric thickness decreases leakage

current increases
High Volume IC s
use CMOS w/ Locally Strained Si
Strained Si substrates not used

PMOS 45 nm NMOS
Compressive Strain Tensile Stress SiN Layer
increased hole mobility increased electron mobility

From T. Ghani, et. al., IEDM 2003, p 978.

Courtesy Intel Not for reproduction
 Problem Leakage Current Increases
as SiO2 Gate Dielectric thickness
decreases
1.E+03 25

1.E+02
20
EOT
1.E+01
Jg (A/cm2)

15
1.E+00

EOT (A)
1.E-01
Jg,sim,SiON 10

1.E-02
Jg,ma 5
1.E-03 x

1.E-04 0
2003 2005 2007 2009 2011 2013 2015 2017

Calendar Year
PIDS ITRS 2003
Near Term Solution New Materials
Dielectric Material w/ High k
Poly Si Gate w/ Metal Gate
Transistor Channel w/ Strained Si
GL = 25 to 35 nm
EOT = 1.3 nm
SOI Si channel = 8.5 10 nm.

PMOS Idsat = 789 A/

m
@ Vgs - Vt = 1.25 V + Vdd = 1.5 V
.
NMOS Idsat = 1006 A/ m
Q. Ziang, et al., AMD @ Vgs - Vt = 1.3 V + Vdd = 1.5 V.
VLSI 2003
NMOS w/Strained Si
Long Term Solution
New Type of Transistor & Wafer
Partially-Depleted SOI
Bulk MOSFET
G
G
S D
S D
Buried Oxide layer

Ultra-Thin Body SOI Double-Gate MOSFET

Gate

SiO2
G G1

S D S D
SiO2 SiO2
Source Drain
Buried Oxide layer G2
BOX
IC R&D in Nano Transistors

source

p-Ge

SiOx
Gate

i-Ge
drain
p-Si
Core
VS
GL = 6 nm p-Si core/i-Ge/SiOx/p-Ge
EOT = 1.2 nm GL = 1500 nm
SOI Si channel = 4.6 nm EOT ~ 0.4nm
PMOS Idsat = 130 A/
m Idsat = 1 A/
m
@ Vgs - Vt = 1.65 @ Vdd = 1 V
V + Vdd = 1.5 V

Bruce Doris IBM

IEDM 2002 and 2003
How do we compare Nano-Tech Transistors
with Conventional Transistors?
Transistors
Current flow
Width

Length or CD

ITRS requires high performance transistors for the next 15

years have a current of from ~ 1 to ~ 2 x 10-3 amp/m

NMOS ~ 1mA / m
PMOS ~ 0.5 to 0.7 mA / m

Saturation Current is normalized by gate width W

 p-Si core/i-Ge/SiOx/p-Ge
source
GL = 1500 nm
p-Ge EOT ~ 0.4nm
Gate
SiOx Observed range of 1 to 5 A @ 1V
i-Ge
drain Diameter without metal connection
p-Si to Ge gate is 50 nm
Core

Current Width
flow
Length or CD

1 milli-amp of current/ m needed to meet performance requirements

1 x 10-3 amps = 200 nanowire transistors x 5000 nano Amps/transistor
This would require 200 nanowires in 1 micron width = 50 nm / nanowire
with Idsat = ~ 5 A/
m of each nanowire transistor @ 1Vdd
Or

1000 nano Amps/transistor x 1000 nanowire transistors with 10 nm space

With Idsat = ~ 1 A/
m -------- an impossible pitch
Interconnect Delay :LOCAL LINE SCALING
Local lines scale as the transistors shrink.

Transistor L

w w

Local conductor lines get smaller in cross-section, spacing & length.

RC Delay 2
2
L Both L&W Scale
w the Same
Thanks to Novjot Chhabra
Interconnect Delay :GLOBAL LINE SCALING
Global conductor lines getting smaller in cross-section
but NOT in length. Signal delay is growing exponentially!

.25u
Generation

LINEs
get smaller
But!
CHIPs dont

.13u
Generation

RC Delay 2
L2 L Stays Same

w W Decreases

Thanks to Novjot Chhabra

 THE PROBLEM IS RC - HOW FAR CAN
YOU GO?
A Theoretical Ideal

Aluminum (alloy) >>> Copper, R reduction of

Resistivity 3.2 1.8 1.8 x

SiO2 >>>>>>>>>>> Air, C reduction of

Dielectric 4.2 1.0 4.2 x
Constant

RC Reduction of
7.5

Thanks to Novjot Chhabra

 MODELED EFFECTIVE DIELECTRIC CONSTANTS

Bulk Dielectric

50nM SiC

k1
Cu Cu 0.26uM
0.14uM

50nM SiC

Bulk Dielectric

If bulk dielectric = 2.6 (SiLK*) then keff = 2.94

If bulk dielectric = 2.2 then keff = 2.57
If bulk dielectric = 1.5 then keff = 1.96
If bulk dielectric = 1.0 (Air) then keff = 1.5

* SiLK Semiconductor Dielectric, Trademark of the Dow Chemical Company

Thanks to Novjot Chhabra

 ITRS Challenge 2003

2001 2002 2004 2007 2010 2013 2016

Leading Production
Technology Node 130 nm 115 nm 90nm 65 nm 45 nm 32 nm 22 nm
= DRAM Pitch
150 130 90 65 45 32 22
MPU / ASIC Pitch (nm)

MPU Printed Gate Length (nm) 90 75 53 35 25 18 13

MPU Physical Gate Length (nm) 65 53 37 25 18 13 9

Beta Site
Leading Edge Tool 90 nm Node
Specifications set
R&D
45 nm Node Metrology R&D 65 nm Node
Materials available
10 nm structures difficult to obtain Early R&D
45 nm Node
 Process control
Is based on Statistical Significance
CP = CPK
UL LL EFFECT OF P/T ON MEASURED Cp
100%

MEASURED Cp/ACTUAL Cp
CP < 1 90%

6 80% P/T=0.1
P/T=0.2
70% P/T=0.3
P/T=0.5
60% P/T=0.7
P/T=0.8
50% P/T=1.0
CP = 1
40%

30%
0.75 1 1.25 1.5 1.75 2 2.25 2.5

ACTUAL Cp

CP > 1

If Distribution is Centered
 What are you Measuring?
single value from distribution

average

test
Distribution of structure
linewidths inside test inside a die
structure
AGENDA

The ITRS Challenge

Litho Processes and Metrology

FEP Processes and Metrology

Interconnect Processes and Metrology

Materials Characterization
 Litho Process and Metrology
CD Control Starts at the Mask 22 nm Node - 2016
6.35m Overlay and CD Control after Exposure
m

152
mm Light

m
2m
15
Mask
52 nm mask line width
26 nm scattering bars
LENS

CD Control after Etch

Wafer

13 nm printed line width

9 nm physical line width

Optical Lithography
Feature Size vs Wavelength
500
CD < /2
400
Node (nm)

300
248 nm
193 nm
200

157 nm
100
EUV

0
1994 1998 2002 2006 2010 2014
Year
 Litho Metrology 157
nm
193 nm EUV
Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm Driver
Lithography Metrology
Printed Gate CD Control (nm) 5.3 3 2 1.5 1.1 0.7 MPU

Wafer CD 3 Precision P/T=0.2 1.1 0.6 0.4 0.3 0.2 0.1 MPU

Line Edge Roughness (nm) 4.5 2.7 1.8 1.3 0.9 0.65 MPU

Precision for LER 0.9 0.54 0.36 0.26 0.18 0.13

193 and 157 nm

EUV
Physics of Resolution
Resolution W = k /NA
To print small features use smaller
the wavelengths
Use tricks to Print features sizes
close to the wavelength
is the wavelength of the light
NA is the numerical aperture
NA = sin is index of refraction
K is a constant that depends on the process
See Principles of Lithography, H. Levinson, p 19
 Physics of Depth of Focus
DoF = k2 / (NA)2 >> feature size
To print small features use smaller
the wavelengths
Use tricks to Print features sizes
close to the wavelength
is the wavelength of the light
NA is the numerical aperture
NA = sin is index of refraction
K is a constant that depends on the process
See The Rayleigh Depth of Focus, C. Mack, Microlithography World: Feb 2004
Tricks to extend Optical Lithography
Mask features that do not print
Optical Proximity Corrections Phase Shift Masks
SIDE View
Contact
Light Contact W/ OPC

Alternating Phase Shift

Mask
TOP View
LENS
Rim Phase Shift

Wafer Many other types

Isolated Line w/
Scattering Bars
Immersion LENS
Change NA by changing refractive index
from air = 1 to water = 1.46

Extends 193 nm Litho to smaller feature

sizes W(immersion)/W(dry) = 1/1.46 ~ 0.7

DoF(immersion)/DoF (dry) at 193 nm

See The Rayleigh Depth of Focus, C. Mack,

Microlithography World: Feb 2004
 Low Energy SEM for CD Measurements

Top Down
FE source Image
Secondary
Electron
Detector

Scanning
coils

wafer Lens

Sample Stage

Thanks to David Joy

Limits of SEM for CD Measurements
TBW =

Loss of Depth of Field

CD
DoF =
20 nm (resolution)/(convergence
angle)

10 nm
TBW =

CD

Gabors limit
5 nm
Thanks to David Joy
Challenges: Round Top Resist & LER

Line Edge Roughness

Requires Better
Dimensional Precision

50 nm

50 nm
Ultra Low Voltage CD-SEM

Thanks to Neal Sullivan of Schlumberger

 Lithography CD Metrology
Improve CD-SEM thru 65 nm node

High Voltage CD-SEM

100 200 keV

e-

Comparison of conventional SE (left) and

Low Loss (right) images of copper
interconnects. Note the greatly enhanced
surface detail and lack of edge brightness in
the Low Loss image.
Micrograph courtesy of O C Wells
Low loss detector

Figures from David Joy

 3D CD Metrology SEM Scatterometry CD-AFM

Commercially available R&D

Software comparison of top
down line scan of edge to
golden image
Software to convert
Tilt Beam SEM top down image to
3D image
600

5
500

400

300

200
Scatterometry
100

0
-480 -400 -320 -240 -160 -80 0 80 160

CD-AFM

Dual Beam FIB

(destructive)
Scatterometry for CD Measurements
Mirror

in = out
Multi-wavelength Polarization
Light Source Sensitive
Detector
Real Time Calculation
of line width & shape
Eliminates Libraries
600

5
500

400

Incident Polarized 300

200

White Light 100

0th order 0
-480 -400 -320 -240 -160 -80 0 80 160
CD-AFM Limited by Probe Tip

Carbon Nanotube Probe tips

 Average vs Individual

CD-SEM measures one line at a time

Scatterometry gives an average over many

lines

Reports indicate a large number (80 different

lines) CD-SEM measurements in test area
required to match scatterometry average

Lose individual line information

AGENDA

The ITRS Challenge

Litho Processes and Metrology

FEP Processes and Metrology

Interconnect Processes and Metrology

Materials Characterization
Front End Processes & Metrology
Pattern &
Shallow Trench Isolation
Implant Wells

Pattern & Gate Dielectric

Pattern Poly/metal
Implant LDD

Pattern & Implant S/D

 FEP : High Metrology
Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm Driver
Front End Processes Metrology
High Performance Logic EOT
1.3-1.6 0.9-1.4 0.6-1.1 0.50.8 0.40.6 0.40.5 MPU
equivalent oxide thickness (EOT) nm
Logic Dielectric EOT Precision 3 (nm) 0.005 0.004 0.0024 0.0024 0.0016 0.0016 MPU
Metrology for Ultra-Shallow Junctions at
26 14.8 10 7.2 5.2 3.6 MPU
Channel Xj (nm)

High near UV light Out of the Furnace

absorption High Dit
Makes thin interfacial layer = Error in EOT
difficult to measure
1.00E-06
9.00E-07
8.00E-07
Light source: Dit=0
7.00E-07

C (F /cm ^ 2)
(Xe, D2, lasers) Dit=1e10
6.00E-07
monochromator analyzer 5.00E-07 Dit=1e11
polarizer 4.00E-07 Dit=1e12
p
3.00E-07
p Dit=1e13
2.00E-07
p s p 1.00E-07
s
E(t) 0.00E+00
-3 -2 -1 0 1 2 3
E
Vg (V) tox=3nm,Nsub=1e17,Npoly=1e20
s s
Polarization Si Polarization
before sample after sample
Optical/X-ray vs Electrical Measurement
C-V Structures receive Further Processing
Optical thickness vs electrical EOT
Capacitance of a very thin interface can have big effect
)thigh
EOT = t int + (3.9/

toptical = t int + t high poly-Si Vgate

Vpoly depletion
tox. Cox.
tint. dielectric C interface

Si-substrate
QM charge

Optical Physical Traditional Electrical

(Process Monitoring) (Performance/Reliability)

See also : C Richter in Char & Met for ULSI 2000

 SPC requires measurement to
Average Gate Dielectric over large area
Light source
(Xe, D2, lasers)

monochromator analyzer
polarizer
p
p
s s
s
(a)
a-Si
E(t)
HfSixOy

30
Si(100)

p
Si Polarization
after sample

2002 ALMC concensus method for TEM

New Optical Models for higher

Optical Constants
9.0 2.5

Imag(Dielectric Constant), 2
Real(Dielectric Constant), 1
8.0
2.0
7.0

6.0 1.5

5.0 High K 1.0

4.0
0.5
3.0
SiO2
2.0 0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
Photon Energy (eV)

In-Line Metrology Suppliers continue to use older damped oscillator models

Simplified X-ray Path for X-ray reflectometer
slits
diffuse scatter
X-ray
source

slits detector
specularly
sample
reflected
beam
Models can include interface layer 0090814-07 40 HfO2 850C/20s
10 6
experimental data
10 5
simulated profile

Intensity (counts s )
-1
10 4
d
10 3
4 nm HfO2
10 2

2 d sin 10 1
Phase shift =
10 0

10 -1
0 3600 7200 10800 14400
Thanks to Rich Matyi Angle (arcseconds)
Extra reflection from SOI Wafers Impacts Optical
Measurements and Light Scattering

Si Wafer
SOI Wafer

Gate Dielectric Gate Dielectric

on Si Wafer on SOI Wafer

Quantum confinement for sub 20 nm silicon

Need SOI Optical Constants
AGENDA

The ITRS Challenge

Litho Processes and Metrology

FEP Processes and Metrology

Interconnect Processes and Metrology

Materials Characterization
Interconnect Processes & Metrology
Pattern Low Control Line width/depth and shape

Deposit barrier and copper

Control barrier/copper & voiding

Chemical Mechanical Polishing

Control Flatness

Low k / barrier
etch stop / low k
 Gaps in Interconnect Metrology
Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm
Interconnect Metrology
13 10 7 5 4
Barrier layer thick (nm) process range (3 )
20% 20% 20% 20% 20%
Precision 1 (nm)
0.04 0.03 0.02 0.016 0.013
Void Size for 1% Voiding in Cu Lines 87 52 37 26 18 12
Detection of Killer Pores at (nm) size 6.5 4.5 3.25 2.25 1.6 1.1

VOID Detection in Copper lines

Killer Pore Detection in Low

Barrier / Seed Cu on sidewalls

Control of each new Low

R-C test structures of new low
Prior to manufacture

Resistance Test

Capacitance Test
 XRR for low process control
0
10
1101807-08
Raw Data
-1
10 Fitted Data

-2

Reflectivity
10

-3
10

-4
10

-5
10
0.0 0.5 1.0 1.5 2.0

Porous Low-k Scattering Angle 2 /Deg.

391.1 nm
SiNC 15 nm (density 1.89g/cm3)
18 nm
SiNC 3 nm (density 1.70g/cm3)
SiNC 15 nm (density 1.89g/cm3)
6 periods SiNC 3 nm (density 1.70g/cm3)

SiNC 15 nm (density 1.89g/cm3)

SiNC 3 nm (density 1.70g/cm3)
SiO2 (density 2.14 g/cm3) 0.2 m
550 nm

Si substrate
 Pore Size Distribution
Diffuse (small angle) x-ray scattering

0.050
Scattering Intensity

Average pore diameter = 50

105105 0.040 p = 0.2
Raw data
4 Distribution 1
Scattering Intensity /CPS

10 Simulated data
Residual 0.030 p=1

p (r)
3
10
0.020 p = 0.5
2
10

1 0.010
10

101000 0.000 0 10 20 30 40 50 60 70
2 4 6 8
2 4
Scattering Angle 2 /Deg. 6 8
Scattering Angle r ()
AGENDA

The ITRS Challenge

Litho Processes and Metrology

FEP Processes and Metrology

Interconnect Processes and Metrology

Materials Characterization
Method Dependent Observation of
Film Properties

Local information
HRTEM of SiO2 Thickness

Silicon Wafer on a Wafer Chuck

TEM Imaging of the Interface
Incident
beam
Measured
Profile

Distance
 TEM of thin gate dielectric
Simulation and Experimental Data
show ADF-STEM and HR-TEM give
same thickness

Rough Interface SiO2

Silicon

Smooth Interface

a b

Consensus method uses 50 nm thick sample & ADF-STEM

Thanks to Dave Muller

 Local Electrode Atom Probe

z
Vaccel

Vpulseb y
x

Vex Atom Distribution

: < 100% detection

Metrology & New Structures
Memory
SINGLE/FEW
STORAGE BASELINE 2002 PHASE CHANGE NANO FLOATING MOLECULAR
MAGNETIC RAM ELECTRON
MECHANISM TECHNOLOGIES MEMORY GATE MEMORY MEMORIES
MEMORIES
Ga te WORD
Engi neere d ba rrier
W
me mor y nod e
+ +
n n R

BIT
Si

-BISTABLE
SWITCH
PSEUDO- MAGNETIC -ENGINEERED -MOLECULAR
DEVICE TYPES DRAM NOR FLASH SPIN- TUNNEL OUM TUNNEL BARRIER SET NEMS
VALVE JUNCTION -NANOCRYSTAL -SPIN BASED
MOLECULAR
DEVICES

Logic

S INGLE R APID SINGLE QU ANTUM

R ESONANT TUNNELING N ANOTUBE
D EVICE E LEC TR ON Q UANTUM F LUX C ELLULAR M OLEC ULAR D EV ICES
D IODE FET D EVICES
T RANSISTOR L OGIC A UTOMATA
Josephson
Junction -Electronic QCA 2-terminal and
TY PES 3-terminal 3-terminal FET
+inductance -M agnetic QCA 3-terminal
loop
Metrology & Molecular Electronics

James Heath, Fraser Stoddart, and Anthony Pease

Metrology & Molecular Electronics
A

Paul Weisss Group STM of Conductance Switching

 Nanowire Transistors and Interconnect
5 nm layer of Ge on top of 10 nm p-Si core diameter
4 nm SiOx & 10 nm i- Ge layer

500 nm

L.J. LAUHON, M.S. GUDIKSEN, D. WANG

& CHARLES M. LIEBER
Nature 420, 57 - 61 (2002)
Conclusions

There are many opportunities for the Physics

Community in the area of future IC
technology

Nanoelectronics is here!

Metrology is a Key Enabler!

Use of HRTEM for Calibration
High Resolution TEM (Phase Contrast)
has a ~ 10% error for Thickness Determination Due to Cs

Specimen Oxide Oxide

Specimen Cs %
Thickness Defocus Model Measured
Tilt (mrad) (mm) Error
A Thickness Thickness
154 0 -425 0.5 10.56 9.84 -6.8
154 0 -156 0.5 10.56 11.4 8
154 0 -20 0.5 10.56 10.44 -1.1
154 12.6 -425 0.5 10.56 9.12 -13.6
154 25 -425 0.5 10.56 10.68 1.1
154 0 -425 0.5 10.56 8.88 -15.9

HRTEM Image Simulations for Gate Oxide Metrology

S. Taylor, J. Mardinly, M.A. OKeefe, and R. Gronsky

Characterization and Metrology for ULSI Technology 2000