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A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Yonah uFCPGA with Intel
3
Calistoga_GM/PM+ICH7-M core logic 3

2006-05-19
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 1 of 40
A B C D E
A B C D E

Compal confidential
File Name : LA-3341P
ZZZ

1
PCB Thermal Sensor Mobile Yonah 1

ADM1032 uFCBGA-479/uFCPGA-478 CPU


page 4
page 4, 5, 6
Clock Generator
Fan Control H_A#(3..31)
FSB ICS 954306
page 4
H_D#(0..63) 533/667MHz

page 15

DDR2 -400/533/667 DDR2-SO-DIMM X2


LVDS Panel Intel Calistoga GMCH BANK 0, 1, 2, 3 page 13,14
Interface page 16
PCBGA 1466 Dual Channel
page 7, 8, 9, 10,11,12
CRT & TV OUT
2
page 17 Mini-PCIE Card 2

page 27
DMI

PCIE x3

RTC CKT. USB2.0 USB conn X3


page 29
Intel ICH7-M AC-LINK
page 31
PCI BUS
mBGA-652 BT Conn
3.3V 33 MHz Reserved
page 31
Power On/Off CKT. page 18, 19, 20, 21
page 42

10/100 LAN MO DEM


Audio CKT AMOM page 29

DC/DC Interface CKT. RealTek 8100CL LPC BUS


page 26
AMOM page 28
3
page 38 AMP & Audio Jack 3

Power Circuit DC/DC SATA HDD


RJ45 CONN
page 48~56 page 35 ENE KB910/L Connector x2
page 22
page 34 page 31

PATA CDROM SPR CONN.


Touch Pad Int.KBD Connector
page 32 page 32 page 22
*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
BIOS *SPDIF CONN
page 35 *DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1
4 4

page 46

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 2 of 40
A B C D E
A

Voltage Rails

+5VS
power
plane +3VS
+2.5VS
+B
+1.5VS
LDO3 +5VALW +1.8V
+0.9VS
LDO5 +3VALW +5V
+CPU_CORE
+VCCP
State

S0 O O O O

S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X

O MEANS ON
X MEANS OFF

1 1

PCI Devices
EXTERNAL IDSEL# REQ/GNT# PIRQ

CARD BUS & 1394 AD22 2 C,D,E,G

RealTekK 8100CL AD24 1 E

Load BOM check item


1.U31 GM/PM/GML part number
2.U6 ICH7 part number

BOM: 43144132L01 (GM)


43144132L02 (GML)

Jump-Short:
PJP4,PJP6,PJP7,PJP8,PJP10,PJP12,PJP14,PJP18,PJP19,PJP20,PJP25

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 3 of 40
A
5 4 3 2 1

+VCCP

This shall place near CPU


ITP_TDI R6 1 2 56_0402_5%
<7> H_A#[3..31] H_D#[0..63] <7>
JP16A ITP_TMS R3 1 2 56_0402_5%

H_A#3 J4 E22 H_D#0 ITP_TDO R2 1 2 56_0402_5%


H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 ITP_BPM#5 R1 56_0402_5%
M3 A5# D2# E26 1 2
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 ITP_TRST# R4 56_0402_5%
M1 A7# D4# F23 1 2
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 ITP_TCK R5 56_0402_5%
J1 A9# D6# E25 1 2
D H_A#10 H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10
H_A#14 A13# D10# H_D#11
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12 ITP_DBRESET# R181 1 2 @ 200_0402_5% PAD T27
H_A#16 A15# D12# H_D#13
R1 A16# D13# F26
H_A#17 Y2 K22 H_D#14 ITP_BPM#0 PAD T5
H_A#18 A17# D14# H_D#15 ITP_BPM#1 T4
U5 A18# D15# H25 PAD
H_A#19 R3 N22 H_D#16 ITP_BPM#2 PAD T3
H_A#20 A19# D16# H_D#17 ITP_BPM#3 T1
W6 A20# D17# K25 PAD
H_A#21 U4 P26 H_D#18 ITP_BPM#4 PAD T2
H_A#22 A21# D18# H_D#19
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20
H_A#24 A23# D20# H_D#21
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26
H_A#27
T3
W3
A25#
A26#
D22#
D23# M23
P25
H_D#23
H_D#24
Thermal Sensor ADM1032AR
H_A#28 A27# D24# H_D#25 +3VS
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26
H_A#30 A29# D26# H_D#27
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28 2
<7> H_REQ#[0..4] A31# D28#
L26 H_D#29 C598
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31 0.1U_0402_16V4Z
H_REQ#2 REQ1# D31# H_D#32 1
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 U30
H_REQ#4 REQ3# D33# H_D#34 EC_SMC_2
L5 REQ4# D34# V24 1 VDD SCLK 8
V26 H_D#35
H_ADSTB#0 D35# H_D#36 H_THERMDA EC_SMD_2
<7> H_ADSTB#0 L2 ADSTB0# D36# W25 2 D+ SDATA 7
H_ADSTB#1 V4 U23 H_D#37 C592
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38 1 2 H_THERMDC 3 6
C D38# H_D#39 D- ALERT# C
D39# U22
AB25 H_D#40 2200P_0402_50V7K THERM# 4 5
D40# H_D#41 THERM# GND
D41# W22
Y23 H_D#42 R458
CLK_CPU_BCLK A22 D42# H_D#43 ADM1032AR_SOP8
<15> CLK_CPU_BCLK BCLK0 D43# AA26 +3VS 1 2
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45 10K_0402_5%
D45# Y22 Address:100_1100
AC26 H_D#46
D46# H_D#47 EC_SMC_2
D47# AA24 <31> EC_SMC_2
H_ADS# H1 AC22 H_D#48 EC_SMD_2
<7> H_ADS# ADS# D48# <31> EC_SMD_2
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53
<7> H_DRDY# DRDY# D53#
R17 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56
+VCCP
<7> H_LOCK#
H_LOCK#
H_RESET#
H4
B1
IERR#
LOCK#
D56#
D57# AD24
AE21
H_D#57
H_D#58
FAN control +5VS
<7> H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60 C765 1
<7> H_RS#[0..2] D60# AE25 2 10U_1206_16V4Z
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62 U40
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63 1 8
H_TRDY# RS2# D63# VEN GND
<7> H_TRDY# G2 TRDY# 2 VIN GND 7
FAN1 3 6
H_DINV#0 VO GND
DINV0# J26 H_DINV#0 <7> <31> EN_FAN1 4 VSET GND 5
M26 H_DINV#1
DINV1# H_DINV#1 <7>
ITP_BPM#0 AD4 V23 H_DINV#2 G993P1UF_SOP8
BPM0# DINV2# H_DINV#2 <7>
ITP_BPM#1 AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 <7>
ITP_BPM#2 AD1
B ITP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] <7>
H23 H_DSTBN#0
ITP_DBRESET# C20 DSTBN0# H_DSTBN#1
<20> ITP_DBRESET# DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
<7> H_DBSY# DBSY# DSTBN2# +5VS +3VS
H_DPSLP# B5 AD23 H_DSTBN#3
<19> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0
<19,39> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
<7> H_DPWR# DPWR# DSTBP1#
ITP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<39> H_PROCHOT# PRDY# DSTBP2#

2
ITP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
+VCCP 1 R18 2 H_PROCHOT# D21
PROCHOT# 1SS355_SOD323
R551
75_0402_5% 10K_0402_5%
H_PW RGOOD D6 D28
<19> H_PWRGOOD H_CPUSLP# PWRGOOD JP30
D7

1
<7> H_CPUSLP# ITP_TCK SLP# FAN1
AC5 TCK 1
ITP_TDI AA6 A6 H_A20M#
TDI A20M# H_A20M# <19> 2

1000P_0402_50V7K

C763 10U_0805_10V4Z
ITP_TDO AB3 A5 H_FERR#
TDO FERR# H_FERR# <19> 3

1
R456 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# 1 1
TEST1 IGNNE# H_IGNNE# <19>
R455 1 2 51_0402_5% TEST2 D25 B3 H_INIT# ACES_85205-0300
TEST2 INIT# H_INIT# <19>
ITP_TMS AB5 C6 H_INTR
TMS LINT0 H_INTR <19>
ITP_TRST# AB6 B4 H_NMI D22
TRST# LINT1 H_NMI <19> 2 2
LEGACY CPU BAS16_SOT23
THERMAL

C761
H_THERMDA A24 D5 H_STPCLK#
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# <19>
A25 A3 H_SMI# <19>

2
H_THERMTRIP# C7 THERMDC SMI#
<7,19> H_THERMTRIP# THERMTRIP#
H_THERMDA, H_THERMDC routing together.
FOX_PZ47903-2741-42_YONAH
Trace width / Spacing = 10 / 10 mil <31> FAN_SPEED1
1
C762
1000P_0402_50V7K
A +VCCP 2 A

+VCCP
1

R437
R457 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R436 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2005/03/10 2006/03/10 Title


Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E

H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# <20>
C

Q35 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
@ MMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 4 of 40
5 4 3 2 1
5 4 3 2 1

+CPU_CORE
Length match within 25 mils JP16B JP16C
D D
The trace width 18 mils space VCCSENSE
<39> VCCSENSE AF7 VCCSENSE VSS AB26 AE18 VCC VSS K1
7 mils <39> VSSSENSE VSSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
VSS AD25 AB15 VCC VSS M2
VSS AE26 AA15 VCC VSS N1
+VCCP B26 AB23 AD15 T1
+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
+VCCP K6 VCCP VSS AF24 AF15 VCC VSS V2
1

+1.5vs is a power source equired 1 1


J6
M6
VCCP VSS AE23
AA22
AE15
AB14
VCC VSS W1
A26
VCCP VSS VCC VSS

C586

C587
V_CPU_GTLREF
R454
1K_0402_1%
by the PL clock generator on the N6 VCCP YONAH VSS AD22 AA13 VCC VSS D26
T6 VCCP VSS AC21 AD14 VCC VSS C25
processorsilicon R6 AF21 AC13 F25
2

2 2 VCCP VSS VCC VSS


K21 VCCP VSS AB19 AF14 VCC VSS B24
J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
1

N21 AC19 AA12 E24

R451
T21
VCCP
VCCP
VSS
VSS AF19 AD12
VCC
VCC
YONAH VSS
VSS B21

2K_0402_1%
+VCCP is the FSB rail of the R21
V21
VCCP VSS AE19
AB16
AC12
AF12
VCC VSS C22
F22
VCCP VSS VCC VSS

POWER, GROUNG, RESERVED SIGNALS AND NC


processor and GMCH W21 AA16 AE12 E21
2

VCCP VSS VCC VSS


V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
Close to CPU pin AD26 H_PSI# AE6
VSS AE16
AB13
AA9
AD10
VCC VSS C19
F19
<39> H_PSI# PSI# VSS VCC VSS
within 500mils. CPU_VID0 VSS AA14 AD9 VCC VSS E19
<39> CPU_VID0 AD6 VID0 VSS AD13 AC10 VCC VSS B16
CPU_VID1 AF5 AC14 AC9 A16
<39> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<39> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<39> CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C <39> CPU_VID4 VID4 VSS VCC VSS C
CPU_VID5 AF2 AA11 AE9 E16
<39> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<39> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
+CPU_CORE
133 0 0 1 VSS AF11 AD7 VCC VSS D13
R442 V_CPU_GTLREF AD26 AE11 AC7 C14
100_0402_1% GTLREF VSS VCC VSS
VSS AB8 B20 VCC VSS F13
1 2 VCCSENSE CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1
R441
1 <15> CPU_BSEL1
CPU_BSEL2
B23
C21
BSEL1 VSS AD8
AC8
F20
E20
VCC VSS B11
A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
100_0402_1% AF8 B18 D11
VSSSENSE COMP0 VSS VCC VSS
1 2 R26 COMP0 VSS AE8 B17 VCC VSS C11
COMP1 U26 AA5 A18 F11
COMP2 COMP1 VSS VCC VSS
U1 COMP2 VSS AD5 A17 VCC VSS E11
COMP3 V1 AC6 D18 B8
COMP3 VSS VCC VSS
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+CPU_CORE E7 VCC VSS AC3 C17 VCC VSS C8
Close to CPU pin AB20
AA20
VCC VSS AF3
AE4
F18
F17
VCC VSS F8
E8
VCC VSS VCC VSS
within 500mils. AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25


0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25


should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R453

R452

R439

R438

AA17 C5 C15 T26


mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS


AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 5 of 40
5 4 3 2 1
5 4 3 2 1

D +CPU_CORE D

1 1 1 1 1 1 1 1
Place these capacitors on L8 C13 C14 C28 C23 C34 C18 C19 C30
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C33 C39 C42 C35 C38 C41 C2 C48
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C40 C32 C27 C22 C16 C11 C36 C31
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

C C
+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C26 C21 C15 C10 C1 C6 C24 C12
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

Mid Frequence Decoupling

+CPU_CORE
<6/19> Remove C578 820u Cap
820U_E9_2_5V_M_R7
330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

@330U_V_2.5VK_R9
1 1 1 1 1 1 ESR <= 1.5m ohm
Capacitor > 1980uF
@ C8
C47

C583

C576

C584

C585
+ + + + + + North Side Secondary
South Side Secondary
2 2 2 2 2 2
B B
<6/19> Remove C37 330u Cap

+VCCP

1
1 1 1 1 1 1
C591 + Place these inside
C43 C44 C45 C3 C4 C5 socket cavity on L8
220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 6 of 40
5 4 3 2 1
5 4 3 2 1

<4> H_D#[0..63] H_A#[3..31] <4> Description at page15.


U31A U31B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <20> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <20> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <20> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T6
HD4# HA7# <20> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T9
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 D
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T7
HD7# HA10# <20> DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <20> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T12
HD9# HA12# <20> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <20> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T10
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <20> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <20> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T8
HD15# HA18# <20> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T16
HD16# HA19# <20> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T14
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <20> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <20> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <20> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <20> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 CLK_MCH_DREFCLK#

CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# <15>
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 CLK_MCH_DREFCLK
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK <15>
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 MCH_SSCDREFCLK# MCH_SSCDREFCLK# <15>
H_D#31 T5 M_CLK_DDR#1 AT1 D41 MCH_SSCDREFCLK
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP MCH_SSCDREFCLK <15>
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 CLKREQB#
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ# CLKREQB# <15>
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 T17 PAD M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 T11 PAD AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 M_ODT0 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] <4> <13> M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V M_ODT1
AB4 HD49# HDSTBP#0 K3 <13> M_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R40 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R41 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 V_DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 T32


HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32


HD59# RESERVED2
R461

R462

H_D#60 AB5 <20> PM_BMBUSY# PM_BMBUSY# G28 F3


H_D#61 HD60# H_RESET# PM_EXTTS#0 PM_BMBUSY# RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# <4> <13,14> PM_EXTTS#0 F25 PM_EXTTS0# RESERVED4 F7

RESERVED
PM
H_D#62 AD4 E8 H_ADS# <20,39> DPRSLPVR DPRSLPVR H26 AG11
HD62# HADS# H_ADS# <4> PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,19> H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# ICH_POK PM_THERMTRIP# RESERVED6


HDPWR# J9 H_DPWR# <4> <20,31> ICH_POK AH33 PWROK RESERVED7 H7
H8 H_DRD Y# 2 1 PLTRST_R# AH34 J19
HDRDY# H_DRDY# <4> <18,22,24> PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R98 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
H_VREF K13 D4 H_HITM# <18> MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# <4> ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# <4> RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# <4>
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4>
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# <4>
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# <4>
24.9_0402_1%

24.9_0402_1%

V_DDR_MCH_REF
1

trace width and


R466

R464

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 spacing is 20/20.
D6 H_RS#2
HRS2#
H_RS#[0..2] <4>
2

CALISTOGA_FCBGA1466~D +1.8V

1
R483

Layout Note: 100_0402_1% +3VS

2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / V_DDR_MCH_REF
<13,14> V_DDR_MCH_REF
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 10/20.


1 1 R481 R71
+VCCP +VCCP 10K_0402_5%
C663

100_0402_1% PM_EXTTS#0 2 1
+VCCP
2

2
221_0603_1%

221_0603_1%

R79
1

1
100_0402_1%

@ 10K_0402_5%
1

R38

R463

DPRSLPVR 1 2
R45

A A
2

H_SWNG0 H_SWNG1
2

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1
1

200_0402_1%

R37

R465

1
R42

C87

C82

C601

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.


2

2
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 7 of 40
5 4 3 2 1
5 4 3 2 1

D D

U31D U31E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B


DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
<13> DDR_A_DQS#[0..7] AN20 DDR_A_D27 <14> DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
<13> DDR_A_MA[0..13] SA_DQ38 AL14 <14> DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
<13> DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 <14> DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
<13> DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 <14> DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
<13> DDR_A_WE# SA_WE# SA_DQ58 <14> DDR_B_WE# SB_WE# SB_DQ58
T18 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T13 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T19 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T15 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 8 of 40
5 4 3 2 1
5 4 3 2 1

D D

R89 +1.5VS_PCIE
U31C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38

EXP_RXN0 F34
LVDSA0+ B37 G38
<16> LVDSA0+ LVDSA1+ LA_DATA0 EXP_RXN1
<16> LVDSA1+ B34 LA_DATA1 EXP_RXN2 H34
LVDSA2+ A36 J38
<16> LVDSA2+ LA_DATA2 EXP_RXN3
EXP_RXN4 L34
LVDSA0- C37 M38
<16> LVDSA0- LVDSA1- LA_DATA#0 EXP_RXN5
<16> LVDSA1- B35 LA_DATA#1 EXP_RXN6 N34
LVDSA2- A37 P38
<16> LVDSA2- LA_DATA#2 EXP_RXN7
EXP_RXN8 R34
LVDSB0+ F30 T38
<16> LVDSB0+ LB_DATA0 EXP_RXN9
LVDSB1+

LVDS
<16> LVDSB1+ D29 LB_DATA1 EXP_RXN10 V34
LVDSB2+ F28 W38
<16> LVDSB2+ LB_DATA2 EXP_RXN11
EXP_RXN12 Y34
LVDSB0- G30 AA38
<16> LVDSB0- LB_DATA#0 EXP_RXN13
LVDSB1- D30 AB34
<16> LVDSB1- LB_DATA#1 EXP_RXN14
LVDSB2- F29 AC38
<16> LVDSB2- LB_DATA#2 EXP_RXN15
LVDSAC+ A32 D34
<16> LVDSAC+ LA_CLK EXP_RXP0
LVDSAC- A33 F38
<16> LVDSAC- LVDSBC+ LA_CLK# EXP_RXP1
<16> LVDSBC+ E26 LB_CLK EXP_RXP2 G34
LVDSBC- E27 H38
<16> LVDSBC- LB_CLK# EXP_RXP3
J34

PCI-EXPRESS GRAPHICS
EXP_RXP4
D32 LBKLT_CTL EXP_RXP5 L38
C GMCH_ENBKL C
<16> GMCH_ENBKL J30 LBKLT_EN EXP_RXP6 M34
H30 LCTLA_CLK EXP_RXP7 N38
H29 LCTLB_DATA EXP_RXP8 P34
EDID_CLK_LCD G26 R38
<16> EDID_CLK_LCD LDDC_CLK EXP_RXP9
EDID_DAT_LCD G25 T34
<16> EDID_DAT_LCD LDDC_DATA EXP_RXP10
<16> GMCH_LVDDEN GMCH_LVDDEN F32 V38
LVDD_EN EXP_RXP11
2 1 B38 LIBG EXP_RXP12 W34
R482 1.5K_0402_1% C35 Y38
LVBG EXP_RXP13
C33 LVREFH EXP_RXP14 AA34
C32 LVREFL EXP_RXP15 AB38

EXP_TXN0 F36
<17> TV_COMPS TV_COMPS A16 G40
TV_LUMA TVDAC_A EXP_TXN1
<17> TV_LUMA C18 TVDAC_B EXP_TXN2 H36
<17> TV_CRMA TV_CRMA A19 J40
TVDAC_C EXP_TXN3

TV
EXP_TXN4 L36
2 R58 1 J20 TV_IREF EXP_TXN5 M40
4.99K_0402_1% N36
EXP_TXN6
B16 TV_IRTNA EXP_TXN7 P40
B18 TV_IRTNB EXP_TXN8 R36
B19 TV_IRTNC EXP_TXN9 T40
EXP_TXN10 V36
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 TV_DCONSEL0 EXP_TXN12 Y36
EXP_TXN13 AA40
EXP_TXN14 AB36
EXP_TXN15 AC40
3VDDCCL C26
<17> 3VDDCCL DDCCLK
CRT

3VDDCDA C25 D36


<17> 3VDDCDA DDCDATA EXP_TXP0
EXP_TXP1 F40
<17> CRT_VSYNC CRT_VSYNC H23 G36
CRT_HSYNC VSYNC EXP_TXP2
<17> CRT_HSYNC G23 HSYNC EXP_TXP3 H40
B CRT_B B
<17> CRT_B E23 BLUE EXP_TXP4 J36
D23 BLUE# EXP_TXP5 L40
CRT_G C22 M36
<17> CRT_G GREEN EXP_TXP6
B22 GREEN# EXP_TXP7 N40
CRT_R A21 P36
<17> CRT_R RED EXP_TXP8
B21 RED# EXP_TXP9 R40
EXP_TXP10 T36
EXP_TXP11 V40
2 R65 1 J22 CRT_IREF EXP_TXP12 W36
255_0402_1% Y40
EXP_TXP13
EXP_TXP14 AA36
EXP_TXP15 AB40

CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 9 of 40
5 4 3 2 1
5 4 3 2 1

+VCCP
2

D5 +2.5VS
D D
@ CH751H-40_SC76 U31H
1 1

+VCCP H22 1 2
VCC_SYNC C162
R80 +2.5VS AC14 0.1U_0402_16V4Z
VTT0
AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS
@ 10_0402_5% W14 C30
VTT2 VCCTX_LVDS1 +1.5VS_PCIE R490
V14 A30
2

VTT3 VCCTX_LVDS2 0_0805_5%


T14
R14
VTT4
VTT5 VCC3G0 AB41 W=40 mils 2 1 +1.5VS

10U_1206_6.3V6M

10U_1206_6.3V6M
P14 VTT6 VCC3G1 AJ41
+1.5VS

220U_D2_4VM
N14 VTT7 VCC3G2 L41 1
M14 VTT8 VCC3G3 N41 1 1

C682
L14 R41 +
VTT9 VCC3G4
2

+2.5VS

C666

C665

0.1U_0402_16V4Z
AD13 VTT10 VCC3G5 V41
220U_D2_4VM

D19 AC13 Y41


VTT11 VCC3G6 2 2 2
AB13 VTT12 1
@ CH751H-40_SC76 1 AA13 AC33 +1.5VS_3GPLL
VTT13 VCCA_3GPLL

C225
Y13 G41 +2.5VS
1 1

VTT14 VCCA_3GBG
C610

+ W13 H41
VTT15 VSSA_3GBG 2 +1.5VS_DPLLA L28 +1.5VS_DPLLB L29
V13 VTT16
R520 +3VS U13 L7 BLM11A601S_0603 MBK160808_0603 MBK160808_0603
2 VTT17 +2.5VS_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5VS 2 1 +1.5VS 2 1 +1.5VS

2200P_0402_50V7K
@ 10_0402_5% R13 F21
VTT19 VCCA_CRTDAC1

0.1U_0402_16V4Z

330U_V_2.5VK_R9

0.1U_0402_16V4Z

330U_V_2.5VK_R9
0.1U_0402_16V4Z
N13 G21 close pin G41
2

VTT20 VSSA_CRTDAC2
M13 VTT21 1 1 1 1
L13 VTT22 1 1

C115

C116

C138

C616

C226

C645
+ +
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA CRTDAC: Route caps within
AA12 VTT24 VCCA_DPLLB C39 +1.5VS_DPLLB
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
2 2 250mil of Alviso. Route FB
W12 2 2 2 2
VTT26 within 3" of Calistoga
V12 VTT27
U12 VTT28 VCCA_LVDS A38 +2.5VS
T12 VTT29 VSSA_LVDS B39
C
R12 VTT30 C
P12 +2.5VS
VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
+3VS_TVDACC +3VS +3VS_TVDACB +3VS +3VS_TVDACA +3VS

0.01U_0402_16V7K
4.7U_0805_10V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z
L12 VTT34 VCCA_TVBG H20 +3VS_TVBG
R11 G20 R52 R55 R44
VTT35 VSSA_TVBG
1 1 P11 VTT36 2 1 2 1 2 1
C612

C613

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
N11 1 1 0_0805_5% 0_0805_5% 0_0805_5%
VTT37

C160

C215

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19 1 1 1 1 1 1
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB 2 2

C110

C111

C114

C109

C107

C106
N10 VTT41 VCCA_TVDACB1 D20
M10 VTT42 VCCA_TVDACC0 E20 +3VS_TVDACC 2 2 2 2 2 2
P9 VTT43 VCCA_TVDACC1 F20
N9 VTT44
M9 VTT45 close pin A38
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48
M8 +3VS_TVBG +3VS
VTT49 R39
P7 VTT50 VCCD_LVDS0 A28
N7 VTT51 VCCD_LVDS1 B28 2 1
M7 C28 0_0805_5%
VTT52 VCCD_LVDS2

2200P_0402_50V7K

0.1U_0402_16V4Z
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS_TVDAC 1 1
M6 VTT55 VCCDQ_TVDAC H19

C117
MCH_A6 A6 VTT56
0.47U_0603_10V7K

C112
R5 VTT57 VCCHV0 A23 +3VS 2 2
P5 VTT58 VCCHV1 B23
0.1U_0402_16V4Z

10U_1206_6.3V6M

1 N5 VTT59 VCCHV2 B25


C607

M5 VTT60 1 1
P4 VTT61 VCCAUX0 AK31
N4 VTT62 VCCAUX1 AF31
2
C124

C615

M4 VTT63 VCCAUX2 AE31


2 2
R3 VTT64 VCCAUX3 AC31
B P3 AL30 B
N3
VTT65
VTT66
VCCAUX4
VCCAUX5 AK30 PCI-E/MEM/PSB PLL decoupling
0.22U_0603_10V7K

M3 VTT67 VCCAUX6 AJ30


R2 AH30 +1.5VS
VTT68 VCCAUX7
P2 VTT69 VCCAUX8 AG30
+1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.1U_0402_16V4Z

1 M2 AF30 R99 R46


VTT70 VCCAUX9
C81

MCH_D2 D2 AE30 0_0603_5% 0_0603_5%


VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1 2 1 2 1
0.22U_0603_10V7K

2200P_0402_50V7K
0.1U_0402_16V4Z

10U_1206_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C163

1 P1 VTT74 VCCAUX13 AG29


C597

N1 VTT75 VCCAUX14 AF29 1 1 1 1 1 1


2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

C174

C248

C280

C113

C614

C105
VCCAUX16 AD29
2
1 VCCAUX17 AC29
2 2 2 2 2 2
C596

VCCAUX18 AG28
VCCAUX19 AF28
AE28 @ @
2 VCCAUX20
VCCAUX21 AH22
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
+1.5VS_MPLL R459 +1.5VS_HPLL R460
AF13 VCCAUX36 VCCAUX27 P19
AE13 P16 0_0603_5% 0_0603_5%
+1.5VS VCCAUX37 VCCAUX28
AF12 VCCAUX38 VCCAUX29 AH15 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
AE12 VCCAUX39 VCCAUX30 P15

0.1U_0402_16V4Z

10U_1206_6.3V6M

0.1U_0402_16V4Z

10U_1206_6.3V6M
AD12 VCCAUX40 VCCAUX31 AH14

1 1 1 1
CALISTOGA_FCBGA1466~D

C604

C593

C605

C594
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 10 of 40
5 4 3 2 1
5 4 3 2 1

Strap Pin Table


CFG[3:17] have internal pull up

U31F CFG[19:18] have internal pull down


+VCCP +1.5VS +VCCP U31G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_10V7K

0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C669
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C668
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34


2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30
C86

C85
C164

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG6 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 10 = 1.05V*(Default)
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG10 CFG18 01 = 1.5V
1U_0603_10V4Z
10U_1206_6.3V6M

10U_1206_6.3V6M

T25 W17 T30 AJ27


P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C83

C84
C222

C128
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C173

C600

C139

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
220U_D2_4VM

AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22


V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22

C125
+ R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
C595

AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22


2 R48
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 <7> CFG5 1 2 @ 2.2K_0402_5%
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R54 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 <7> CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R51 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 <7> CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R47 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 <7> CFG11

470U_V_2.5VK_R9
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19

10U_1206_6.3V6M

10U_1206_6.3V6M
R20 N26 AW19 R49 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 <7> CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
V19 AE26 N25 AU19 1 1 R50 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 <7> CFG13

C599
U19 AE25 M25 AT19 +
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62

C609

C641
220U_D2_4VM

T19 AE24 L25 AR19 R53 1 2 @ 2.2K_0402_5%


VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 <7> CFG16
1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P24 VCC64 VCC_SM64 AP19
2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
+ AB18 AE21 M24 AJ19
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
C606

AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18


Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_10V7K
AC22 AW15 R74 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R82 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R87 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C104
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12


M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C603

C602

AB20 VCC89 VCC_SM89 AY8


Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 11 of 40
5 4 3 2 1
5 4 3 2 1

U31I U31J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 12 of 40
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14>

<8> DDR_A_D[0..63] JP21

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
<8> DDR_A_DM[0..7] VSS DQ4

C368

C369
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<8> DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,14>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C130

C129

C131

C204

C206

C180

C143

C193

C187
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120


NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D39
DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C643

C642

C640

C639

C192

C175

C166

C630

C629

C158

C145

C136

C628

133 134 DDR_A_D34


DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9VS NC,TEST CK1 M_CLK_DDR1 <7>
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168
RP25 RP27 56_0404_4P2R_5%
Pla ce these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP41,all 171 172
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D54 173 DQ50 DQ54 174 DDR_A_D51
DDR_A_D50 175 176 DDR_A_D55
RP24 56_0404_4P2R_5% RP15 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D61 179 180 DDR_A_D57
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D60 181 DQ57 DQ61 182 DDR_A_D56
183 VSS VSS 184
RP6 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_RAS# DM7 DQS7#
1 4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA12 DDR_A_D59 189 190
DDR_A_D58 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP23 56_0404_4P2R_5% RP12 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA4 <14,15> CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA2 CLK_SMBCLK 197 198
<14,15> CLK_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP22 56_0404_4P2R_5% RP9 56_0404_4P2R_5%

1
10K_0402_5%

10K_0402_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1
DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C80 FOX_ASOA426-M4R-TR

R33

R35
A A
CONN@
RP21 56_0404_4P2R_5% RP3
DDR_CS1_DIMMA# 2
56_0404_4P2R_5% 0.1U_0402_16V4Z
2
SO-DIMM A
3 4 1 M_ODT0
REVERSE

2
M_ODT1 1 4 3 2 DDR_A_MA13

56_0404_4P2R_5% RP18 56_0404_4P2R_5%


4 1 DDR_CKE1_DIMMA Top side
3 2 DDR_A_MA11 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 13 of 40
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13>
<8> DDR_B_DM[0..7] JP24

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
<8> DDR_B_MA[0..13] 5 DQ0 DQ5 6

C366

C367
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C132

C214

C205

C159

C157

C169

C142

C141

C140
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
<8> DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13


<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C156

C146

C137

C202

C179

C170

C165

C147

C144

C133

C191

C176

C168

DDR_B_DQS#4 129 130 DDR_B_DM4


DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9VS 163 164 M_CLK_DDR2
closely JP42,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP10 RP16 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP7 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS#0 1 4 4 1 DDR_B_MA11 177 178
DDR_B_MA10 DDR_CKE3_DIMMB DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP8 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_BS#1 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP5 56_0404_4P2R_5% RP14 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_CS2_DIMMB# 1 4 4 1 DDR_B_MA6 193 194 DDR_B_D63
DDR_B_RAS# DDR_B_MA7 CLK_SMBDATA VSS DQ63
2 3 3 2 <13,15> CLK_SMBDATA 195 SDA VSS 196
CLK_SMBCLK 197 198 R32
<13,15> CLK_SMBCLK SCL SAO
RP4 56_0404_4P2R_5% RP11 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA2

1
10K_0402_5%
DDR_B_WE# 2 3 3 2 DDR_B_MA4 1 10K_0402_5%

R34
A RP1 C79 FOX_ASOA426-M4R-TR A
56_0404_4P2R_5% RP2 56_0404_4P2R_5% CONN@
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 DDR_B_MA13
M_ODT2
0.1U_0402_16V4Z
2
SO-DIMM B
1 4 3 2
STANDARD

2
56_0404_4P2R_5% RP19
4 1 DDR_B_BS#2 Bottom side
3 2 DDR_CKE2_DIMMB

56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 14 of 40
5 4 3 2 1
5 4 3 2 1

FSLC FSLB FSLA CPU SRC PCI +3VS +CK_VDD_MAIN1


CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
+3VS 1 2
R299 R323 R324 0_0805_5% 1 1 1 1 1 1 1
0 0 1 133 100 33.3 C456 C422 C431 C440 C450 C441 C430
2.2K_0402_5% 2.2K_0402_5%
Q12 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2N7002_SOT23 2 2 2 2 2 2 2
0 1 1 166 100 33.3
CLK_SMBDATA

S
<20,24> ICH_SMBDATA 1 3
Table : ICS954306 +CK_VDD_MAIN2

G
2
D D
FSB Frequency Selet: +3VS 1 2 1 2 +CK_VDD_REF
+3VS R174 0_0805_5% 1 1 1 R188
C416 C418 C417 1_0805_1%
Stuff CLK_Ra CLK_Rb CLK_Rc 1 2 +CK_VDD_48

2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R187

G
CPU Driven 2 2 2 2.2_0805_1%
CLK_SMBCLK
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf<20,24> ICH_SMBCLK 1 3

S
2N7002_SOT23
Change Crustal to SJ100002F10
Stuff CLK_Rd CLK_Re CLK_Rf Q15
533MHz C419 2 1 22P_0402_50V8J
+CK_VDD_MAIN1

1
No Stuff CLK_Ra CLK_Rb CLK_Rc U13 Place crystal within
Y2
CLK_XTAL_IN 14.31818MHZ_20P_1BX14318BE1A
500 mils of CK410
16 VDD X1 57
Stuff CLK_Rd CLK_Rf
Place near U54

2
+CK_VDD_48 10 56 CLK_XTAL_OUT 2 1
VDD48 X2 C421 22P_0402_50V8J
667MHz 1
Place these components
No Stuff CLK_Ra CLK_Rb CLK_Rc C424 5 VDDPCI
28 1 2
CLK_Re 0.1U_0402_16V4Z
2
24 VDDSRC
SATACLKT R305 0_0402_5% near each pin within 40
29 1 2
+VCCP
33 VDDSATA
SATACLKC R311 0_0402_5% mils.
1
C425 41 52 CPU_BCLK 1 2 CLK_CPU_BCLK
VDDSRC CPUCLKT0 CLK_CPU_BCLK <4>
R239 10_0402_5%
2

0.1U_0402_16V4Z 50 51 CPU_BCLK# 1 2 CLK_CPU_BCLK# CLK_CPU_BCLK 2 1


2 VDDCPU CPUCLKC0 CLK_CPU_BCLK# <4>
@ R232 R247 10_0402_5% R240 @ 49.9_0402_1%
56_0402_5% <6/12> Remove CLK_48M_CB +CK_VDD_REF 55 CLK_CPU_BCLK# 2 1
R237 VDDREF MCH_BCLK CLK_MCH_BCLK R248 @ 49.9_0402_1%
CLK_Rd CPUCLKT1 49 1 2 CLK_MCH_BCLK <7>
8.2K_0402_5% R236 12_0402_5% R254 10_0402_5%
1

FSA 2 1 1 2 <20> CLK_48M_ICH CLK_48M_ICH 2 1 FSA 11 48 MCH_BCLK# 1 2 CLK_MCH_BCLK# CLK_MCH_BCLK 2 1


C MCH_CLKSEL0 <7> FSLA/USB_48MHz CPUCLKC1 CLK_MCH_BCLK# <7> C
R258 10_0402_5% R255 @ 49.9_0402_1%
1 2 R227 FSB 15 CLK_MCH_BCLK# 2 1
<5> CPU_BSEL0 FSLB/TEST_MODE
R231 1K_0402_5% 2 1 +3VS R259 @ 49.9_0402_1%
0_0402_5% <20> CLK_14M_ICH CLK_14M_ICH 2 1 CLKREF1 59 R218 @ 10K_0402_5%
FSLC/TEST_SEL/REF1
1

CLK_Ra R230 33_0402_5% 64 CLKREQA#


*CLKREQA# CLKREQA# <24>
R228
18 SSCDREFCLK 1 2 MCH_SSCDREFCLK MCH_SSCDREFCLK 1 2
LCDCLK_SST/SRCCLKT0 MCH_SSCDREFCLK <7>
@ 1K_0402_5% 2.4K_0402_1%1 2 R266 CLKIREF 46 R257 10_0402_5% R256 @ 49.9_0402_1%
IREF SSCDREFCLK#1 MCH_SSCDREFCLK# MCH_SSCDREFCLK# 1
19 2 MCH_SSCDREFCLK# <7> 2
2

LCDCLK_SSC/SRCCLKC0 R270 10_0402_5% R269 @ 49.9_0402_1%


61 CPU_STOP#
H_STP_CPU# CLK_PCIE_MCARD 1 2
<20> H_STP_CPU#
H_STP_PCI# 8 22 PCIE_MCARD 1 2 CLK_PCIE_MCARD R281 @ 49.9_0402_1%
+VCCP <20> H_STP_PCI# PCI/SRC_STOP# SRCCLKT2 CLK_PCIE_MCARD <24>
CLK_ENABLE# R282 10_0402_5% CLK_PCIE_MCARD#1 2
<39> CLK_ENABLE#
9 23 PCIE_MCARD#1 2 CLK_PCIE_MCARD# R283 @ 49.9_0402_1%
Vtt_PwrGd#/PD SRCCLKC2 CLK_PCIE_MCARD# <24>
R284 10_0402_5% CLK_MCH_3GPLL 1 2
2

CLK_PCI_ICH 2 R229 1 PCI_ICH 7 R287 @ 49.9_0402_1%


<18> CLK_PCI_ICH **SEL_LCDCLK#/PCICLK_F1
R201 33_0402_5% 30 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_MCH_3GPLL# 1 2
SATA1/SRCCLKT4 CLK_PCIE_SATA <19>
R297 10_0402_5% R291 @ 49.9_0402_1%
@ 1K_0402_5% 33_0402_5% 2 1 R920 PCI_LAN 60 31 PCIE_SATA# 1 2 CLK_PCIE_SATA#
<23> CLK_PCI_LAN REF0/PCICLK1 SATA1/SRCCLKC4 CLK_PCIE_SATA# <19>
R304 10_0402_5%
1

FSB 1 2 REQ_SEL 62 2 1 +3VS


MCH_CLKSEL1 <7> *REQ_SEL/PCICLK2
<6/3> PCI_CLK_LAN R226 @ 10K_0402_5%
1 2 R200 +3VS 10K_0402_5%2 1 R216 1 63 CLKREQB# CLK_PCIE_ICH 1 2
<5> CPU_BSEL1 selection (33MHz) *SEL_PCI1/PCICLK3 *CLKREQB# CLKREQB# <7>
R191 1K_0402_5% R295 @ 49.9_0402_1%
0_0402_5% 33_0402_5% 2 1 R215 PCI_EC 2 20 CLK_PCIE_ICH# 1 2
<31> CLK_PCI_EC **SEL_SATA1/PCICLK4 SRCCLKT1
1

CLK_Rb Delete PCIE VGA CLK R302 @ 49.9_0402_1%


@ R199 33_0402_5% 2 1@ R225 PCI_SIO 3 21 CLK_MCH_DREFCLK 1 2
<29> CLK_PCI_SIO **SEL_SATA2/PCICLK5 SRCCLKC1 R245 @ 49.9_0402_1%
0_0402_5% +3VS 100K_0402_5%
1 2 R589 PCI_PCM 6 CLK_MCH_DREFCLK#1 2
PCICLK6 MCH_3GPLL CLK_MCH_3GPLL R252 @ 49.9_0402_1%
CLK_Re 26 1 2 CLK_MCH_3GPLL <7>
2

SRCCLKT3 R288 10_0402_5% CLK_PCIE_SATA 1 2


27 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# R296 @ 49.9_0402_1%
B SRCCLKC3 CLK_MCH_3GPLL# <7> B
CLK_SMBDATA 54 R292 10_0402_5% CLK_PCIE_SATA# 1 2
<13,14> CLK_SMBDATA SDATA R303 @ 49.9_0402_1%
<13,14> CLK_SMBCLK CLK_SMBCLK 53 35 PCIE_ICH 1 2 CLK_PCIE_ICH CLK_CPU_XDP 2 1
SCLK SATA2/SRCCLKT5 CLK_PCIE_ICH <20>
R294 10_0402_5% R279 @49.9_0402_1%
34 PCIE_ICH# 1 2 CLK_PCIE_ICH# CLK_CPU_XDP# 2 1
+VCCP SATA2/SRCCLKC5 CLK_PCIE_ICH# <20>
R301
2 10_0402_5%
1 +3VS R272 @ 49.9_0402_1%
R930 10K_0402_5%
<7> CLK_MCH_DREFCLK CLK_MCH_DREFCLK 1 2 MCH_DREFCLK 13 2 1 CLKREQC#
DOTT_96MHz
2

R246 10_0402_5% @ R273 10K_0402_5%


R202 <7> CLK_MCH_DREFCLK# CLK_MCH_DREFCLK#1 2 MCH_DREFCLK# 14 45 CPU_XDP 1 2 CLK_CPU_XDP
R253 10_0402_5% DOTC_96MHz *CPUCLKT2_ITP/CLKREQC# R278 @ 10_0402_5%
R205 @ 1K_0402_5% 37
8.2K_0402_5% SRCCLKT6
Delete 17" New Card PCIE CLK
1

CLKREF1 2 1 1 2 36
MCH_CLKSEL2 <7> SRCCLKC6
4 GND
1 2 R184
<5> CPU_BSEL2
R177 1K_0402_5% 12 43
0_0402_5% GND SRCCLKT8
1

CLK_Rc 17 GND SRCCLKC8 42 2 1 +3VS


@ R183 R931 10K_0402_5%
58 2 1 CLKREQD#
0_0402_5% GND @ R277 10K_0402_5%
CLK_Rf 47 44 CPU_XDP# 1 2 CLK_CPU_XDP#
2

GNDCPU *CPUCLKC2_ITP/CLKREQD# @ R271 10_0402_5%


LCD clock select Pin44/45 function select 25 39 CLKREQA# C802 1 2 1000P_0402_50V7K
GNDSRC SRCCLKT7
+3VS +3VS +3VS CLKREQB# C803 1 2 1000P_0402_50V7K
40 GNDSRC SRCCLKC7 38 <6/12> Delete 15.4" New Card PCIE CLK
32 CLKREQC# C804 1 2 1000P_0402_50V7K
GNDSATA
1

R235 R233 R312 CLKREQD# C805 1 2 1000P_0402_50V7K


ICS954306_TSSOP64
A 10K_0402_5% @ 10K_0402_5% 10K_0402_5% A
* Internal Pull-Up Resistor
2

CLK_ENABLE# PCI_ICH REQ_SEL ** Internal Pull-Down Resistor


1

R238 R308

10K_0402_5% @ 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
High:Pin18/19 = 100MHz High:Pin44/45 = CLKREQ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
*Low:Pin18/19 = 96MHz *Low:Pin44/45 = CPUCLK2_ITP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3341P
Date: Tuesday, June 20, 2006 Sheet 15 of 40
5 4 3 2 1
A B C D E F G H

LCD Panel & inverter Connector

1 JP2 UMA 1
WL_LED# LVDSAC+ +3VS
+3VS <24,29> WL_LED# 39 40 LVDSAC+ <9>
DISPOFF# LVDSAC-
INVT_PWM 37 38 LVDSAC- <9>
<31> INVT_PWM 35 36

2
R434 DAC_BRIG LVDSA1-
<31> DAC_BRIG 33 34 LVDSA1- <9>
1 2 EDID_CLK_LCD 31 32
LVDSA1+ LVDSA1+ <9> R430
10K_0402_5% EDID_CLK_LCD
<9> EDID_CLK_LCD 29 30
R435 EDID_DAT_LCD LVDSBC+ 4.7K_0402_5%
<9> EDID_DAT_LCD 27 28 LVDSBC+ <9>
1 2 EDID_DAT_LCD LVDSBC-
LVDSBC- <9>
D17

1
10K_0402_5% 25 26 CH751H-40_SC76
+5VS 23 24 LVDSB1- 1 2 DISPOFF#
21 22 LVDSB1- <9> <31> BKOFF#
+3VS LVDSB1+
19 20 LVDSB1+ <9>
LVDSB0+
17 18 LVDSB0+ <9>
LVDSB0- D16
+LCDVDD 15 16 LVDSB0- <9>
LVDSB2+ CH751H-40_SC76
13 14 LVDSB2- LVDSB2+ <9>
11 12 <9> GMCH_ENBKL 1 2
LVDSB2- <9>
9 10

2
LVDSA0-
INVPWR_B+ 7 8 LVDSA0- <9>
LVDSA0+ R431
5 6 LVDSA2- LVDSA0+ <9> 100K_0402_5%
3 4 LVDSA2- <9>
LVDSA2+
1 2 LVDSA2+ <9>

1
ACES_88107-4000G

2 B+ INVPWR_B+ 2

L25 1 2 FBMA-L10-201209-301LMT

@ L24 1 2 FBMA-L10-201209-301LMT
1 1
C806 C807

Delete 17" LVDS Conn JP1 2 2

0.1U_0402_16V4Z 68P_0402_50V8K

3 3

+LCDVDD +5VALW

+LCDVDD +3VS
1

Q33
2

R429 SI2301BDS_SOT23
R428
100_0402_1% 100K_0402_5%

S
1 3

D
1 2

G
2
2N7002_SOT23 0.047U_0402_16V4Z
2
Q32 G
S 1 1 1 1
3

C572 C574 C575


C573
1

4.7U_0805_10V4Z 4.7U_0805_10V4Z
Q31 2 2 2 2
DTC124EK_SC59

<9> GMCH_LVDDEN 2 0.1U_0402_16V4Z


3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 16 of 40
A B C D E F G H
A B C D E

+R_CRT_VCC , +CRTVDD (40mils) NZQA5V6AXV5T1_SOT533-5

+5VS +CRTVDD
+R_CRT_VCC
D1 F1 3 4
2 1 1 2

RB411D_SOT23 1.1A_6VDC_FUSE 1
2
CRT CONNECTOR C582
0.1U_0402_16V4Z
2
1 5
1
EMI 1
JP3
ALLTO_C10510-115A5-L_15P-s
L3 6 D46
MBK2012800YZF 11
CRTR 1 2 CRTL_R 1
<9> CRT_R
L2 7
MBK2012800YZF EMI 12 16
CLOSE TO JP3
CRTG 1 2 CRTL_G 2 17
<9> CRT_G
L1 8
MBK2012800YZF 13
CRTB 1 2 CRTL_B 3
<9> CRT_B

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
+CRTVDD 9

2
75_0402_5%

75_0402_5%

75_0402_5%
1 1 1 1 1 1 14
4
+5VS EMI

R16 4.7K_0402_5%

R443 4.7K_0402_5%
10

R7
R14

R10
C580 15
2 2 2 2 2 2

C29

C20

C25

C17
C9

C7
1 2 5

1
5

1
0.1U_0402_16V4Z U29
R449 @ @ @ Q1 R21
P

OE#

CR THSYNC CRT_HSYNC_R CRT_HSYNCRFL 3V_DDCDA


3 2N7002_SOT23-3

S
<9> CRT_HSYNC 1 2 2 A Y 4 1 2 1 1 2 3VDDCDA <9>
0_0402_5% L27 0_0402_5%
G

74AHCT1G125GW_SOT353-5 FBM-L11-160808-800LMT_0603 Q34


2N7002_SOT23

G
3

2
1 2 CRT_VSYNCRFL R445

220P_0402_25V8K

220P_0402_25V8K
L26 3V_DDCCL

S
1 3 1 2 3VDDCCL <9>

10P_0402_50V8K

C579 10P_0402_50V8K
FBM-L11-160808-800LMT_0603 1 1 1 1 0_0402_5%

R19 R444

G
2
5

U28 2 2 2 2

C581
R447 2.2K_0402_5%
P

OE#

2 CRTVSYNC CRT_VSYNC_R 2
<9> CRT_VSYNC 1 2 2 A Y 4
0_0402_5%
+3VS
G

C46

C577
74AHCT1G125GW_SOT353-5
2.2K_0402_5%
3

TV-Out Connector
S-Video
EMI L4
R24 MBC1608121YZF_0603
1 2 TVLUMA 1 2 LUMA_CL
<9> TV_LUMA
0_0402_5%
L6 JP17
R31 MBC1608121YZF_0603 1
TVCRMA CRMA_CL 1
<9> TV_CRMA 1 2 1 2 2 2
3 0_0402_5% 3
3 3
4 4
L5 5
R26 MBC1608121YZF_0603 5
6 6 GND 8
1 2 TVCOMPS 1 2 COMPS_CL 7 9
<9> TV_COMPS 0_0402_5% 7 GND
270P_0402_50V7K

270P_0402_50V7K

270P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
SUYIN_030107FR007G317ZR
1

1
75_0402_5%

75_0402_5%

75_0402_5%

1 1 1 1 1 1
R28

R29

R23

C75

C77

C49

C74

C76

C50
2 2 2 2 2 2
R22
2

1 2 TVGND

0_0805_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3341P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 20, 2006 Sheet 17 of 40
A B C D E
5 4 3 2 1

D D

+3VS

R179 1 2 8.2K_0402_5% PCI_DEVSEL#

R529 1 2 8.2K_0402_5% PCI_STOP#

R528 1 2 8.2K_0402_5% PCI_TRDY#

R530 1 2 8.2K_0402_5% PCI_FRAME# <23> PCI_AD[0..31] U6B


PCI_AD0 E18 D7 PCI_REQ0#
R526 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 AD1 GNT0# E7
PCI_AD2 A16 C16 PCI_REQ1#
R540 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16 PCI_GNT1#
PCI_REQ1# <23>
AD3 GNT1# PCI_GNT1# <23>
PCI_AD4 E16 C17 PCI_REQ2#
AD4 REQ2# PCI_REQ2#
R538 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2#
AD5 GNT2# PCI_GNT2#
PCI_AD6 E17 E13 PCI_REQ3#
R213 1 PCI_PERR# PCI_AD7 AD6 REQ3#
2 8.2K_0402_5% A17 AD7 GNT3# F13
PCI_AD8 A15 A13 PCI_REQ4#
R178 1 PCI_REQ4# PCI_AD9 AD8 REQ4# / GPIO22 +3VS
2 8.2K_0402_5% C14 AD9 GNT4# / GPIO48 A14
PCI_AD10 E14 C8 PCI_REQ5#
R527 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 AD11 GPIO17 / GNT5# D8

5
PCI_AD12 B12 U10
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 1

P
AD13 C/BE0# PCI_CBE#0 <23> B
PCI_AD14 G15 C12 PCI_CBE#1 4 PCI_RST#
AD14 C/BE1# PCI_CBE#1 <23> Y PCI_RST# <23,29,31>
PCI_AD15 G13 D12 PCI_CBE#2 2
AD15 C/BE2# PCI_CBE#2 <23> A

G
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 <23>
PCI_AD17 C11 @ TC7SH08FU_SSOP5

3
PCI_AD18 AD17 PCI _IRDY# R186
D11 AD18 IRDY# A7 PCI_IRDY# <23>
C PCI_AD19 PCI_PAR 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR <23>
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL#
F11 AD21 DEVSEL# A12 PCI_DEVSEL# <23>
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# <23> +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# <23>
R195 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP# Delete VGA_RST#
AD25 STOP# PCI_STOP# <23>

5
PCI_AD26 A8 F14 PCI_TRDY# U11
AD26 TRDY# PCI_TRDY# <23>
R196 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 1

P
AD27 FRAME# PCI_FRAME# <23> B
PCI_AD28 C7 4 PLT_RST#
AD28 Y PLT_RST# <7,22,24>
R194 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A

G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R193 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME# @ TC7SH08FU_SSOP5
PCI_PME# <23,31>

3
AD31 PME#
R197 1 2 8.2K_0402_5% PCI_PIRQE# R185
0_0402_5%
R524 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3
Interrupt I/F G8 PCI_PIRQE# 2 1
PIRQA# GPIO2 / PIRQE# PCI_PIRQE# <23>
PCI_PIRQB# B4 F7 PCI_PIRQF#
R525 1 PCI_PIRQG# PCI_PIRQC# PIRQB# GPIO3 / PIRQF# PCI_PIRQG#
2 8.2K_0402_5% PCI_PIRQC# C5 PIRQC# GPIO4 / PIRQG# F8 PCI_PIRQG#
PCI_PIRQD# B5 G7 PCI_PIRQH#
PCI_PIRQD# PIRQD# GPIO5 / PIRQH#
R198 1 2 8.2K_0402_5% PCI_PIRQH#

R192 1 2 8.2K_0402_5% PCI_REQ0# AE5


MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R211 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R210 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <7>
R212 1 2 8.2K_0402_5% PCI_REQ5# Place closely pin A9
ICH7_BGA652~D

CLK_PCI_ICH
B B

2
R176

@ 10_0402_5%

1
1
C415

@ 8.2P_0402_50V
2

A A

Security Classification Compal Secret