DATASHEET

NC-VERILOG SIMULATOR

The NC-Verilog® Simulator is the industry’s premier Verilog® simulator, delivering

high performance and capacity with transaction/signal viewing and integrated

coverage analysis. The NC-Verilog Simulator is fully compatible with the Cadence®

Incisive™ Unified Simulator, providing an easy upgrade path to comprehensive

digital verification from system design to system design-in for nanometer-scale ICs.

INCISIVE FUNCTIONAL
IP Incisive verification IP VERIFICATION PLATFORM
Algorithm The functional verification of
development CoWare SPW
nanometer-scale ICs requires speed
Analog/ and efficiency. Yet today's fragmented
Mixed-signal Incisive AMS
methodologies make it impossible to
Acceleration/ optimize either. Each verification
Emulation Incisive Palladium systems
stage has its own methodology, tools,
Acceleration- models, and user interface. Engineers
on-Demand
Incisive
must re-create almost everything at
XLD
Unified test every stage. The Incisive verfication
generation Incisive
platform is the world's first functional
Unified
HDL analysis verification platform that supports a
Simulator
unified methodology to deliver the
Assertions fastest, most efficient verification in
Comprehensive the industry.
coverage
Transaction
support NC-SC
Simulator
Debug/analysis
NC-VHDL NC-
Simulation Simulator Verilog
Simulator
Third-party
EDA support

Figure 1: The NC-Verilog Simulator is the fully compatible Verilog simulator

in the Cadence Incisive functional verification platform
 NC-VERILOG SIMULATOR
The NC-Verilog Simulator delivers
high-performance, high-capacity
Verilog simulation with transaction/
signal viewing and integrated coverage
analysis. It is fully compatible with the
Incisive functional verification
platform, so design teams can easily
upgrade to the Incisive Unified
Simulator and Incisive XLD team
verification, with native support for
Verilog, VHDL, SystemC®, SystemC
Verification Library, PSL/Sugar assertions,
and Acceleration-on-Demand.
BENEFITS
• Speeds verification with premier
simulation performance
• Designs chips in excess of 100M gates
with 64-bit capacity
• Maximizes efficiency with unified
transaction/signal viewer
• Ensures comprehensive verification
with integrated code coverage
• Provides a quick, fully compatible
upgrade to the Incisive platform
• Ensures accuracy with certified libraries
from more than 30 ASIC vendors
performance by identifying the areas
that consume the most simulation
time. NC-Verilog 64-bit capacity
simulates designs larger than 100
million gates.
UNIFIED ENVIRONMENT AND DEBUG
The unified NC-Verilog simulation
and debug environment makes it easy
to manage multiple simulation runs
and analyze the design and testbench.
Its transaction/waveform viewer
and schematic tracer quickly trace
design behavior back to the source.
The NC-Verilog source viewer lets
designers examine their design, set
complex breakpoints to control
simulation execution, and access
results in both interactive and post-
processing debug modes. Tcl/Tk
support enables customization and
integration of applications into the
environment. Industry-standard
application programming interfaces
like VPI, PLI, OMI, and compiled SDF
enable user-defined checks and
analyses so that the project team
need learn only one environment.
INTEGRATED CODE COVERAGE
The NC-Verilog Simulator provides
access to a wide variety of coverage
metrics to help determine how well
tests have exercised the design. These
include block coverage, path coverage,
expression coverage, state variable
coverage, state transition coverage,
state sequence coverage, and toggle
coverage. Integrated coverage analysis
and display tools speed the process of
determining which additional tests
will need to be developed.
FLEXIBLE OPTIONS
Upgrade the NC-Verilog Simulator to
the Incisive platform:
• Supports multilanguage simulation
(Verilog, VHDL, SystemC, SystemC
Verification Library, and PSL/Sugar)
• Speeds performance 100 times through
native transaction-level simulation
• Speeds performance up to 100 times
with Acceleration-on-Demand
• Reduces testbench development by
up to 50% through transaction-level
support, unified test generation,
and verification component re-use

FEATURES

PREMIER PERFORMANCE
AND CAPACITY
The NC-Verilog Simulator provides
the industry’s premier simulation
performance for Verilog designs
using the unique native-compiled
architecture of the Incisive Unified
Simulator. It produces efficient native
machine code directly from Verilog
for high-speed execution. Linked list
scheduling of the resulting data
structures pre-processes signal actions
and maximizes the effectiveness of
modern caching algorithms available
in today’s computing platforms.
The NC-Verilog performance profiler
identifies bottlenecks. Designers find
areas of high activity by viewing how
each module contributes to overall
performance. Minor changes can
greatly improve simulation

Figure 2: The NC-Verilog unified simulation and debug environment makes it easy to manage
multiple simulation runs and analyze the design and testbench
• Reduces debug time by up to 25%
through unified transaction/signal
viewing, native assertion support,
and unified debug environment
for all languages
• Assures comprehensive verification with
code and functional coverage analysis
• Enables analog mixed-signal/RF
verification
• Uses algorithm development with
model reuse for design verification
SPECIFICATIONS
SIMULATION
• Native-compiled architecture
– Verilog IEEE 1364-1995 and a majority
of IEEE 1364-2001 extensions
– SystemVerilog (IEEE-1800)
– Compiles directly to host
processor machine code for
maximum performance
• Supports Verilog configurations
through a library mapping file
– Supports multidimensional arrays,
e.g. regs, integers, and time
– Permits generation of multiple
instances of modules, primitives,
variables, nets, tasks, functions,
continuous assignments, initial blocks,
and always blocks
– Maximizes effectiveness of
modern caching algorithms
• Capacity
– Typical 10 million gate equivalents
in 32-bit OS (4GB addressable)
– Typical 100 million gate equivalents
in 64-bit OS
• Server farm
– Platform computing LSF
– Sun Microsystems Gridware
RESULT ANALYSIS
• Debug and GUI
– Waveform window
– Register window
– Unified transaction/signal viewing
– Schematic tracer
– Expression calculator
– Signal flow browser
– Source viewer
– Error browser
– Tcl/Tk scripting for
customizable displays
– Log signal and transaction data
to SST database
• Performance analysis tool
– Outlines areas of code where most
simulation time is being spent
• Code coverage
– Automatic Finite State Machine
(FSM) extraction
– Coverage attributes supported
include blocks, paths, expressions,
variables, gates, FSM (states,
sequences), toggle
– Coverage reuse
– Rank order coverage contributions
– Bit-wise expression scoring
THIRD-PARTY SUPPORT
• ASIC libraries
– More than 30 ASIC vendors
have certified their libraries for
the Incisive platform
– More than 150 unique libraries
• Models
– Third-party model support
through the Cadence verification
IP partner program
• Software
– Third-party software support
through the Cadence Connections®
program with more than 30
verification company partners
INTERFACES
• PLI (IEEE 1364)
• VPI (PLI 2.0, IEEE 1364)
• OMI (IEEE 1499)
• Compiled SDF
PLATFORMS
• Sun Solaris
• HP-UX
• Linux
• Windows NT
CADENCE SERVICES
AND SUPPORT
• Customer-focused solutions that
increase ROI, reduce risk, and achieve
your design goals faster
– Collaborative approach and design
infrastructure — virtual teaming
– Proven methodology and flow tuned
to your design environment
– Design and EDA implementation
expertise
• Product and flow training to fit your
needs and preferred learning style
– More than 80 instructor-led
courses — certified instructors, real-
world experience
– More than 25 Internet Learning
Series (iLS) online courses
• Cadence customer support that keeps
your design team productive
– Cadence applications engineers
provide technical assistance
– SourceLink® online support gives you
access to software updates, technical
documentation, and more — 24
hours a day, 7 days a week
FOR MORE INFORMATION
Email us at info@cadence.com,
or log on to www.cadence.com
© 2005 Cadence Design Systems, Inc. All rights reserved.
Cadence, the Cadence logo, Connections, SourceLink, and
Verilog are registered trademarks, and Incisive is a trademark
of Cadence Design Systems, Inc. SystemC is registered
trademarks of Open SystemC Initiative, Inc. in the United
States and other countries and is used with permission.
All others are properties of their respective holders.
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