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2016 13th International Conference on Power Electronics (CIEP)

Unity Power Factor Rectier with Reactive and


Harmonic Current Compensation
Gonzalez O., Perez-Ramrez J., Beristain J. A. Rodrguez E.J.J., Vazquez N.
Department of Electrical and Electronics Engineering Department of Electronics Engineering
Sonora Institute of Technology Celaya Institute of Technology
Obregon City, Mexico Celaya, Mexico

AbstractThis work presents the extended capabilities of a rectiers as APFs. Nevertheless, few works have taken this
single-phase Pulse Width Modulation (PWM) rectier to achieve idea since then; the most recent one that can be found is [15],
a unity power factor (PF) in the Point of Common Coupling where a sensorless technique for a PWM rectier with APF
(PCC). It can act as a dynamic var compensator, xed var
compensator and Active Power Filter (APF). To accomplish such performance is presented. The most relevant improvement
tasks a control scheme based in two cascaded loops is used. in recent works consists in the application of new control
The outer loop regulates the dc bus voltage and provides active schemes. In [16] a passivity based control is used for a PWM
power reference; the inner loop performs the tracking of active, rectier with APF functionality; [17] presents a Digital Signal
reactive and harmonic current references. Transistors are driven Processor (DSP) based linear control in the pq frame for the
by a Sinusoidal Pulse Width Modulation (SPWM) strategy which
receives a modulating signal from the inner loop of the control same purpose.
scheme. An average modeling is carried out and equations based Another approach to extend the capabilities of PWM rec-
on such model are obtained for the sizing of the passive elements. tier was made in [18], almost 20 years ago. It considers
Simulation and experimental results are presented. the idea of generating a limited amount of reactive power by
Index TermsPWM rectiers, Active Power Filter, var com- taking advantage of the same converter used as an SPWM
pensator, bridge converter, power factor correction.
rectier. As long as we can report, almost no work has been
done in this matter since then.
I. I NTRODUCTION
This work presents the idea of extending the capabilities of
Power rectiers are widely used on industry applications an SPWM single-phase bridge rectier to accomplish power
such as: adjustable speed drives, uninterruptible power sup- factor correction for polluting loads connected to the same
plies, dc motors, etc. [1]. For a long time, discrete power PCC. It can work as a unity power factor rectier, a var
rectiers based on diodes or SCRs were used. However, generator, a dynamic var compensator, an active power lter
international standards like IEC-555 and IEEE 519 require a or a combination of these functionalities.
decrease in harmonic pollution; for that reason solutions such This work is structured as follows: in the next section the
as PWM rectiers are commonly used to minimize the effect generalities of the system are described. Section three presents
of harmonic currents in the power supply lines [2]. Several the average model of the system and sizing equations for
topologies are available; some of them are shown in [3]. the passive elements. In section four, simulation and practical
The idea of using power converters to decrease the effect results are presented. Finally, conclusions are emitted.
of polluting loads in the grid has been presented since the
early 70s. It was rstly introduced by Sasaki and Machida II. S YSTEM DESCRIPTION
[4], and then taken up in other works such as [5] and [6]. Figure 1 shows a general scheme of the proposed system.
Recent approaches of using power converters for power quality The bridge rectier is coupled to de ac mains through an
enhancement aim on the inclusion of new control techniques inductance L. In the same PCC, linear and nonlinear polluting
as presented in [7] and [8]. Also, there is a trend to adopt new loads are connected. Whether the polluting loads are connected
converter topologies in these kind of applications as presented or not, the rectier provides active power to dc loads with
in [9], [10] and [11]. a unity PF. A capacitor C is connected to the dc bus for
A variety of topologies used as power rectiers aim to the dc voltage ripple regulation and it is used as an energy
accomplish unity power factor. However, as expressed in storage device for compensation functionalities. The converter
[12] only a small proportion focuses on power compensation is able to provide or consume reactive power (var) in two
for loads connected to the same PCC. Early works such as different ways: provided with a xed var reference or by
[13] and [14] introduce the idea of using PWM controlled sensing the current of linear loads connected at the PCC. Using
this sensing stage and a dq transformation-based reference
The authors acknowledge nancial support from CONACYT Grant acquisition conguration, the converter can work as an APF in
FORDECYT No. 190966, CONACYT Grant FOINS PDCPN2013-01 No.
215695 and the Program for Promotion and Support in Research Projects order to clean the grid current ig of harmonic currents caused
(PROFAPI ITSON). by local nonlinear loads.

978-1-5090-1775-1/16/$31.00 2016
c IEEE
238
Fig. 1. Proposed system.

Fig. 2. Acquirement of reactive power and harmonic current references.

A. Acquisition of reactive and harmonic current references


Figure 2 shows the conguration used to obtain the current Fig. 3. Control scheme used for the proposed system.
references for power factor correction; these references consist
of reactive and harmonic current components. The current of reference value Vdc
and the converter current if must follow
the loads iZ is taken to dq coordinates using the single-phase a given reference in order to keep a high PF at the PCC;
dq transformation dened in (1). ideally, it should be unitary. In order to achieve such tasks, the
    
id cos (t) sin (t) iZ control scheme presented in Fig. 3 is used. An external loop
= , (1)
iq sin (t) cos (t) iZ+90 regulates the dc voltage using a PI controller. The output signal
of the outer loop is the reference of active current id . A current
where iZ+90 is the current of the loads delayed 90 degrees;
reference if results from the sum of different components:
also, it is considered the voltage of the grid as
Active current to keep regulated the dc bus voltage.
vg = Vg cos(t) Fixed reference of reactive power.
Reactive and harmonic current components obtained from
.
sensed ac loads current.
In the dq frame the active (id ) and reactive (iq ) components
of iZ become constant values or dc components; the harmonic The error between the reference current if and the current
currents appear in the form of ac components in id and iq . if is provided to the PI controller-based inner loop; it produces
Since references of reactive and harmonic components are a modulating signal for a PWM strategy working in the linear
required in order to achieve compensation, the average active region that drives transistors Q1 Q4 ( see Fig. 1). With this
component Id is ltered from id . The single-phase inverse dq strategy, an output voltage van is set such that the input current
transformation dened in (2) is used to return the references if tracks the current reference if .
to the time domain.
     III. S YSTEM M ODEL AND SIZING EQUATIONS

 iq + ih =
cos (t) sin (t) id Id
(2) A. Average model
iq + ih +90 sin (t) cos (t) iq
Since a time-continuous control technique is used, an aver-
B. Control scheme age model is needed to match such behaviour. The average
In the proposed system, two main tasks must be accom- model has been obtained using the average signal of the
plished: the dc bus voltage must be kept regulated in a switching functions that describe the behaviour of the input

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current iE and the output voltage van of the converter. Those TABLE I
behaviours are expressed in (3) and (4). S YSTEM REQUIREMENT PARAMETERS FOR EXPERIMENTAL PROTOTYPE .

Parameter Value
van = SW vdc = uvdc (3)
Vg 180 V
Qmax 5000 var
iE = SW if = uif , (4) w 120 rad/s
vdc 10 % of Vdc
where SW is a switching function obtained by considering Pmax 1500 W
each leg as a Single Pole Double Throw (SPDT) switch and
 operator denotes an averaging operation. Nodal and mesh TABLE II
circuit analysis produces the model in terms of the dynamics C ALCULATED PARAMETERS FOR THE EXPERIMENTAL PROTOTYPE .
of the capacitor C and the inductance L:
Parameter Value
dif 1 C 2 mF
= (uvdc vg ) (5) L 8.4 mF
dt L
Vdc 360 V
  fs 9600 Hz
dvdc 1 1
= uif vdc . (6)
dt C R
A. Simulation results
B. Sizing equations for passive elements
For the simulation stage, PSIM R software is used. Simu-
A power ow analysis is performed in the PCC considering lation consists in a 4 seconds test where every second a load
a steady state operation and that the fundamental and harmonic change is carried out. The second column of Table III shows
components can be separated by applying the principle of the load conditions for each interval. Fig. 4 displays a plot
superposition. From such analysis it is possible to establish of the dc voltage, the converter current and the reference of
an expression for the size of the inductance L in terms of the the dc voltage. For every load change, the converter has the
active and reactive power. capability to maintain regulated the dc voltage.
Vg2 sin (1 ) Figure 5 shows plots of the grid voltage and current, the
L= , (7) ac loads voltage and current, and the current reference and
Pmax
the converter current under different load conditions. Fig. 5 a)
where 1 is the phase angle of van for the maximum power displays the waveforms for the converter working as a unity
ratings (Pmax and Qmax ) and is dened as power factor rectier, in Fig. 5 b) and c) it is working as a

  rectier with var generator and APF functions, respectively.
Pmax Vg Pmax
1 = arcsin arctan . Table III presents a summary of simulation results. As a
Vm Q2max + Pmax 2 Qmax remarkable fact, the converter keeps practically a unitary PF
Using the previous analysis and the solution of (6) for vdc , in the PCC.
two possible equations for the capacitor sizing are obtained:
B. Experimental results
Pmax
C= , (8) An experimental prototype of the proposed system was
vdc Vg cos arctan Q max
Pmax
implemented in the laboratory with the parameters shown in
Tables I and II. Fig. 6 displays measurements obtained using
Qmax the Fluke 43B power analyzer. It can be seen that the rectier
C= , (9)
vdc Vg sin arctan Q max keeps a unity power factor with a THD of 2.8%.
Pmax
Figure 7 shows the power and harmonic content measure-
where vdc is the desired peak to peak voltage ripple in the dc ments for the var compensation and APF capabilities. Figs. 7
bus, Pmax and Qmax are the desired maximum power ratings a) and b) show how a compensation of an inductive load is
for the converter. carried out at the same time that active power is delivered
to dc loads. An improvement is achieved in the PCC; the
IV. S IMULATION AND EXPERIMENTAL RESULTS displacement PF is raised from 0.75 to 1.0. A bridge rectier
In order to validate the proposed extended functionalities is connected to the grid in order to provide harmonic current
of the PWM rectier, several simulations are performed and pollution as seen in Fig. 7 c). This nonlinear load raises
an experimental prototype is implemented. The parameters of the value of the THD to 24.6%. However, when the APF
the requirements for the experimental prototype are shown in functionality of the rectier is enabled, the THD of the current
Table I. The values of the passive elements are obtained using in the grid decreases to 6.6% as shown in Fig. 7 d).

(7) for the inductor and (8) or (9) for the capacitor. Vdc is Plots of the dc bus voltage, the grid voltage and the grid
set to twice the amplitude of vg . The switching frequency for current are found in Fig. 8. The dc bus voltage stays regulated
the rectier is set highly enough to minimize the input current even when the compensation functionalities are enabled. The
ripple and to achieve harmonic current compensation. These improvement of the grid current waveform is remarkable. Most
values obtained are summarized in Table II. of the harmonic content is suppressed.

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C. Comparison between simulation and experimental results
In order to validate the proper implementation of the ex-
perimental prototype, a comparison of simulation and exper-
imental results is presented in Table IV. The PF at the PCC
and the THD value of the grid current ig are compared.
The rst line shows the performance of the rectier when it
is just driving active power to the dc loads. Both, simulation
and experimental results show that the power management is
carried out with a unitary PF and a low THD.
For the case where reactive power compensation is per- Fig. 4. Simulation of the dc bus voltage regulation.
formed in addition to the active power transfer, the PF and
THD conditions are kept. It is remarkable that the THD of ig
decreases with this situation; that is because the fundamental
component of the current ig increases due to the increase of
active power demand.
In the last experiment it is seen that the PF decreases and the
THD increases its value lightly; this has an explanation, the
coupling inductance L bounds the power transfer capabilities
and also works as a lter for the high frequency components
of the current caused by the switching stage. For high values
of L, the if current ripple is minimized. However, abrupt
changes cannot be handled and this sets a limitation for the
harmonic current compensation functionality. This leads to a
slightly higher THD and consequently a PF less but close than
one. Nonetheless, the values achieved with such limitations are
quite acceptable. The PF is signicantly close to one and the
THD is less than 10% in both scenarios.

V. C ONCLUSION

An extension of the capabilities of a unity power factor


rectier is presented in this work. An average model and
sizing equations based on such model are obtained as well.
Simulation and experimental results are obtained. These re-
sults support the idea of incorporating new functionalities to
existing PWM rectier topologies. This capabilities could be
used in a variety of industrial and residential applications.

TABLE III
S UMMARY OF SIMULATION RESULTS .

Interval
Load condition P FZ P FP CC T HDiZ T HDig vdc
(s)
0 to 1 No loads - - - - 0.18%
1 to 2 Dc loads - 0.999 - 1.9% 0.99%
Dc loads and
2 to 3 0.624 0.999 1.3% 1.3% 1.01%
linear ac loads
Dc loads, lin-
3 to 4 ear and nonlin- 0.676 0.996 65.5% 8.8% 1.12%
ear ac loads

TABLE IV
S IMULATION AND EXPERIMENTAL RESULTS COMPARISON .

Simulation Experimental
Function PF THD PF THD
Rectier 0.999 1.9% 1.0 2.8%
var compensation 0.999 1.3% 1.0 2.5% Fig. 5. Simulation of steady state under different load conditions.
Active lter 0.996 8.8% 0.98 6.6%

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Fig. 6. Unity power factor rectier function a) Power analysis at PCC, b)
Grid current harmonic content analysis.

Fig. 8. Waveforms a) before APF functionality, b) after APF functionality.


CH2: dc bus voltage (vdc ), CH3: grid voltage (vg ), CH4: grid current (ig ).

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