Am3341/2841/2841A Distinctive Characteristics ‘© “Plug-In” replacement for Fairchild 3341 © Asynchronous buffer for up to 64 four-bit words © Easily expandable to larger buffers 64x 4 Bits First-In First-Out Memories Complex MOS Integrated Circuits © Am2841 has 1MHz guaranteed data rate © Am2841A has 1.2MHz guaranteed data rate © 100% reliability assurance testing in compliance with MIL-STD-883 © Special input circuit provides true TTL compatibility “The Ama341/am2B41/Am28414 os an asynchronous (ietin ft (ut memory. stick, organized ay BA Toure words, The device accepts a tourbit parallel word Og~03 under control of the sn tn 151) Input. Dato entered into she FIFO immediatly rippet through the device 1 the outputs Op~O3. Up to 64 words may be entered before any words are read from the memory. The stored ‘words tine up at the Outbut end in the order in which they ware ‘eritten, A read command’ on the shift out input (SO) causes the ext 10 the ast word of data to move Yo the output and ll ate tits one place down the eck. Input ready IR} and outoutresdy (ORI sate sev os memory full and memory emoty flags and ied Brovide the necessary pulses for satreannerting FIFOs to obtain Seeer Racks FUNCTIONAL DESCRIPTION Parallel expansion to wider worss only requires that rows of FIFOs be laced sie by sie. Reading and wiring operations are completely independent, £0 the device can be used ae 3 butter between two signal machines fraing anynctvonoutly and at widely gifering cloce rate. Soe input eicuts are providaa on al impute to pul the Input egal up te an MOS Viig when 2 TTL Voy is reaches, providing tue TTL ‘compatibility without the inconvenience and extra power cain of ‘xterm pullup resistors A detailed dese fon page & and of tis date snet, The AmdB41 and AmNTOTA wre ‘netinallyidantea! to the AMAGAT, nut ae high pertormance LOGIC BLOCK DIAGRAM | ogi co: ORDERING INFORMATION MelwabW cew-n'e auawrre aMmeuire Auaeaare wrmucol Gelecmre amine AMZeNiO | AMESAIADE Romie Sip Scr ase ‘ogee me Noe waar Aueanersie AMZBELAK | C10 470°C ana ~55°C to +126°C vemperature ranges, | Note Pintle markes for arlene CONNECTION DIAGRAM Logic syMBoL, Top View ag $9.08 05 0) 0) Oy HH guage eee Ves = Pin 18 = Vbp = SND - Ping This datasheet wa is brought to you by synfo.nlMAXIMUM RATING (Above which the useful life may be impaiced! Storage Temperature TEE Cro EOC ‘Temperature (Ambient) Under Bias 55°C 10 4125°C Von Supply Voltage Vass —7V to Vsg +0.3V Vos Supply Voltage Vas ~20V to Vos +0.3V Dc tnput Voltage Vas —10V 10 sg 10.80 OPERATING RANGE Tanaeerre, 66 T Anaseve se | ewe | ssossn | oxo | ~re0ses anaesiom | ~sstewri2e"e eno | 190206 : | ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Uniess Otherwise Noted) Typ. Parameters Description Conditions| Min, nate) [Yor Dorp HIGH Voragr Ton= Soma Ves 10) Vou ‘vipat LOW Vartave ons 16 ma Vin Tnpur HIGH Covel ~ Vest] Vie Input LOW Level a or Tout Leakage Current Vin Ov hi Input HIGH Current Mins = Ys “1.0 250 Veg= 0 vou Input Puivp niation Vola wote2) | VSS=MIN | . euP put Patho en Voar_ Voltage 3t Peak Input Current WWote2) Tear Maximum Input Curent WWote 2) voce Ta- Cw o70C 7 sd Tas SC H12C oe ra OC 10 270°C Poet Tas Be Cw ase Neh 1 Telbaphat nna vance?” PO TAT AEE SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted Am3341 Am241 Am2841 A, Parameters Definition ‘Test Conditions __Min_Typ. Max. Min. Typ. Mex. Min. Typ. Max. Units tmx | Moumem Stor SO 075, 10 12 we Tiny _| Seay, SINIGH IR LOW 30 | ae | 50 | 400 | 0 =o [ne tin | Bey, SILOW wo TF RIGH 138} 295 | 860] 100 380 _| 100 50 ne ‘Minimum Teme Stand ji Se ne fovs | inpoth HIGH 2 = * ‘Minima Time Stand 5 we tov | Inno on 00 oj; | |# TOSi_| Date Release Time 00 200 200 [a 300 | ats Sup Tw 5 8 a ne Tons _| Batay, SO HIGHT OR LOW 30 | 38 | B00" | “79 | 200 HOBO FOO | 37m ton | Bay, 50 LOW fo OR HIGH v70_} 60 | 350 [70 300_| 680] 70 | 200 | a50| as ‘ter | Ripple through Time FIFO Empty 10 | a a [6 | RICE tH | Belay, OR LOW to Oats Our 50» LOW 5 7 me ‘yr | Minimum Reset Pale with 0 66 00s toa | Delay, Bate Out vo OA HIGH | —_SO™= HIGH os op oe a inaut Capestonce (Except a ol apr a 7 7 | or ‘Gn | Input Capacieance NA 6 7 7 LerCurrent Versut Input Voltage | er | DESCRIPTION OF THE Am3341 FIFO OPERATION “The Am3341 FIFO consists internally of 64 four-bit date registers and one 64-bit control register, as shown in the logic block Giagram. A "1" in a bit of the control register indicates that 2 [bit data word is stored in the corresponding data register. A ‘O" in a bit of the control register indicates that the corre sponding date resister does not contain valid cata. The control Fegster directs the movement of data through the data registers, Whenever the nf it of the control register contains @ "1" and the {neT)th bit contains 2 "0", then a strobe 1s generated causing the (n+Tith data register to fead the contents of the ni® data register, simultaneously setting the (n*t}th control register bit and ciearing the nt control register bit, so that the control flag moves with the data, In this fashion data in the data repster moves down the stack of data registers toward the output as long as there are “empty” locations aheac of it. The fall through oper ation stops when the date reaches a register n with 2 "1" in the (ne Tith control register nt oF the end of the register Data is intiatly loaded from the four data inputs Dg~D3 by applying 2 LOW-to-HIGH transition on the shift in (SU) input. ‘A""1" 4s placed in the first control register bit simultaneously. “The first control register bit is returned, buffered, to the input ready (IR} output, and this pin goes LOW indicating that data has been entered into the first data register and the input 's now ousy", unable to accept more data. When SI next goes LOW, the fall-through process begins (assuming that atleast the second location is empty}. The data in the first repster 1s copied into the second, and the fist control register bit is cleared. This causes IR to go HIGH, indicating the inputs are available for another data word, “The dete falling thraugh the register stacks up at the output end. At the outout the last contral register bit is buffered and brought ut as Output Ready (OR) A HIGH on OR indicates there is 3 1 in the last control register bit and therefore there is valid cata on the four data outputs O9~O3, An input signal, shift out ISO), 1s used to shift the data out of the FIFO. & LOW:t0-HIGH transition on SO clears the [ast register bit, causing OR to go LOW, indicating that the data on the outouts may ne longer be valid. When SO goes LOW, the "0" which is now present at the last control register bit allows the data in the next to the last register to move into the last register position and on to the outputs, The “0” in the control register then “bubbles” back towate the input asthe data shifts toward the output I the memory is emptied by reading out all the data, then when the last word is being read out and SO goes HIGH, OR will go LOW’ as before, but when SO next goes LOW, there is no data to move into the last location, so OR remains LOW until more dota arrives at the output. Similarly, when the memory is full ota wastten inte the fest Jocetion will not shift into the second when SI goes LOW, and IR will remain LOW instead of returning toa HIGH state “The pairs of input and output control signals are designed so that the SO input of one FIFO can be driven by the IR output of another, ané the OR output of the first FIFO can drive the Si input of the second, allowing simple expansion of the FIFO to any depth Wider buffers are formed by allowing parallel rows of FIFOs to operate together, as shown in the application on the last page ‘An over-riding master reset (MR) is used to reset all control ‘register bits and remove the date from the output (i.e.reset the ‘outputs to all LOW!FIFO empry, 5! LOW IR HIGH, word INITIAL CONDITION we IO Word "“C" writen in same manner, and 30 on, When buffer i fl ail control bts are 1's and IF stays LOW. =a 2 sae >TeTeTeTeTete T=] EEO OF RB Write int int fret stage by raising SI. (8 = delay) IR goes LOW indicating data hat Been entered, FIRST READ OPERATION 50 goes HIGH, indicating “Ready 10 Read". OF then goes LOW incicating "Data Rese 3 Te.. te data into FIFO by lowering SI. After delay, data moves to second location, and IR goet HIGH indeating input svaleble for 4 fe oe} 9 —eye AAD TL When SO goes LOW, the “0” inthe last conto bit bubbles toward the memory input. OF goes HIGH at the new word arrives atthe ‘output. TF goer HIGH wen “0” reaches Input () ome amy gee joe al ate spontencously neple tough registers to end of FIFO, causing OR 19 90 5 HIGH. The time required for de ‘auch the FIFO it the "Ripple through Time to fall comoletely | Read word "8" out, word “C" moves to output, and $0 on, ae 1) —PREPEPEP sete a cosa Fal nlf beh ee ate = a EEEEEET a Bead word iW". OR soyt LOW tecse FIFO & amsty, Word Word“ waten nto FIFO |. Sitamane in ota on aw word lt tec 6 ai a IO St 90 LOW alloning word to fall heough] ~~ O_O arses toe at fe urna aay A - OF TIMING DIAGRAM | { = ote USER NOTES | a rr—r— the ovtous unt the moses avobe8 or tow ast Word tal though to te cuter, However OR wi ain TW nceatng svat the ours ino ea 2. When the ovtout ata changes a Yes pul on 80, the nga aay gues COW belore thse hoy change cutout aa and always says LOW unl afer ve mew cata | hes pene on the utp so anytime OR HIGH tare | 4.1880 4 fed HIGH while te mamery 4 amply and # word | is written into the input, then that word will fall through the Z cycle (at least tome] and then will go back LOW again. The fored word witenan onthe utp H more words me sertten into the FIFO. they wl ie opbahind the fa were tnd wine spent of the eutpu ant SD hes bem Broa tow 4. When the master teset is brought LOW, the control resister and the outputs are cleared. IR goes HIGH and OR goes LOW. I SI is HIGH when the master reset goes HIGH then the data fon the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset is ended, then IR will go HIGH, ‘but the data on the inputs will not enter the memory until SI goes HIGH.gee APPLICATION. ee 3] es Fs Ed a Ps eS mune SE vas SES mu 8 3 y | a ai toa pa ae SEES ansaey anaes oe won anzear 3? oi amsteyanaee o aumee SESS eet SS eae <3 ‘The composite input ready indicates both devices wide enough forall devices to load date under w ready t0 receive di case conditions. 8 X 192 FIFO Buffer Using Am3341/Am2841 Ga “The shift in pulse must be PHYSICAL DIMENSIONS. Duai-in-Line 16Pin Side Brazed 16-Pin Molded alt ar 126 x190M vo