ASIC Design Document

Project Code:
Project Name: Synchronous FIFO Design Using
VHDL
Account:
Vertical: PES
Location: Bangalore
Customer Name: Internal
Technical Manager/ Email ID: Giri.Raju@wipro.com
Project Manager / Email ID: Gurmeet.Ubhi@wipro.com
Quality Co-ordinator / Email ID:

Customer Contact Information:

Prepared by /Date Reviewed by /Date Approved by /Date

VLSI / System Design Business Unit

Wipro Technologies

Bangalore
Revision History
Revision Description Date Changes By
Chetan.DNarayana
0.1 Initial Revision 09-Mar-07 @wipro.com
VLSI / System Design Business Unit
Wipro Technologies

ASIC Design Document for

Synchronous FIFO

Revision 1.1 August 8, 2002

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Confidential information
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TABLE OF CONTENTS

1 INTRODUCTION ................................ ................................ ................................ ................................ ..7

2 ARCHITECTURAL OVERVI EW................................ ................................ ................................ ...........7

3 SIGNAL INTERFACE DEF INITION................................ ................................ ................................ ......9

3.1 INPUTS ................................ ................................ ................................ ................................ ............9

3.2 OUTPUTS ................................ ................................ ................................ ................................ ........9

4 SUB-MODULE DESCRIPTION ................................ ................................ ................................ ..........10

4.1 MEMORY ................................ ................................ ................................ ................................ .......10

4.1.1 Functional Description................................ ................................ ................................ ........10
4.2 WRITE UNIT ................................ ................................ ................................ ................................ ...10
4.2.1 Functional Description................................ ................................ ................................ ........10
4.3 READ UNIT ................................ ................................ ................................ ................................ ....10
4.3.1 Functional Description................................ ................................ ................................ ........10
4.4 STATUS MONITOR ................................ ................................ ................................ .......................... 11
4.4.1 Functional Description................................ ................................ ................................ ........11
5 LIMITATIONS & ENHANC EMENTS ................................ ................................ ................................ ..11

6 TIMING DIAGRAMS ................................ ................................ ................................ .......................... 12

6.1 BASIC READ AND W RITE AND FIFO EMPTY ................................ ................................ ....................... 12
6.2 FIFO F ULL ................................ ................................ ................................ ................................ ....12
6.3 ERROR WHEN FIFO IS EMPTY ................................ ................................ ................................ ..........13
6.4 ERROR WHEN FIFO IS FULL ................................ ................................ ................................ ............. 13

GLOSSARY ................................ ................................ ................................ ................................ ............. 14

 ASIC Design Document for Synchronous FIFO

List of figures

Figure 1 : Block Description of the FIFO

Figure 2: Basic Read/Write Timing Diagram
Figure 3: FIFO Full Timing Diagram
Figure 4: FIFO Empty Error Timing Diagram
Figure 5: FIFO Full Error Timing Diagram

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 ASIC Design Document for Synchronous FIFO

1 Introduction
This document explains the scope and features of the Synchronous FIFO designed using
VHDL as a part of an internal project carried out during March 2007.

FIFO is an acronym for First In, First Out. This expression describes the principle of a queue or
first-come, first-served (FCFS) behavior: what comes in first is handled first, what comes in
next waits until the first is finished and so on. FIFOs are used commonly in electronic circuits
for buffering and flow control. It usually achieves a Store and Forward path for data.

There can be two types of FIFOs, a Synchronous FIFO, where the same clock is used for both
reading and writing. An Asynchronous FIFO which uses different clocks for reading and
writing.

2 Architectural Overview
The following block diagram shows the architecture and interface of the FIFO unit.

Rst

MEMORY
Clk (BUSWIDTH x
FIFODEPTH)

Dout Din
READ WRITE
UNIT UNIT
Rd Wr

Full
STATUS MONITOR Err
Empty

Figure 1 : Block Description of the FIFO

The design is parameterized, using the generics concept of VHDL, to have desirable data
width, and the depth of the FIFO. The data width refers to the width of the data bus and the
memory block in bits and the depth refers to the size of the FIFO, as to how many entries can
be pushed into the FIFO before filling it completely.

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 ASIC Design Document for Synchronous FIFO

The FIFO consists of a set of contiguous memory locations to which data can be written or
read from, on a first-in-first-out basis. The data can be continuously written to the FIFO until it
is full and can be read back when required. The data that was written first will be the data that
is obtained on the first read. Subsequent reads will return the data that was written
successively in time.

The design also flags the memory status as to whether it is full, without space for any incoming
data or empty, when no more data is available in memory. The module which issues a read or
write request should monitor the FIFO status before initiating a transaction. If the request
violates the rules for respective transaction an Error pulse is triggered by the FIFO.

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 ASIC Design Document for Synchronous FIFO

3 Signal Interface Definition

3.1 Inputs

Write Signals
Wr - Indicates a Write Request to the FIFO. For a valid write
request, this signal should be asserted during the rising
edge of the system clock.
Din - Data to be written to the FIFO. The data should be
available at the same clock edge when the Wr signal is
asserted.

Read Signal
Rd - Indicates a Read Request to the FIFO. For a valid read
request, this signal should be asserted during the rising
edge of the system clock.

Miscellaneous
Clk - System Clock. The design works on the positive edge
every clock cycle.
Rst - Active High Asynchronous Reset input.

3.2 Outputs

Data signal
Dout - Output Data that is read from memory during a read
transaction.

Status Signals
Full - The FIFO full flag. This asserts on the successful write
operation which last caused the FIFO memory to be
full, and is de-asserted until a read operation happens
to vacate a memory location.
Empty - The FIFO empty flag. This when asserted indicates
that there is no data in the FIFO, and de-asserts when
a write operation is initiated on the empty FIFO.
Err - An error flag. A pulse of 1 clock duration is generated
on this output, if a write to FIFO is attempted when it is
full or a FIFO read is attempted when it is empty.

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4 Sub-Module Description
4.1 Memory
This is a collection of contiguous memory locations which constitute a RAM.

4.1.1 Functional Description

Each memory location is of width BUSWIDTH in bits, where BUSWIDTH is the deign
parameter. The number of such memory locations will be equal to another parameter defined
as FIFODEPTH. So the memory can hold maximum number of entries equal to the
FIFODEPTH at any instant of time.

4.2 Write Unit

This unit is responsible for responding to an external write request initiated on the FIFO and
transfers the incoming data to next free location in Memory.

4.2.1 Functional Description

The Write Unit maintains an internal write pointer which indicates the location in memory
where the next incoming data can be written. On every successful write operation, this pointer
is incremented. This is implemented in a loop back fashion, which does not exceed the
maximum FIFO size given by the FIFODEPTH. Hence, if the FIFODEPTH is defined to be
256, then the write pointer starts at 0 and reaches a maximum of 255, it then loops back to 0 to
continue incrementing.

The write pointer maintained internal to the Write Unit can be accessed by the Status Monitor
for the purpose of generating the FIFO Full flag.

On every rising edge of the clock input, the Write Unit will sample the Wr signal of the FIFO
input, if found to be asserted, a write operation is initiated. The data that is to be written will
also have to be available on the Din input, by the same clock edge. It will next check from the
Status Monitor if the FIFO is full. If so, then it updates the Status Monitor of an illegal operation
detected, else the data on Din input is transferred o the memory location pointed by write
pointer and then increments the write pointer.

4.3 Read Unit

This unit is responsible for responding to an external read request initiated on the FIFO and
transfers the appropriate data from Memory on to the Dout output bus.

4.3.1 Functional Description

The Read Unit maintains an internal read pointer which indicates the location in memory
where the next data can be read from. On every successful read operation, this pointer is
incremented. This counter is implemented in a loop back fashion, which does not exceed the
maximum FIFO size given by the FIFODEPTH. Hence, if the FIFODEPTH is defined to be
256, then the read pointer starts at 0 and reaches a maximum of 255, it then loops back to 0 to
continue incrementing after every successful read operation.

The read pointer maintained internal to the Read Unit can be accessed by the Status Monitor
for the purpose of generating the FIFO Empty flag.

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 ASIC Design Document for Synchronous FIFO

On every rising edge of the clock input, the Read Unit will sample the Rd signal of the FIFO
input, if found asserted, a read operation is initiated. It will next check from the Status Monitor
if the FIFO is empty. If so, then it updates the Status Monitor of an illegal operation detected,
else the data from the memory location pointed by read pointer is transferred to the external
interface and then increments the read pointer.

4.4 Status Monitor

This unit coordinates with the Read Unit and Write Unit to flag any anomalies in the functioning
to the external interface.

4.4.1 Functional Description

Empty Flag: The Empty signal on the FIFO output is asserted by the Status Unit to indicate
that the FIFO does not contain any data. An attempt to read the FIFO when this flag is
asserted is unexpected and if tried would pulse an error flag.

Full Flag: The Full signal on the FIFO output is asserted by the Status Unit to indicate that the
FIFO memory is full, and any further write operation will not be supported. If such an
unsupported operation is attempted, an error flag will be pulsed.

Error Flag: If a FIFO read is requested when it is empty, or if a FIFO write is requested when it
is full, then an error is flagged by the Status Monitor. This occurs as a pulse of one clock
duration on the Err output of the FIFO. The duration of the error pulse may extend beyond one
clock period, if the unsupported request is continued even in the next clock cycle.

The external module which tries to access the FIFO should take care that it does not attempt a
read when the FIFO is empty or a write when the FIFO is full. Such a request will not be
supported by the FIFO and will in turn pulse the Err signal, intimating the requestor of an illegal
request attempted. If the FIFO receives both read and write requests simultaneously and an
Err pulse is tossed, the requestor will be able to identify which request has failed, by sampling
the Full and Empty signals at that instant. If the Full is asserted in the event of an Err pulse,
then the write request wouldn’t have succeeded, else if the Empty is asserted, then the read
request wouldn’t have succeeded.

5 Limitations & Enhancements

The following are some of the limitations of the design and the already identified
enhancements:
§ The reset signal is active high. This can be made a active low reset.
§ FIFO almost full and FIFO almost empty indications can be generated.

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6 Timing Diagrams
6.1 Basic Read and Write and FIFO Empty

Clk

Rst

Wr

Rd

Din Data 1

Dout Data 1

Empty FIFO empty FIFO empty

Full

Err

Figure 2: Basic Read/Write Timing Diagram

6.2 FIFO Full

Clk //

Rst //

Wr //

Rd //

Din Data 1 // Data256

Dout //

Empty FIFO empty //

Full // Fifo full

Err //

Figure 3: FIFO Full Timing Diagram

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6.3 Error when FIFO is empty

Clk

Rst

Wr

Rd

Din

Dout

Empty FIFO empty

Full

Err Error
Figure 4: FIFO Empty Error Timing Diagram

6.4 Error when FIFO is full

Clk //

Rst //

Wr //

Rd //

Din Data 1 // Data256 Data257

Dout //

Empty FIFOempty //

Full // FIFO full

Err // Error
Figure 5: FIFO Full Error Timing Diagram

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 ASIC Design Document for Synchronous FIFO

Glossary
FIFO : First In First Out
-- End of Document --

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