Research on EMC Optimization of High Speed

PCB Design
Xi Chen, Shuguo Xie, Mingmin Zhao and Chengbin Fu
EMC lab
School of Electronic and Information Engineering, Beihang University
Beijing, China
chenxi0724@yahoo.com.cn

AbstractIn This paper three optimization methods of medium in series, the equivalent impedance is Z1,2
ground design are used to solve EMI problems on the PCB
mixed with both analog and digital signals. A model was and Z 2,3 [1], So, The series impedance of the signal is:
built to test the surface current, E field, H field and
S-parameters of the circuit board to consider the effect of Z driver = Z 1, 2 + Z 2,3
these methods of avoiding EMI and SI problems. Then
simulation experiments on a real product are carried out
to show the improved performances after adopting these
methods.
Keywords-high_speed PCB layout; EMC; EMI; spilt
ground; SI

I. INTRODUCTION
Recent trends in use of high-speed logic families in
electronic circuit enhance the EMI (electromagnetic
interference) problems of a PCB product. The high
frequencies can cause interference easily in an
inappropriate design such as ringing, reflections,
crosstalk and radiation. If be ignored, this
noise can seriously influence the system performance. In
the PCB design, the designers always believe that the
ground is nothing but a whole plane. But probably
they do not know that EMI problems of the PCB
probably product due to error design of the ground.
This paper is organized as follows: In section II,
three considerations for reducing EMI from printed
circuit boards with ground plane design. In section III,
using simulation tools to make the theory into a specific
simulation example enable readers to more intuitive
understanding of the correctness of the theory. In section
IV experiments are carried out in a real product to show
the improved performances due to these three adopted
techniques. Finally, make a conclusion about ground
design in PCB product to avoid EMI problems.
II. THREE REQUIREMENTS OF GROUND DESIGN
A. The signal layer should as closely as possible to the
ground plane
In signal integrity issues, we generally called the
ground as the return path. In high frequencies, the
inductance of signal path and return path are required
minimize, this means that, as long as the circumstances
allow, return path will try to close to signal path. As the
Fig. 1 shown, there is a signal line on a PCB, and its
return path is located in the third path. At this moment
the impedance of the signal is between two layers of
Fig. 1  signal line and its equivalent circuit
So, the smaller of the impedance of two layers, or
the lower the Z driver value, the impedance of the signal
is more approach to Z1,2 .
Therefore, we can conclude that reducing the
impedance between adjacent layers is the most
important way to minimize the thickness of the plane
between the media. Or we must make the return path
nearly the signal as possible as we can.
B. Different signal set up different ground
Different nature of the circuit need different
accuracy of voltage, different return path, at the same
time, the tolerance for noise limits are not the same.
Usually, the frequency of digital circuit is much taller,
and the simulation for the sensitivity of the circuit noise
is stronger, therefore the digital part and the analog part
should be separated as much as possible. So, both the
return path will mutual isolated. When the circuit board
exists as different nature of the circuit and mix together,
in the case of the ground should be partition [2].
C. Writing cross the Segmentation clearance is not
appropriate
Analog signals and digital signal will eventually go
back to the ground, however, due to digital signal
change speed, thus, there will be a lot of noise generated,
but the analog signal need a clean reference ground to
work. If we do not split the ground but mixed them

This material is based upon work supported by the National

Basic Research Program of China (973 Program, No.
2010CB731800 )

978-1-4244-8165-1/11/$26.00 2011 IEEE

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together, the digital signal noise will influence the
analog signal through the ground layer. Many designers
recognized that recently, when they design a PCB
product taking into account the ground segmentation.
But without the right to the division of the ground, still
can bring some EMI problems. The most typical
problems caused by the signal lines across the
segmentation clearance.
Writing cross the segmentation clearance may cause
the following question:
z Resulting the line impedance discontinuity;
z produce crosstalk;
z May cause signal reflections;
z Increase the current loop area, the loop
inductance, and make the output waveforms
prone to oscillation;
z May increase radiation, and vulnerable to the
impact of the magnetic space;
z Make magnetic field coupling with other
circuits easily;
z The high frequency voltage drop of loop
inductance composition of common mode
radiation, and through an external cable
produces common-mode radiation.
When we design a mix-signal circuit, we cant allow
the analog ground and digital ground produce
overlapping [1]. Otherwise, both will cause noise and
interference because of capacitive coupling [3]. As Fig.
2 shown, if there is a line across the integral formation,
so, what is the problem? If we use the segmentation
method as shown below, assuming we split the ground
into digital ground (DGND) and analog ground
(AGND), and suppose that the two pieces of land links
together at a uncertain point, the signal return path is
shown below, not under the signal line, but return alone
the connection point and form a large loop.
Connection

 upper part of the edge of clearance segmentation.
As we know, the current flowing through the
multi-conductor surface will produce common mode
EMI, the outputs current of circuit components flow into
the load will produce differential mode EMI[4].
Differential mode radiation is calculated as [5]:
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I p f 2 Ls
E p = 1.316 10 14
d
In this formula:
I p ---Two layer impedance
f ---Current frequency
Ls ---Loop area
d ---the distance of measuring antenna to cable
From the above formula, it is that the radiation
intensity is proportional to the loop area, that is, the
greater of the return path, the greater of the radiation.
From the analysis we can conclude that because of the
signal across the segmentation clearance that leads to the
signal current cannot be return to the source through the
minimum loop, and radiation the electromagnetic energy
by the way of differential mode and because of the
signal current backflow impedance becomes very
large[6][7]. Therefore, the noise current on the ground
can also become large and the common mode radiation
arise from the big difference voltage on the ground is
also very strong. If there are some signal lines have to
across the two kinds of ground, the designer should
connect the ground with a single point under the signal,
to make the return path shortest [8].
III. MODEL VALIDATION
In order to verify the correctness of the theory, this
paper used the simulation software to verify the point
above. Here we use SIwave and HFSS to simulation.
This paper set up a double-layer PCB circuit board. As
shown in Fig. 3, assume that there is a signal line from
above AGND to DGND above. From the ground plane
0.135mm and give a current to this line at point A and
observe the Surface current, distribution of near field E,
H and the Isolation on the whole board.
A D
B
Signal injection
C

This paper connects the AGND and DGND at
different place, as Fig.3 shown, B is located just
below the signal line, C is located in the bottom of the
edge of clearance segmentation, D is located in the
Analyze the surface current, the near field and the S_
parameters about the three conditions.
A. Surface current
We analyze the surface current in HFSS, Fig.4, Fig.5
and Fig.6 is simulation result about surface current of
the connection of B, C, and D. Comparison figures is as
follows:
 Fig.8 is shown the Electric field strength:
Connection line B

Connection point B



Connection line C
Connection point C



Connection point D

Connection line D

 most of them are under the signal line. So this board
Contrasted can be found, the surface current
distribution about C and D is larger than B. On the
connection line, C and D are also produce larger surface
current distribution. But we can know from Fig.4 that
when the point is located in B, the surface current
distribution is concentrated, mostly under the signal line,
so the radiation is smaller than other two.
B. Near-field
This paper used SIwave in order to get the near-field
electromagnetic field analysis result, because the
relationship is complex about electric and magnetic field
in near-field. E and H dont determine the relationship.
So we simulate each other.
Fig.7 is shown the Magnetic field intensity:

The conclusion can be draw from the two groups of
pictures up. When the connection is located under the
signal line (point B), energy distribution is concentrated;
should not produce radiation, and have little influence to
the outside. But when connect the C and D, whether
electric field or magnetic field can be seen that the
energy and not completely along the line distribution. In
the position of the connection, also has the energy
distribution that means it is easily produce EMI
problems.
C. Isolation
Connect the S-parameter probe on the signal input
port and signal backflow port, to get the forward voltage
transmission coefficient (S (2,1)).
C
D

Connection line B B

Connection
line C


It can be seen from the Fig.9, when the connection is

located under the signal, the transmission coefficient is
minimal, or we can say the impact is minimizing for the
devices on the board.
Connection
line D IV. AN APPLICATION EXAMPLE
For the original design of the 4-layer PCB, analog
GND is located in the third layer (GND) (Fig.10 (a)), the
RF signal ground reference in the 4-layer (bottom)
(Fig.10 (b), (c)). It BCI measure does not meet ISO


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11452-4 requirement, based on the theoretical analysis,
we can get this board exist in the following problems:
z RF signal wiring too far away from the
RF_GND
z No isolation processing between RF and digital
ground.
z The hollowed in GND makes the return path
discontinuous between the RF and digital,
resulting in return path is not controllable and
makes EMI problems.

  



  
   In PCB design process, EMC is not be ignored, this
So, do the following improvement as Fig.11 shown:
z Use the copper to fill in the black on GND
layer (digital layer) and separated out the RF
ground (a)
z Connected the RF ground and digital ground
with a single point under the signal line (b)
z Disconnect the digital GND and RF GND on
bottom layer (c)
Joint line
                                   1998 IEEE Aerospace Conference.
 
 [5] Tamir E Moran, Methods to Reduce Radiations from Spilt
In order to validate the improvement effect, using
SIwave simulation to get the S-parameters. PORT_1 for
the practical input port, PORT_2 set as the each pin for
the RF chip. S 2,1 is date for the interference from the
connectors port to the port of RF chip. The smaller of
the S 2,1 that the crosstalk is smaller.
V. CONCLUSION
paper combine the theoretical and practical example to
discuss the EMC and SI problems in mixed-signal PCB
ground design and analyze the close relationship
between the loop area and electromagnetic radiation and
SI. Use the EMC simulation software to verify it. The
result shows that a well ground segmentation for
high-speed PCB has a great significance.
REFERENCES
[1] Eric Bogatin, Signal Integrity:Simplified,2005
[2] Jing wei, The Split Ground Plane, Printed Circuit
Information, 2007, (3), pp.39-43.
[3] J, Q, Shen, Improve the electromagnetic compatibility of the
mixed signal PCB partition design, Digital technology and
application, 2010, (9), pp.81-82.
[4] Neal Schneier, High Speed Digital Interconnect analysis
Ground Plane Structures, IEEE, 1999.
[6] Ohnson H, Common Mode Ground Currents, HSDD,
newsletter v01.7#022002
[7] H, Z, Gu, The PCB EMC technology, Design Practice, 2004.
[8] A, F, Qian, Printed circuit board design of EMI solution,
EDN Electronic design technology, 2009,(1), pp.70-71

Figure.12 to Figure.13 is the before and after

comparison chart for the most sensitive port. From that
we can known that signal crosstalk are largely improved,
interference signal has been effectively suppressed, and
verifying the improvements are feasible.

 

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