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High Step-up Ratio DC-DC

Converter Topologies
Part I
Speaker: G. Spiazzi

P. Tenti, L. Rossetto, G. Spiazzi, S. Buso, P. Mattavelli,


L. Corradini
Dept. of Information Engineering DEI
University of Padova
Seminar Outline
Why we need high step-up ratio converters?
Application fields
Low power high step-up ratio topologies
Coupled inductors
High power high step-up ratio topologies
Non isolated
Isolated

2
High Step-up Ratio Topologies
Why?

Low-voltage high-current energy sources


Fuel-cells (some kW)
Paralleled photovoltaic modules in domestic
applications (some kW)
Microinverter, i.e. connection of a single
photovoltaic module to the grid (some hundred
watts)
Step-down inverters require an input voltage
higher than the maximum line voltage peak

3
Example of Microinverter

Utility
grid
Microinverter
structure

200-300W High Step-Up Microinverter


single pv panel for single panel
DC-DC

Modularity
Reduction of partial shading effects
Dedicated Maximum Power Point Tracker (MPPT)

4
Simple Boost Topology
Boost scheme including some parasitic elements:
Diode model
IL UD rD Io
+ D
rL L +
+ rS Voltage
Ui C Ro Uo conversion ratio
S (neglecting inductor
- current ripple):
Switch model
1 1 1
M= = F(d,Uo ,Ro )
1 d 1 + rD (1 d) + rS d + rL + UD 1 d
Ro (1 d)
2
Uo
5
Simple Boost Topology
Voltage conversion ratio M including
conduction losses:
M
ideal
8 Mmax

2
Ro

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Duty-cycle
6
Simple Boost Topology
Converter =
Pout UoIo UoID
= = = M (1 d) = F(d,Uo ,Ro )
efficiency: Pin UiIi UiIL
1

0.95

0.9

Ro
0.85

0.8

0.75

0.7
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Duty-cycle 7
Low Power Applications

Example:
Example integrated Boost-Flyback converter

ig It can be seen as a
1:n21
Ld D2 + + flyback converter with a
im
Lm C2 U2
non dissipative snubber:
Ug Uo
D1 and C1 deliver to the
S
D1 +
C1 U1 output the energy stored
-
in the transformer
leakage inductance Ld

8
Integrated Boost-Flyback Converter
Ideal waveforms:
- CCM operation of flyback section ig iD2
1:n21
- DCM operation of boost section Ld D2 + +
Lm C2 U2
im
Ug Uo

im iD1 D1 +
S C1 U1
ig -

t
iD1
Advantages:
ZCS turn on
iD2 t Soft diode turn off
t Reduced switch
t0 t1 t2 t3 t4=Ts-t0 voltage stress
9
Integrated Boost-Flyback Converter

Problems:
Parasitic oscillations at D2 turn off caused by its
capacitance Cr resonating with transformer leakage
inductances Ld and Ls

ur
+
ig is Cr
1:n21
Ld Ls D2 + +
Lm C2 U2
High voltage stress
im
Ug Uo
across D2
D1 +
S C1 U1
-
Dissipative R-C-D snubber
is needed
10
Modified IBF Converter

ur
ig
1:n21
is Cr
+
Clamping diode D3 added to
Ld Ls x D
2 +
+ the original topology
im
Lm
D3 C2 U2
Ug Uo
Advantages:
D1 + Clean diode voltage
S C1 U1
- waveforms without parasitic
oscillations
Energy transfer toward the
output also during switch turn
on interval
Slight voltage gain increase
due to resonances between
parasitic components
11
Modified IBF Converter

ig

im
Interval T01 = t1-t0

iD1 ig iD2

Ld Ls D2 + +
im
Lm C2 U2
iD2 t
Ug Uo

t +
iD3 S C1 U1
t
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

12
Modified IBF Converter

ig

im
Interval T12 = t2-t1

t
ur
+
iD1 ig Cr
Ld Ls +
+
Lm C2 U2
iD2 t im
Ug Uo

t +
iD3 S C1 U1
t
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

13
Modified IBF Converter

ig

im
Interval T23 = t3-t2

iD1 ig

Ld Ls +
+
Lm C2 U2
iD2 t im D3
iD3
Ug Uo

t +
iD3 S C1 U1
t
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

Note: actual iD3 slope can be either positive or negative


14
Modified IBF Converter

ig

im
Interval T34 = t4-t3

iD1 ig

Ld Ls +
+
Lm C2 U2
iD2 t im D3
iD3
Ug Uo

t iD1 D1 +
iD3 t S C1 U1
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

15
Modified IBF Converter

ig

im
Interval T45 = t5-t4

t
ur
+
iD1 ig Cr
Ld Ls +
+
Lm C2 U2
iD2 t im
Ug Uo

t iD1 D1 +
iD3 t C1 U1
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

16
Modified IBF Converter

ig

im
Interval T56 = t6-t5

iD1 ig iD2

Ld Ls D2 + +
im
Lm C2 U2
iD2 t
Ug Uo

t iD1 D1 +
iD3 t C1 U1
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

17
Modified IBF Converter

ig

im
Interval T67 = t7-t6

iD1 iD2

Ls D2 + +
im
Lm C2 U2
iD2 t
Uo

t +
iD3 C1 U1
t
-
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

18
Converter Parameters

Input voltage: Ug = 25-35 V


Output voltage: Uo = 400 V
Nominal output power: Po = 300 W
Switching frequency: fs = 100 kHz

Magnetizing inductance: Lm = 20 H
Primary leakage inductance: Ld = 0.4 H
Secondary leakage inductance: Ls = 2 H

19
Voltage Conversion Ratio

Comparison between calculations and spice


simulations
Uo U1
M= M1 =
M M1 Ug Ug
21 5.6
This unmatched point
17 5.2
corresponds to a
13 4.8 different topological
sequence
9 4.4

5 4
0.4 0.5 0.6 0.7 0.8
Duty-cycle
20
Voltage Conversion Ratio

Effect of resonant intervals on the overall


voltage gain

M
14
13
With parasitic Uo
12
components M=
11 Ug
10
9
8 No parasitic
7 components
6
0.4 0.45 0.5 0.55 0.6 0.65 0.7
Duty-cycle
21
Experimental Results

Ug = 35 V, Uo = 400 V, Po = 300 W
ux [100V/div]

uDS [50V/div

ig [2.5A/div]

Peaking due to a small dip in the converter


input voltage due to fast current rise time

22
Experimental Results

Ug = 35 V, Uo = 400 V, ux ux

Po = 300 W uDS
uDS
ig

im

t
Impk ig ig

iD1
t0 t1 t2 t3 t4 t5 t6

iD2 t

t
iD3 t
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0
23
Experimental Results

Ug = 25 V, Uo = 400 V, Po = 300 W

ig

ux [100V/div] Ld Ls +
+
Lm C2 U2
im D3
iD3
uDS [50V/div Ug Uo

+
S C1 U1
-
ig [5A/div]

D3 turns off during


the switch on interval
t0 t1 t2 t3

24
Measured Efficiency

Po = 200 W Po = 300 W

fs = 100kHz fs = 100kHz
0.94
0.95

0.93
0.94
fs = 200kHz 0.92 fs = 200kHz
0.93
0.91

0.92 0.90
25 27 29 31 33 35 25 27 29 31 33 35
Ug [V] Ug [V]

25
Measured Efficiency

fs = 100 kHz

Ug = 35V
0.95

0.94
Ug = 25V
0.93

0.92
100 150 200 250 300
Po [W]

26
IBF Converter with Voltage Multiplier

Voltage multiplier cell

+
D2 C +
2 U2

+
D3 C3 U3
ig Uo
im
Ld Lm D1 +
Ug S C1 U1
-

27
IBF Converter with Voltage Multiplier

IBF converter with voltage multiplier cell


versus modified IBF

ur
+
+
+ ig is Cr
D2 C U2 1:n21
2
Ld Ls x D +
2 +
+ im
Lm
D3 C2 U2
D3 C3 U3
Uo Ug Uo
ig X
im
D1 +
Ld Lm D1 +
Ug S
S C1 U1
C1 U1 -
-

Similar behavior with a higher degree of freedom


in controlling the switch voltage stress
28
Converter Waveforms
BOOST section in DCM and FLYBACK section in CCM

Igpk
ig Impk
Im1
Cr + im
+ + Im2
ur D2 C2 U2 Imvl
is
x Ns
t
Ls + Impk
Np D3 C3 U3
ig Uo iD1
im
Ld Lm D1 +
Ug S Im1/n21
C1 U1 iD2 t
- is(t5) Im2/n21

-is(t2) t
iD3 iD3(t3) t
t0 t1 t2 t3 t4 t5 t6 t7=Ts-t0

29
Experimental Prototype
Design example: From the design constraints:

Input voltage: M= Uo / Ug=400/35=11.42


Ug = 2535V M1= U 1/ Ug=75/35=2.143
Output voltage: Numerically solving:
Uo = 400V
Nominal output power: d = 0.519, n21 = 4.589
Po = 300W M2 = U 2/ Ug = 4.823
Switching frequency: M3 = M-M1-M2 = U 3/ Ug = 4.454
fs = 100kHz
Boost output: 150V rated mosfet M M1
calculated voltage
U1 = 75V 25 gains (continuous 5
Magnetizing inductance: curves) and simulation
Lm = 20H 20 results (dotted) 4
Primary leakage inductance:
Ld = 0.4H 15 3
Secondary leakage
inductance: 10 2
Ls = 2H
5 1
Based on desired current ripple and DCM- 0.4 0.5 0.6 0.7 0.8
CCM mode at nominal power
Duty-cycle 30
Experimental results
ux Measured main
waveforms in a
switching period
Ug = 35V, Vo = 400V,
uDS Po = 300W

ux: 100V/div; uDS: 20V/div; ig: 5A/div Cr +


+ +
ig ur D2 C2 U2
is
x Ns

L +
Np D3 s C3 U3
ig Uo
im
ux Ld Lm D1 +
ux Ug S
C1 U1
-
uDS uDS

layout
zero current stray Details of turn on and
turn on inductances
resonance turn off intervals
ig ig

t0 t1 t2 t3 t4 t5 t6 31
Converter efficiency
The converter efficiency was measured as a function of input
voltage, at Po=300W,Fig.1, and at Ug=[25V,35V] and variable
output power, Fig. 2

Efficiency Efficiency

Ug = 35V
0.96
0.95

0.95

0.94
Ug = 25V
0.94

0.93 0.93
25 27 29 31 33 35 100 150 200 250 300
Ug [V] Po [W]
Fig.1 Fig.2

32
Isolated IBF Converter

Cr +
ur
+
D2
+
C2 U2
For isolation, the loss-
is
x Ns less snubber D1-C1 is
L
D3 s
+ substituted by an
Np C3 U3
Uo
active clamp
ig
im
Ld Lm D1 +
Ug S
C1 U1
-
ig id io

Ld D2 + +
C i Lm Cr ur C2 U2
UAC + AC m Np
SAC Ls is +
Ug Uo Ro
Ns + -
S D1 C1 U1

33
Isolated IBF Converter

Advantages:
ZVS turn on
Soft diode turn off
Reduces switch voltage stress
Clean diode voltage waveforms without parasitic
oscillations
Energy transfer toward the output also during
switch turn on interval
Reduced active clamp circulating current

34
Converter Operation
Hp: negligible capacitor voltage ripples
Interval T01 = t1-t0
id Impk
im(t0) im
Imvl ig id io

t Ld D2
+
id(t0) im Lm C2 U2
Np
Ls is +
Ug Uo Ro
iSAC
Ns + -
t S C1 U1
iD2 Ug

t
iD1
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0

Soft D2 turn off


35
Converter Operation
Hp: negligible capacitor voltage ripples
Interval T12 = t2-t1
id Impk
im(t0) im
Imvl ig id io

t Ld + +
id(t0) im Lm Cr ur C2 U2
Np
Ls is +
Ug Uo Ro
iSAC
Ns + -
t S C1 U1
iD2 Ug

t
iD1
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0

36
Converter Operation
Hp: negligible capacitor voltage ripples
Interval T23 = t3-t2
id Impk
im(t0) im
Imvl ig id io

t Ld
+
id(t0) im Lm Np C2 U2
Ls is +
Ug Uo Ro
iSAC
Ns + -
t
S D1 C1 U1

iD2 Ug

t
iD1
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0

Note: actual iD1 slope can be either positive or negative


37
Converter Operation
Hp: negligible capacitor voltage ripples
Interval T34 = t4-t3
id Impk
im(t0) im
id io
Imvl
Ld
t +
id(t0) C i
UAC + AC m Lm Np C2 U2
SAC Ls is +
Uo Ro
iSAC -
Ns +
D1 C1 U1
t
iD2 Ug

t
iD1
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0

Soft D1 turn off


38
Converter Operation
Hp: negligible capacitor voltage ripples
Interval T45 = t5-t4
id Impk
im(t0) im
Imvl id io

t Ld + +
id(t0) C i Lm Cr ur C2 U2
UAC + AC m Np
SAC Ls is +
Uo Ro
iSAC
Ns + -
t C1 U1
iD2 Ug

t
iD1
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0
Reduced active clamp circulating current
39
Converter Operation
Hp: negligible capacitor voltage ripples
id Impk
im(t0) im
Imvl
Interval T56 = t6-t5
t
id(t0)

id io iSAC

Ld D2 t
+
C i Lm C2 U2 iD2 Ug
UAC + AC m Np
SAC Ls is +
Uo Ro
t
Ns + -
iD1
C1 U1
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0

40
Converter Parameters

Input voltage: Ug = 25-35 V


Output voltage: Uo = 400 V
Nominal output power: Po = 300 W
Switching frequency: fs = 100 kHz

Magnetizing inductance: Lm = 20 H
Primary leakage inductance: Ld = 0.4 H
Secondary leakage inductance: Ls = 2 H

41
Experimental Results

Ug = 35 V, Uo = 400 V, Po = 300 W (2s/div)


uD1 [100V/div]

uDS [20V/div]

id [5A/div]

Peaking due to a small dip in the converter


input voltage due to the fast current rise time
42
Experimental Results

Ug = 35 V, Uo = 400 V, Po = 300 W (2s/div)

uD1 [100V/div]

uDS [20V/div]

id [5A/div] The resonant phase

} reduces the active clamp


circulating current

43
Experimental Results

Ug = 35 V, Uo = 400 V, Po = 300 W (2s/div)


390 pF external
Ld D2 +
C
UAC + AC Lm Cr ur C2
+
capacitor added
SAC Ls +
Ug Uo Ro
-
+
S D1 C1

id [5A/div]
The resonant phase

} reduces the active clamp


circulating current

44
Detail of Main Switch Turn On

Ug = 35 V, Uo = 400 V,
Po = 300 W
Time scale: 500ns/div
id Impk uD1 [100V/div]
im(t0) im
Imvl
uDS [20V/div]
t
id(t0)

iSAC

t
iD2 Ug
id [5A/div]

t
iD1 t6 = t0 t1 t2
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0
45
Detail of Main Switch Turn Off

Ug = 35 V, Uo = 400 V,
Po = 300 W
Time scale: 500ns/div
id Impk uD1 [100V/div]
im(t0) im
Imvl
uDS [20V/div]
t
id(t0)

iSAC

t id [5A/div]
iD2 Ug

t
iD1 t3 t4 t5
t
t0 t1 t2 t3 t4 t5 t6=Ts-t0
46
Zero Voltage Switching

Detail of the main switch turn on


(nominal output power)

uGS [5V/div]

uD1 [100V/div]
uDS [20V/div]

id [5A/div]

[200ns/div]

47
Different Operating Mode

Ug = 25 V, Uo = 400 V, Po = 100 W
id io

Ld D2
+
im Lm C2 U2
uD1 [100V/div]
+
Uo Ro
-
uDS [20V/div] +
D1 C1 U1

id [2A/div] D1 turns off during


the switch on interval

48
Measured Efficiency

Power stage only


Po = 300 W

Ug = 35V
0.95 0.94

0.94 0.93
Ug = 25V

0.93 0.92

0.92 0.91
100 150 200 250 300 25 27 29 31 33 35
Po [W] Ug [V]

49
Comments
There are different topologies presented in
literature whose behavior is very similar to
the Integrated Boost-Flyback converter.
These topologies have a drawback of a
discontinuous input current waveform, that
make the use of such converters for higher
power levels at least problematic.
For high power applications, a continuous input
current represents a very nice feature

50
High Step-up Ratio DC-DC
Converter Topologies
Part II
Speaker: G. Spiazzi

P. Tenti, L. Rossetto, G. Spiazzi, S. Buso, P. Mattavelli,


L. Corradini
Dept. of Information Engineering DEI
University of Padova
Seminar Outline
Why we need high step-up ratio converters?
Application fields
Low power high step-up ratio topologies
Coupled inductors
High power high step-up ratio topologies
Non isolated
Isolated

2
Cascaded Boost Converter
i1 L1 D1 i2 L2 D2
Io
Ug U1 C1 C2 U Ro
S1 S2 o

Uo Uo U1 1 1
Voltage conversion ratio: M = = =
Ug U1 Ug 1 d1 1 d2
Reduced S1 and D1 voltage stress
High flexibility
Suitable for high power applications through
interleaving connections
Total power processed twice
High S2 and D2 voltage stress
3
Boost with Voltage Multiplier Cells
i1 L1
ir Lr u2
D
Voltage conversion
Cm2 Io ratio:
Ug Dm1 D Co U Ro
S u1 C m2 o
Uo 2
M=
m1

Voltage multiplier cell


Ug 1 d
Reduced switch and diode voltage stress (UDS Uo/2)
ZCS and soft diode turn off through the use of a resonant
inductor Lr
Suitable for high power applications through interleaving
connections
Maximum and minimum duty-cycle limitation to guarantee
soft commutations
High switch RMS current
Voltage stress reduction related to the number of cells
4
Boost with Voltage Multiplier Cells
i1 L1 D
Io
Ug
S Co U Ro
o

Voltage Voltage Voltage


multiplier multiplier multiplier
cell #1 cell #2 cell #M

Uo M + 1
Voltage conversion ratio: M=
Ug 1 d
Uo
Switch voltage stress: UDS
M+1
5
Converter Operation (CCM)

iL

iD1
iD2

ir

t0 t1 t2 t3 t4 t5
i1 L1 D
Io
Ug
T01 = t1-t0 S Co U Ro
o

6
Converter Operation (CCM)

iL
iD1

iD2
ir

t0 t1 t2 t3 t4 t5
ir Lr u2
i1 L1 D
Cm2 Io
Ug Dm1
T12 = t2-t1 u1 C
Co U Ro
o
m1

7
Converter Operation (CCM)

iL

iD1
iD2
Soft Dm1 turn off

ir

t0 t1 t2 t3 t4 t5
ir Lr u2
i1 L1 D
Cm2 Io
Ug
T23 = t3-t2 Co U Ro
o

8
Converter Operation (CCM)

iL

Soft D turn off


iD1
iD2

ir

t0 t1 t2 t3 t4 t5
ir Lr u2
i1 L1 D
Cm2 Io
Ug
T34 = t4-t3 S Co U Ro
o

9
Converter Operation (CCM)

iL
iD1
iD2 Soft Dm2 turn off

ir

t0 t1 t2 t3 t4 t5
ir Lr u2
i1 L1 D
Cm2 Io
Ug
T45 = t5-t4 S D
u1 C m2
Co U Ro
o
m1

10
Dual Boost Converter
i1 L1 D1

Io
U1
S1 C1

Ug Ig Uo Ro

U2
i2 S2 C2

L2 D2

Uo 1 + d
Voltage conversion ratio: M= =
Ug 1 d

Output voltage of each U1 U 1


M1 = = M2 = 2 =
converter: Ug Ug 1 d

11
Dual Boost Converter
i1 L1 D1

Reduced switch and diode voltage Io


U1
stresses S1 C1

Inductor L1 and L2 rated roughly at U g Ig Uo Ro


half of total input current
Suitable for high power applications i2 S2
U2
C2
through interleaving connections of L2 D2
each module
Need for isolated gate driver
Floating load connection
Limited switch voltage stress
reduction
Penalty in the converter efficiency
(negligible for high conversion ratios)

12
Dual Boost Converter
i1 L1 D1

U1
Io Power processed by each module:
S1 C1
P1 = U1Io = P2 = U2Io = P
Ug Ig Uo Ro

Efficiency of each module:


U2
i2 S2 C2 P1 P1
1 = =
L2 D2 Pg P1 + Pd

Efficiency reduction:
Po Po (U1 + U2 Ug )Io 2P UgIo
T = = = =
Pg Po + 2Pd (U1 + U2 Ug )Io + 2Pd 2(P + Pd ) UgIo

1
1
2M1 2M1 1 M 1M
T = = = =
M+1
1 M + 1 1
1 1 2M1
1
1 2M1 1 1
13
Dual Boost Converter
1M
Efficiency reduction: T =
M + 1 1

0.95
1 = 0.95
Overall efficiency T

0.94
1 = 0.94
0.93
1 = 0.93
0.92

0.91

0.9

0.89
2 3 4 5 6 7 8 9 10
Voltage conversion ratio M

14
Interleaved Boost with Voltage Multiplier
Uo
Io
U1 = U2 =
D1 D2 Uo Ro 2
D4 D3
Voltage conversion
u1 C1 u2 C2

L1 L2
ratio d > 0.5:
i1 i2
Uo 2
S1 Ug S2
M= =
Ug 1 d
Reduced switch and diode voltage stress (Uo/2)
Inductor L1 and L2 rated at half of total input current
Reduced input current ripple due to interleaved
operation
Voltage multiplier cell operation requires d > dmin
More ringing on switch voltage due to capacitor ESL
15
Current Waveforms d > 0.5
S2
S1

i1 i2
Uo
U1 = U2 =
2

iD3 iD4
Io
iD1 iD2
D1 D2 Uo Ro
D4 D3

u1 C1 u2 C2

L1 L2
i1 i2
S1 Ug S2

16
Interleaved Boost with Voltage Multiplier

Ug = 20V, Pg = 1280W, Uo = 400V, Po = 1080W

i2

uo

uDS2
Unbalance due to slightly
uDS1 different switch on times

17
Interleaved Boost with Voltage Multiplier

Ug = 20V, Pg = 1280W, Uo = 400V, Po = 1080W

i1

uo

uDS2
Effect of capacitor ESL and
layout parasitic inductances

uDS1

18
Boost with Voltage Doubler
L1 D3 D2
Io
i12
Ug S1
u2 C2 C Uo Ro
o
Uo
U2 =
L2 i2 2
S2

Uo 2
Voltage conversion ratio d > 0.5: M= =
Ug 1 d
Similar behavior as the interleaved boost
with voltage multiplier
Problem: for d < 0.5 the switch voltage
stress (S1) becomes the output voltage
19
Extension to Higher Step-up Ratios
L1 D1 D2 D3
Io
i1
Ug S1 u3
u2
C2 Co Uo Ro
C3

L2 i2
U3 Uo
U2 = =
S2

2 3
L3 i32
S3

Uo 3
Voltage conversion ratio d > 2/3: M = =
Ug 1 d

20
Boost with Voltage Doubler

Interleaved boost with voltage multiplier


versus Boost with voltage doubler

Io L1 D3 D2
D1 D2 Co Uo Ro Io
D4 D3 i1
Ug S1
u2 C2 C
o
Uo Ro
u1 C1 u2 C2

L1 L2 L2 i2
S2
i1 i2
S1 Ug S2

Similar behavior for duty-cycle higher than


50% but the structure becomes asymmetric
21
Boost with Three-state Switching Cell

D3 is
u3 C3 Voltage conversion
Ns
Io ratio (d > 0.5):
u2 C2
Uo n + 1 1
D2
Uo Ro
M= =
Ug n 1 d
Np D1 Dp
u1 C1
ig
L1
Np Np
n=
Ug
S1 S2
Ns
Reduced switch and diode voltage stress (depending on n)
Reduced input current ripple due to interleaved operation
Voltage multiplier cell operation requires d > dmin
Correct operation requires L > Lmin
Operation modes with very low gain
22
Boost with Three-state Switching Cell
Voltage conversion ratio

u2 = u3 0
DCM operation with
very low gain

23
Interleaved Boost with Coupled Inductors and
Voltage Multiplier

D1 C1 U1
Voltage conversion
ns
is
ns Io
ratio d > dmin (CCM):
D2 C2 U2
im1 Lm
Uo n + 2 1
i1 Ld np Uo Ro M=
D3 Ug n 1 d
ig Ld
np
Ug i2 Np Lm
1
D4
im2 Lm C3 U3 n=
S1 S2
Ns Lm + L d

Normalized switch Usw U3 n


UswN = =
voltage stress: Uo Uo n + 2

24
Interleaved Boost with Coupled Inductors and
Voltage Multiplier
D1 C1 U1
Voltage conversion
ns
is
ns Io
ratio d > dmin (CCM):
D2 C2 U2
im1 Lm
Uo n + 2 1
i1 Ld np Uo Ro M=
D3 Ug n 1 d
ig Ld
np
Ug i2 Np Lm
1
D4
im2 Lm C3 U3 n=
S1 S2
Ns Lm + L d

Reduced switch and diode voltage stress (depending on n)


Reduced input current ripple due to interleaved operation
No reverse recovery losses (ZCS turn on)
Voltage multiplier cell operation requires d > dmin
High switch current stress
25
Operation for d > dmin (CCM)

i2 i1

im1

im2 D1 C1 U1
is Io
ns ns

im1 Lm D2 C2 U2
i1 Ld np Uo Ro
t0 t1 t2 t3 t4 t5 t6 t7 t8
D3
ig Ld
np
Ug i2 D4
T01 = t1-t0 im2 Lm S1 S2 C3 U3

26
Operation for d > dmin (CCM)

i2 Soft D3 turn off

im2

im1
D1 C1 U1
is Io
ns ns
i1
im1 Lm D2 C2 U2
i1 Ld np Uo Ro
t0 t1 t2 t3 t4 t5 t6 t7 t8
D3
ig Ld
np
Ug i2 D4
T12 = t2-t1 im2 Lm S1 S2 C3 U3

27
Operation for d > dmin (CCM)

i2 i1 S1 ZC turn on

im2

im1
D1 C1 U1
is Io
ns ns

im1 Lm D2 C2 U2
i1 Ld np Uo Ro
t0 t1 t2 t3 t4 t5 t6 t7 t8
D3
ig Ld
np
Ug i2 D4
T23 = t3-t2 im2 Lm S1 S2 C3 U3

28
Operation for d > dmin (CCM)
Soft D1 turn off
i2 i1

im2

im1
D1 C1 U1
is Io
ns ns

im1 Lm D2 C2 U2
i1 Ld np Uo Ro
t0 t1 t2 t3 t4 t5 t6 t7 t8
D3
ig Ld
np
Ug i2 D4
T34 = t4-t3 im2 Lm S1 S2 C3 U3

29
Operation for d > dmin (CCM)

i2 i1

im2

im1
D1 C1 U1
is Io
ns ns

im1 Lm D2 C2 U2
i1 Ld np Uo Ro
t0 t1 t2 t3 t4 t5 t6 t7 t8
D3
ig Ld
np
Ug i2 D4
T45 = t5-t4 im2 Lm S1 S2 C3 U3

30
Operation for d > dmin (CCM)

i1
Soft D4 turn off

im2

im1
D1 C1 U1
is Io
i2 ns ns

im1 Lm D2 C2 U2
i1 Ld np Uo Ro
t0 t1 t2 t3 t4 t5 t6 t7 t8
D3
ig Ld
np
Ug i2 D4
T56 = t6-t5 im2 Lm S1 S2 C3 U3

31
Operation for d > dmin (CCM)

i1

im1

im2
D1 C1 U1
is Io
ns ns

D2 C2 U2 i2
im1 Lm
i1 Ld np Uo Ro
D3
t0 t1 t2 t3 t4 t5 t6 t7 t8
ig Ld
np
Ug i2 D4
im2 Lm S1 S2 C3 U3 T67 = t7-t6

32
Operation for d > dmin (CCM)

S2 ZC turn on
i2 i1

im2

im1
D1 C1 U1
is Io
ns ns

im1 Lm D2 C2 U2
i1 Ld np Uo Ro
D3
t0 t1 t2 t3 t4 t5 t6 t7 t8
ig Ld
np
Ug i2 D4
im2 Lm S1 S2 C3 U3 T78 = t8-t7

33
Operation for d < dmin (CCM)
Voltage conversion
i1 i2 ratio d < dmin (CCM):
Uo 1
M=
Im1=im2 Ug 1 2d

Np Lm
n= 1
Ns Lm + L d

 The multiplier cell is disabled (u1 = u2 0, U3 Uo)


 The switch voltage stress becomes equal to the
output voltage
 The magnetizing currents are in phase
34
Voltage Conversion Ratio (CCM)
M
1 n+2 1
35 =
1 2dmin 2 1 dmin
30

25
n = 0.5
20 2
dmin =
15 n+4
Disabled n = 0.7
10 multiplier
cell n=1
5
dmin
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
duty-cycle

35
Minimum Switch Voltage Stress
Usw 1 1
Normalized switch voltage Usw1N =
Uo 1 2dmin M
stress for d = dmin:
n+4
=
nM
Normalized switch voltage
stress at nominal Usw n
Usw 2N =
conditions (d > dmin): Uo 2 + n

Optimum turns ratio: Usw1N = Usw 2N

3 8
nopt = 1 + 1 + (M 1)
M 1 9
36
Minimum Switch Voltage Stress
UswNmin
0.5

0.45

0.4

0.35

0.3

0.25
5 7 9 11 13 15 17 19 21 23 25
M
37
Isolated Interleaved High Gain Converter
Active clamp
Voltage multiplier
UCL CCL
S3 S4
im1 Lm
D1 U1
i1 Ld np
C1 Io
is Uo
ns ns Ro
ig Ld
np
Ug i2 U2 C2
im2 Lm S1 S2 D2

Reduced switch and diode voltage stress


Reduced input current ripple due to interleaved operation
No reverse recovery losses (ZVS-ZCS switch turn on)
Same operation mode independent of duty-cycle value
High switch and winding current RMS value
38
Main Waveforms

i2 i1

im1

im2

im1 Lm
U1
i1 Ld np
C1 Io
t0 t1 t2 t3 t4 t5 t6 Uo
ns ns Ro
ig Ld
np
Ug i2 U2 C2
im2 Lm S2
T01 = t1-t0 S1

39
Main Waveforms
S3 ZV & ZC turn on
i2

im1
im2

i1 UCL CCL S3
im1 Lm
D1 U1
i1 Ld np
C1 Io
t0 t1 t2 t3 t4 t5 t6 is
ns Uo
ig ns Ro
Ld
np
Ug i2 U2 C2
T12 = t2-t1 im2 Lm S2

40
Main Waveforms
S1 ZV & ZC turn on
(i1 is negative when S3
i2
turns off)

im1 im2

i1
im1 Lm
D1 U1
i1 Ld np
C1 Io
t0 t1 t2 t3 t4 t5 t6 is
ns Uo
ig ns Ro
Ld
np
Ug i2 U2 C2
im2 Lm
T23 = t3-t2 S1 S2

41
Main Waveforms

Soft D1 turn off


i2 i1
(no reverse recovery
problem)
im2
im1

im1 Lm
U1
i1 Ld np
C1 Io
t0 t1 t2 t3 t4 t5 t6 Uo
ns ns Ro
ig Ld
np
Ug i2 U2 C2
im2 Lm S2
T34 = t4-t3 S1

42
Main Waveforms

S4 ZV & ZC turn on
i1

im2
im1

UCL CCL S4
i2
im1 Lm
U1
i1 Ld np
C1 Io
t0 t1 i t2 t3 t4 t5 t6
s
ns Uo
ig ns Ro
Ld
np
Ug i2 U2 C2
D2
im2 Lm S1 T45 = t5-t4

43
Main Waveforms

S2 ZV & ZC turn on
(i2 is negative when S4 i1
turns off)

im1
im2

i2
im1 Lm
U1
i1 Ld np
C1 Io
t0 t1 i t2 t3 t4 t5 t6
s
ns Uo
ig ns Ro
Ld
np
Ug i2 U2 C2
im2 Lm D2
S1 S2 T56 = t6-t5

44
Main Waveforms

Soft D2 turn off


i2 i1 (no reverse recovery problem)

im1 im2

t0 t1 t2 t3 t4 t5 t6

T01 = t1-t2

45
Mismatch Sensitivity
In case of parameter and/or duty-cycle mismatch
between the interleaved boost sections severe
current mismatch occurs.
The solution is to employ individual clamp capacitors
for each subsection (in this case, the mismatch is
absorbed by a small difference between the clamp
capacitor voltages)
Individual clamp capacitors
CCL1 CCL2
UCL1 UCL2
S3 S4
im1 Lm
D1 U1
i1 Ld np
C1 Io
is Uo
ns ns Ro
ig Ld
np
Ug i2 U2 C2
im2 Lm S1 S2 D2

46
Isolated Interleaved High Gain Resonant
Converter
Resonant
CCL
capacitors
UCL
S3 S4
im1 Lm
D1 U1
i1 Ld np
C1 Io
Uo
is
ns ns Ro
ig Ld Co
np
Ug i2 U2 C2
im2 Lm S1 S2 D2

 Different operation mode is achieved by reducing


the capacitor value of the voltage multiplier cell
 Half-cycle resonances occur between capacitor C1
and C2 and transformer leakage inductances Ld.

47
Main Waveforms
S1 S2 D1 D2
Hard S1 and S2 turn on T01 = t1-t0 on on off off

Soft D1 and D2 turn off T12 = t2-t1 off on on off


T23 = t3-t2 off on off off
ZV & ZC turn on of S3 and S4
T34 = t4-t3 on on off off
T45 = t5-t4 on off off on
i2 i1 T56 = t6-t5 on off off off

im1 im2

t0 t1 t2 t3 t4 t5 t6
48
Preliminary Experimental Results
Ug = 35V, Uo = 360V, Po = 2500W, fsw = 40kHz

High voltage ripple


on clamp capacitors
u2

is uDS1
Current waveform is
half way between
non resonant and
resonant behaviors

uGS1

49
Conclusions
For high power applications, high step-up converters
working with a quite high input current value should
have a continuous input current absorption.
Interleaved operation at input side helps to reduce
the input current ripple as well as to share the total
input current between different conversion
subsections.
A voltage multiplier at the output side avoids the use
of dissipative snubbers across the output diodes.
Isolated structures operate in the same manner
independent of the duty-cycle value (they are better
than the non-isolated ones)

50