Chapter 4 Switching and Queuing Delay Models 225

CPU Forwarding & Routing

Input port processor
Memory
Network layer Output port

Link layer
Line card Line card

packets

System bus

Figure 4-6: Packet datapath for switching via memory. Also shown in Figure 4-5(a).

Input port Output port Routing processor

NFE processor NFE processor CPU

Network layer Memory

packets
Link layer
Line card Line card

System bus

Figure 4-7: Packet datapath for switching via bus. Also shown in Figure 4-5(b).

a cache. Carefully designed, special purpose ASICs can readily outperform a CPU when making
forwarding decisions, managing queues, and arbitrating access to the bus. Hence, CPUs are being
replaced increasingly by specialized ASICs. The second factor that limits the performance is the
use of a shared busonly one packet may traverse the bus at a time between two Line Cards.
Performance can be increased if multiple packets can be transferred across the bus
simultaneously. This is the reason that a switch fabric is used in high-end routers.
Third-Generation Routers: Switching Fabric. By introducing a hardware-forwarding engine
and replacing the bus with an interconnection network, we reach the architecture shown in Figure
4-5(c). In an interconnection network, multiple Line Cards can communicate with each other
simultaneously greatly increasing the system throughput. Today, the highest performance routers
are designed according to this architecture.

Input Ports
The key functions of input ports are to receive packets and make the forwarding decision. This
spans both link and network layers of the protocol stack.
A network port is not the same as a Line Card. A Line Card supports the link-layer functionality
of a network port, which is receiving and transmitting packets. A Line Card may also support the
network-layer functionality, if the Network Front-End Processor is located on a Line Card as in
Visit http://en.wikipedia.org/wiki/ASIC for information about Application-Specific Integrated Circuits