Im 1507469748

ESE-2018 PRELIMS TEST SERIES
Date: 08th October, 2017
ANSWERS
1. (d) 31. (b) 61. (d) 91. (d) 121. (d)

2. (b) 32. (b) 62. (c) 92. (b) 122. (a)
3. (b) 33. (a) 63. (c) 93. (c) 123. (d)
4. (c) 34. (d) 64. (d) 94. (d) 124. (c)
5. (b) 35. (b) 65. (a) 95. (d) 125. (b)
6. (d) 36. (b) 66. (d) 96. (b) 126. (a)
7. (c) 37. (c) 67. (d) 97. (c) 127. (c)
8. (c) 38. (c) 68. (a) 98. (d) 128. (d)
9. (a) 39. (c) 69. (c) 99. (c) 129. (c)
10. (b) 40. (d) 70. (b) 100. (b) 130. (d)
11. (c) 41. (b) 71. (b) 101. (d) 131. (d)
12. (b) 42. (d) 72. (d) 102. (b) 132. (b)
13. (d) 43. (a) 73. (d) 103. (d) 133. (a)
14. (c) 44. (d) 74. (c) 104. (b) 134. (a)
15. (d) 45. (d) 75. (c) 105. (c) 135. (c)
16. (c) 46. (b) 76. (a) 106. (a) 136. (a)
17. (a) 47. (b) 77. (d) 107. (b) 137. (a)
18. (b) 48. (b) 78. (d) 108. (a) 138. (d)
19. (c) 49. (c) 79. (c) 109. (c) 139. (b)
20. (d) 50. (c) 80. (d) 110. (b) 140. (c)
21. (b) 51. (c) 81. (b) 111. (a) 141. (d)
22. (a) 52. (c) 82. (c) 112. (d) 142. (b)
23. (c) 53. (d) 83. (c) 113. (c) 143. (a)
24. (a) 54. (c) 84. (c) 114. (a) 144. (b)
25. (d) 55. (a) 85. (d) 115. (c) 145. (c)
26. (d) 56. (a) 86. (c) 116. (a) 146. (a)
27. (d) 57. (d) 87. (a) 117. (c) 147. (b)
28. (d) 58. (b) 88. (a) 118. (b) 148. (c)
29. (d) 59. (d) 89. (d) 119. (a) 149. (c)
30. (d) 60. (c) 90. (c) 120. (c) 150. (b)
(2) (Test - 17)-08 October 2017
1. (d) 7. (c)
2. (b) 8. (c)
3. (b) Fetch Cycle Execution Cycle

Cache size = 64 Kbytes = 64210 bytes Main memory CPU register Main memory CPU register
block size = 4 bytes 210 1298 210 PC 210 1298 210 PC

10
64 2 211 5298 AC 211 5298 0012 AC
Number of lines =
4 212 2299 1298 IR 212 2299 1298 IR
= 16 210 = 214
4. (c) 298 0012 298 0012 Load ac
from memory
2-way set anociative cache size = 16 kB 299 0009 299 0009
= 16 210 214 B
R
210 1298 210 PC 210 1298 210 PC
Block size = 256 B
211 5298 0012 AC 211 5298 0024 AC
No. of lines =
212 2299 1298 IR 212 2299 5298 IR
E
cache size 214
26 lines
Block size 256
298 0012 298 0012 Add to ac
from memory
2-way set associative cantains 2 lines per
set
26 T
299 0009 299 0009
S
No. of set = 25 32 set 210 1298 210 PC 210 1298 210 PC
2
211 5298 0024 AC 211 5298 0024 AC
5. (b)
A
212 2299 1298 IR 212 2299 2299 IR
Memory address format
tag line identifying in word id bit 298 0012 298 0012 Store ac
M
cache to memory
x y 5 299 0009 299 0009
Block size = 32 bytes 9. (a)

10. (b)
= 25
S
11. (c)
word id = 5 bit
12. (b)
CPU generates 16 bit address
IE
13. (d)
x + y + 5 = 16
14. (c)
x + y = 11
15. (d)
Cache size
No. of lines in cache =
Block size 16. (c)
16 210 214 17. (a)

=
25 25 The sequence of request of block size:
= 29 300, 50, 200, 50
y = 9 Memory regions
x = 11 9 = 2 20 250 200 350 100
tag bits = 2
6. (d)
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(Test - 17)-08 October 2017 (3)
1. Using first fit policy : All request of block size is allocated to existing
(a) Req. for 300 memory.
20 250 200 350 100 18. (b)
300
19. (c)
Virtual address space = 34 bit

(b) Req. for 50 No. of addressable unit = 234 bytes
20 250 200 350 100
Size of physical memory = 256 MB
50 300 = 256 220 bytes
(c) Req. for 200 = 228 bytes

20 250 200 350 100
Page size = 4kB = 212 bytes
R
50 200 300 No. of pages in physical memory
E
(d) Req. for 50 228 16
20 250 200 350 100 = 12 2
2
T
50 200 300 50 Page number offset
16 12
All request of block size is allocated to existing
S 16-bit is used to represent page number.
memory.
No. of pages in virtual address space.
A
2. Using best fit policy :
20 250 200 350 100 234
= 222
M
12
2
Page number offset

(a) Req. for 300 20 12
bit bit
20 250 200 350 100
S
Since page table entry contains frame number.
300 Page number represents as 16-bit in Physical

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memory = 2 byte
(b) Req. for 50
20 250 200 350 100
No of pages : 222
Page table size : 2 byte 222

300 50
= 2 4 220 byte
(c) Req. for 200 = 8 220 byte
20 250 200 350 100
= 8 MB
200 300 50
20. (d)
(d) Req. for 50 21. (b)

20 250 200 350
22. (a)
200 50 300 50 23. (c)
(4) (Test - 17)-08 October 2017
24. (a)
A
25. (d)
No. of 1s in network Id = 24
Total 1s = 26
NID + SID = 26 AB
Subnet Id = 26 24 AB AB
=2
Number of subnets = 22 = 4
B
26. (d)
Given IP address : 10.1.5.7 [class A]
255.255.255.192
Given subnet mark :
R
NID Host ID AB
Number of 1s in Host Id = 18
E
Number of subnet Id bits = 18 A
18
Number of subnet = 12
27.
30.
(d)
(d)
28. (d)
31. (b)
29. (d)
32. (b)
T So from the given Venn diagram the shaded
S
33. (a) 34. (d) 35. (b) portion is outside A and inside B hence AB
is the correct answer.
36. (b) 37. (c) 38. (c)
53. (d)
A
39. (c) 40. (d) 41. (b)
42. (d) 43. (a) 44. (d) The o/p gate 1 is AB (NAND)
45. (d) 46. (b) 47. (b)
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o/p of gate 2 is AB (NAND operation gets

48. (b) 49. (c) 50. (c) cancelled)
51. (c) o/p of gate 3 is AB (NAND operation)
Given number is hexadecimal by correcting it o/p of gate 4 is C (NAND)
into binary code.
S
o/p of gate 5 is C = C(NAND)

(26)16 = + + + + + + +
0 0 1 0 0 1 1 0 o/p gate 6 is ABC = AB C

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(by demorgans law)

The same o/p can be obtained from option (d)
0 0 1 1 0 1 0 1
i.e. ABC AB C
3 5 Hence option (d) is the right option.
= (35)16
54. (c)
But answer is in decimal system. So converting
The K-map is given in product of sum form i.e.
it into decimal system, we get
f A,B,C M 1,3,5
(35)16 = 3 161 5 160
= 48 + 5 on f A,B,C M 0,2,4,6,7
= (53)10
Solving in any of the above form, we get
52. (c) solution
In a Venn diagram in SOP form Method that 1 POS form
(Test - 17)-08 October 2017 (5)
BC 59. (d)
A 00 01 11 10
RAM : Volatile memory
0 0 0 ROM : Permanent (or) Non volatile memory
PLA : It is RAM chip with both i/p AND o/p OR
gates programmable
1 0
PAL : It is a type of RAM chip where AND
gates are programmable.
Y = A CB C
60. (c) For 1st instruction = Opcode Fetch
= AB C
(4T)+
[From Distribution Law]
Method 2 of SOP form +memory read (3T)
=Total 7 T states
BC
A 00 01 11 10
R
2nd instruction =Opcode Fetch (4T)
0 1 1
=Total 4T states
E
1 1 1 1
3rd instruction =10T states if condition
is satisfied
T
Y = C AB
= 7 T states if condition is not satisfied
55. (a)
w(x + yz) = wx + wyz (distributive law)
S Total T-states =7T + 4T9 + 10T 8 +7T
56. (a)
(Condition not satisfaction at 9th time)
A
It is undesirable state of the bus of
computer.
= 7T + 36 T + 80 T + 7 T
When more than one memory mapped
M
device (or) CPU is attempting to place = 50 T + 80 T

output values onto the bus at once.
Normally IC circuits try to make bus = 130 T-states
contention as nil if the chips are operated
61. (d) (1) FORTRAN is a general purpose,
within the rated set-up times and so forth.
S
procedural, imperative programming

If the buses are driven too fast these setup language that is especially suited to numeric
times may be v iolated leading to computation and scientific computing and
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contention. the language used to drive a microprocessor

57. (d) based system is assembly language hence
statement I is false
Generally the RAM timing permeates
tRC = time taken to a Read cycle (2) The instructions LDA and STA are assembly
language instructions hence statement II is
tWC = time taken to write cycle. Hence option
also false
D.
Hence both the statements I and II are false
58. (b)
To have 16 bits we need 16 flip flops 62. (c)
Each counter = 4 flip-flops Step-1: Move immediate data 12 H into register A
So 4 cascade counters = 16 flip-flops A 0001 0010
The no. of o/p states (or) modulus = 216 Step-2: Move immediate data 24 H into register B
To have modulus of 50000 remove
B 0010 0100
= 65536 50000
Step-3: Add the contents of A and B and store the
= 15536 states
result in accumulator
(6) (Test - 17)-08 October 2017
A 00010010 8421 Code with parity bit : can detect a 1 bit

B 00100100 error.
e.g. 1 : transmitted parity bit
(+)
000 11
A 00110110 (36)H even parity
e.g. 2 : 0 0 1 1 0
Step-4: The data (36)H is sent to the output device
even parity
through output port 25 H. In this case though the parity is matching we
63. (c) TRAP = RST 4.5 = 4.58 = 36 16 36 are not receiving actual message.
2 4 66. (d)
= (0024)H
From the Circuit we can see that in order to
16 44 have the bulb in glowing condition both switches
RST 5.5 = 5.58 = 44 2 C
S1 and S2 should be in OFF condition then
= (002C)H only bulb glows. So putting it in truth table
form:
R
RST 6.5 = 6.58 = 52 16 52
3 4 S1 S 2 Y
= (0034)H
0 0 1 bulb glow
E
RST 7.5 = 7.58 = 60 16 60
0 1 0
3 C
= (003C)H 1 0 0
64. (d) We know that in 8255A
CS = Master chip select

T 1 1 0
The above truth table is the truth table of NOR
gate hence option d is the answer.
S
A0 67. (d)

A1 Connected to MPU address lines Given expression can be solved either by K-
A
map (or) by simplifying the expression.
CS A1 A2 Selected
Y m 0,2,4,6
0 0 0 Port A
M
0 0 1 Port B BC
A BC BC BC BC
0 1 0 Port C
A 1 1
0 1 1 Control Register
1 8255 A is not selected
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A 1 1
65. (a)
2421 Code :
Y = C
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Self complimentary code. If the sum of

positional weights is 9 then that code is self So now solving from the options we get
complimentary code.
II. A A C C [By deMorgans law]
Excess-3 code :
Non weighted code. As there is no positional III. AB AB AB AB C =
weight for each every bit.
Gray Code : A B B A B B C
It also a non weighted code. It also has a [By complementation law]
unique property where successive code words
differ by only one digit hence called cyclic = A 1 A 1 C
code.
[By Complementation law A A 1]
0 0 0 0 }
0 0 0
1 }
= A AC
0 0
1 1 } [By complementation A A 1 ]
0 0 1
0 } Hence statements II and III are correct.
(Test - 17)-08 October 2017 (7)
68. (a) Step-1: The contents of immediate data 07H
is initialised to register Accumulator
Given boolean function F(x, y, z) = xy z xyz
A 0000 0111 1
[standard SOP form]
Step-2: The contents of immediate data 05H
In order to convert it into canonical SOP form
is initialised to register B.
F(x,y, z) = xy z z z x x y y xyz B 0000 0101
= xyz xyz z xy xy xy x y xyz Step-3:Add contents of register A and register
B and store in A
= xyz xyz xy z xyz xyz x y z xyz
A 0000 0111 1
A A A
B( ) 0000 0101
= xyz xyz xy z xyz x y z xyz
A 0000 1100
= 6 minterms
69. (c) Step-4:As the value of data is more than 9
add +6 to the number in order to convert it
In J-K master slave flip flop in order to over
into BCD (Binary coded decimal) and store
R
come race around condition negative edge
result in A
triggered flip flop is used.
A 0000 1100
Sequential Circuit uses memory
E
+ 0110
Flash type is the fastest analog to digital
converter. A 0001 0010
Dual slope ADC is accurate as it charges 75. (c)
T
and discharges. Opcode fetch= OF, memory read = MR
70. (b) Memory write = MW
As we know in K-maps we always combine
the cells in the groups of 2, 21, 22 ..... =
S LHLD 4200 H : L (4200), H (4201)
This instruction is 3 byte instruction with 5
1,2,4,8..... Hence answer is (b). machine cycles
A
71. (b) (OF + MR+MR+MR+MR) =
From the given SOP expression writing it in (4T+3T+3T+3T+3T) = 16T states
terms of minterms F A,BC, m 0,2,3,6 .
M
MVI C, 00H : C 00
Writing the minterms in K-map. The C register is initialised to zero.
It is a 2 byte instruction with 2 machine cycles
00 01 11 10 (OF + MR) = (4T+3T) = 7T states
LDA 4800H : the content of address 4800 is
0 1 1 1
S
transferred to register A
A (4800)
1 1 This is a 3 byte instruction with 4 machine
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cycles
Hence from the options correct answer is B. (OF+MR+MR+MR) = (4T+3T+3T+3T)
72. (d) = 13T states
It is general question whether we know that Total T-states = (16 T+7T+13T) = 36 T states
capacitors are used in D-RAMs Given clock frequency of processor = 2MHz
Flip-flops are used in static RAMS as memory
elements. 1
1-Tstate = = 0.5 sec
73. (d) 2M
From the Ckt diagram in order to have output Total time taken = 36 0.5 sec
of AND gates as 1, we need inputs
= 18 s
Q0 Q 1Q2 = 1 1 1
76. (a)
For Q1 1 , we need Q1 = 0 8051 Micro controller
The o/p of the counter = Q0Q1Q2
8255A Programmable peripheral interface
= 1 0 1 = (5)10 8259AProgrammable interrupt controller
74. (c) 8086 Microprocessor 16-bit
(8) (Test - 17)-08 October 2017
77. (d) clockpulses are shown below.
Stack pointer : It is a 16 bit register:
1 2 3 4 5 6 7 8
It points to the top of the stack
And the address of the stack is 16-bit 0 1 0 1 0 1 0 1 0
address 0 1 1 0 0 1 1 0 0
Program Counter : It is a 16-bit register 0 1 1 1 1 0 0 0 0
It always points to the next address of the
instruction which is to be executed. For x = 0 Q0 is connected to clock of T1
Hence in order to store the address location
it needs 16-bit space hence it is 16 bit Flip-flop Q1 is connected to clock of T2 Flip-
register. flop. Hence Down counter.
Accumulator : It is 8 bit register For x = 1 Q0 is connected to clock of T1 Flip-
Accumulator along with flag register flop. Q1 is connected to clock of T2 flip-flop
becomes PSW (Program states word). It hence Up counter.
isa 16 bit register.
R
81. (b)
B register; It it 8 bit register.
78. (d) I0
I1
E
JMP 1230 H
161
o/p
It is direct addressing mode instruction MUX
in which 1230H is address to which
I 16
instruction jump takes place with out any
condition.
LHLD 2360 H
T 4 data select lines
S
Mode 16
It is direct addressing mode instruction Counter
in which 2360H is address from which data
is loaded to the register pair directly. From the figure we can see that Mod 16 will
A
OUT 75 H have 16 outputs for each output of the Mod-
It is also direct addressing mode 16 counter one data input is selected.
instruction in which 75H is the port address 82. (c)
M
to which the data used to be forwarded. We know for R-2R DAC output voltage.
MVIA 82 H
It is immediate addressing mode in which Vref n 1 i R f
V0 = 2n 2 bi R
82 H data is transferred to A register. i 1
For Rf = R = 1
S
79. (c)
We get
From figure we can see it is a 3-bit Johnson
ring counter and it requires (2n = 2 3 = 6 Vref n 1 i
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states) to reach its initial. V0 = 2n 2 bi

i 1
Method (2) :
0 23 1 22 0 21 1 20
Solving by each clock pulse. = 5 24 24 2 4 24

Q0 Q1 Q2
0 1 0 1
1 1 0 initial value = 5
16 4 8 16
Clock1 1 1 1
1 1 5 25
Clock 2 0 1 1 = 5 = 5 =
4 16 16 16
Clock 3 0 0 1
= 1.5625
Clock 4 0 0 0
83. (c)
Clock 5 1 0 0
Clock 6 1 1 0 Vreff 5
We know resolution = n
= 6 = 0.0156
2 2
80. (d)
The circuit is a ve edge triggered clock ripple Vref
% resolution= 100 0.0156100 = 1.56%
counter and it is a Down counter the 2n
(Test - 17)-08 October 2017 (9)
84. (c)
By solving the states from CLK diagram
Clk Q0 Q1 Q2 Q3
0 1 1 1 0
Initial Value
1 0 1 1 1 unused states
2 0 0 1 1
3 0 0 0 1 Initial Value
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1 Initial Value
(PC) PC(PC+1) Memory Database

RD = 0
8 Address Database IRdecode
Bus
R
14 7 3 1 4
during T1 -state both A15-A8 (higher order)
Unused states 2 address bus and A7-A0 (lower order) address
E
bus carry address.
Hence, Mod 4 counter 88. (a) MVI A, 04 H
T
85. (d) A 04H
From the given circuit diagram RLC (Rotate left with out carry)
whenever Z = 0 Mux gets enabled
S 0
Z = 1 Mux gets disabled. cy 0
0 0 0 0 1 0 0 0
A
y z A 08H
x y z S1 S 0 F x,y,z MOV B, A
M
0 0 0 1 0 I2 0 B 08H
0 1 0 0 0 I0 0
RLC
1 0 0 1 0 I2 0
1 1 0 0 0 I0 1 x,y, z 0
cy 0
0 0 0 1 0 0 0 0
86. (c)
S
A (10)H
Drawing the truth table for 4 1 MUX.
89. (d)
IE
x y F
(1) MVI A, C5H
0 0 1
A C5H
0 1 0
(2) ORA A
1 0 0
A 1100 0101
1 1 1
1100 0101
F(x, y) = m 0,3 A 1100 0101
87. (a) A C5H
We can find out from the timing diagram of (3) RAL (Rotate accumulator Left with carry)
opcode fetch machine cycle. cy
1
1 0 0 0 1 0 1 0
8 A
A (8A)H
(10) (Test - 17)-08 October 2017
(4) RRC (Rotate right with out carry) Whenever the RET instruction is executed
cy at the end of the subroutine.
1
The data stored on the top of stock during
the call instruction is transfered back to
0 1 0 0 1 1 0 1
the program counter.
4 5
A (45)H 94. (d)
90. (c) (1) MVI A, 07 H
8 kb
= 1kb = 1024 = 210
A 0000 0111
1 A = (07)H 8
Rotate Left = (07)10 given 128 rows = 27
(2) RLC (without carry) 210

= 23 - columns
27
7 X address and 3 Y address are needed.
cy
R
0 0 0 0 0 1 1 1 0 95. (d)
E
PUSH instruction is used to load the 16-
0
bit data into stack.
E
A (OE)H
POP instruction is used to read the 16-
(3) MOV B, A bit data from stack.
(4) RLC
B (OE)H
T In CALL instruction, the 16-bit address

of next instruction to be executed is first
stored in program counter and then stored
S
in stack from program counter.
cy
96. (b)
A
0 0 0 0 1 1 1 0 0
1 C F1 = A 0 1 if A 0
A (1C)H
= 0 if A 1
M
(5) RLC
i.e. F1 = A
F2 = A 0 0 if A 0
cy
0 0 0 1 1 1 0 0 0 = 1 if A 1
]
i.e. F2 = A
S
3 8
A(38)H A (46)H
So, F = F1 F2
(6) ADD B = AA = 1
IE
A (46)H = (70)10 97. (c)

4
91. (d) 2
2
W hen ev er a CALL instruction is 2+1=3
approached the next instruction address 2
1
after the CALL instruction present in the 2
program counter is loaded on to the stack.
Now the program counter is stored with 21
the address mentioned in the call
instructions.
cs 21
92. (b) RST 7 7 8 = (56)10
21 cs
16 56
= (0038)H
3 8
cs
93. (c)
41 Multiplexer
(Test - 17)-08 October 2017 (11)
98. (d) 102. (b)

99. (c) When zero or negative control input voltage is
applied, the transistor is OFF. The capacitor
Differential gain,
charges up from the Op-Amp output, through C
Ad,dB = 60 dB and Rin, to V. The charge rate is given as
20 log Ad = 60 dB
V
Ad = 103 Charge rate = R C
in
Similarly, CMRRdB=80dB i.e. CMRR = 104 If the control voltage is not changed, the
Vd = V1V2 = 12 mV 8mV = 4mV capacitor C will eventually charge up and hold
the output at +Vsat .
V1 V2
VCM = = 10 mV When a positive control input is applied, the
2
transistor is ON. If this voltage is large enough
1 VCM to drive the transistor into saturation, then
Output voltage,Vo= A d Vd 1 CMRR V
d capacitor is short circuited and thus discharges
R
1 10m rapidly.
3
= 10 4m 1 4
10 4m v0
E
= 4 + 0.25 m
Vsat
= 4.00025 V
T
100. (b)
The given circuit is an instrumentation amplifier,
providing an output based on the difference t
between two inputs. It is a differential amplifier
S Control
optimized for high input impedance and high input
A
CMRR. It is typically used in applications in
which a small difference voltage and a large
common mode voltage are the inputs.
M
t
Analysis of the above circuit yields following
equations:
103. (d)
R1 R1
V3 = 1 R V1 R VCM V2 The 1st section of the shown Wide Bandpass
p p
filter is a High-pass filter and its low cut-off
S
R2 R2 frequency can be found as

V4 = 1 R V2 R VCM V2
p p
1
fL = 0.032 kHz
Output voltage,
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2R1C1
2R
V5 V4 V3 1 V2 V1 , The 2nd section is a Low-pass filter and its high
Rp cut-off frequency can be found as
(for R3 = R4 = R5 = R6 and R1 = R2 = R)
1
fH = 2R C 3.979 kHz
2 2
101. (d)
The circuit given represents an Op-Amp Square Bandwidth of the wide bandpass filter
Wave generator. It is also known as Free-running = fH fL
or Astable multivibrator. (Statement 1 and 2 = 3.947 kHz 3.95 kHz
are true). = (3.978 0.032)kHz
The output of the above circuit is a square wave 104. (b)
and its time period is given by
Quadrature component of modulated wave is a
1 R3 filtered version of message signal and is used
T = 2R f Cln 1 , where R R to eliminate one of the sidebands thereby
2 3
modifying the spectral of modulated wave.
(Statement 3 is true)
(12) (Test - 17)-08 October 2017
105. (c) 1600 1

= 1
s(t) = Acm(t)cos2fc t y(t) 2 1 2
P T = 1200 W
Accos2fct Modulation efficiency
y(t) = A c m(t)cos 2fc t A c cos2fc t PSB 2 200
= P = = 33.3%
T 1200
y(t) = A c [1 m(t)]cos 2fc t
111. (a)
= AM signal (K a 1)
m2
106. (a) PT = C 1 2
P

Vmax= 3V, Vmin = 1V
(0.5)2
Vmax Vmin 3 1
Modulation index = V 0.5 P T = PC 1 2
max Vmin 3 1
R
107. (b) P C = 0.89PT
Here, Vmax = 2.5 V and Vmin = 0.5 V 89% is carrier power and hence 11% is sideband
E
power.
Modulation index
112. (d)
Vmax Vmin 2.5 (0.5) 3
108. (a)
= V
max Vmin
=
2.5 ( 0.5)
=
2
T m2
Total power in AM = PT = C 1 2
P

S
Here, f c + f m = 5500 As m increases PT increases
f c f m = 5000
A 2c
A
PC = = independent of m
5500 5000 2R
fc =
2
113. (c)
M
= 5250 kHz
109. (c) m2
PT = Pc 1 2

Am 4
Modulation Index = A 5 0.8 (ratio of 50 2 A2
c
Pc = 33.33 = c
S
3 2R
message signal voltage of carrier signal voltage)
Ac = 33.33 2 8.16V
A 2c m2
IE
Total power = 2R 1 2 Peak amplitude of carrier after modulation =

Ac(1 + m)
25 (0.8)2 Vmax = 8.16 2 = 16.32 V
= 2 10 1 2 = 1.65 W

110. (b) 114. (a)
PLSB = PUSB The above circuit represents a Pulse generator

m 2
A c2
and it is also called as Monostable or One-shot
= multivibrator. (Statements 1 and 2 are true)
8R
The pulse width of the output wave is given by
= 200
200 8 1 V0
A 2c = = 1600 1 V
1 R f C ln out
tpw = 1
A 2c m2
Total power P T = 2R 1 2

(Test - 17)-08 October 2017 (13)
1 = 2f Vm
= R f C ln ,
1 Now, SR 2f Vm
for VD Vout 0.8V s 2f 3
(Statement 3 is false) 0.8
f M = 42.44 kHz
3 2
115. (c) f max = 42.44 kHz
118. (b)
P. The circuit shown is a first-order Low-pass
When switch S is off.
filter. The high cut-off frequency, (f H) is given by
4k 10k
1
fH = 7.96 kHz
2RC
vi
Q. The circuit given is a second-order Low-
v0
2k 6k
pass filter and its high cut-off frequency is given +
R
by
Switch S
1
fH = 1kHz
E
2 RCRC
R. The circuit shown is a first order high-pass 10k
Aoff,non-inverting = 1
filter and its low cut-off frequency is given by 4k
T
= 3.5
1
fL = 7.96 kHz Rf 10k
2RC
= R 4k 2.5
S. The circuit shown is a second-order high
S Aoff,inverting
1
pass filter and its low cut-off frequency is given A of f =Aoff,non-inverting + Aoff,inverting
by =3.5 2.5 = 1
A
1 When switch S in on.
fL = 1kHz
2 RCRC Voltage at node 1, V1 = 0 V
M
4k 0V 10k
116. (a)
1
For 555 timer, used as an astable multivibrator
vi
circuit,
v0
0V
+
THigh
S
2k 6k
Duty cycle, D =
T
0.693 R A RB C
IE
= 0.693 R 2R 100%
A B Rf 10k
AON = 2.5
R1 4k
1k 80k
= 100% 119. (a)
1k 2 80k
= 50.3% From the circuit,
117. (c) R1
1
Slew rate (SR) is given by VS +
AV V0

dvo 2 nR
SR =
dt maximum
R
For vo = Vm cos t ,
dvo R
SR = V2 = Vo
dt maximum R nR
= Vm sin (t) V
maximum
= o
n 1
(14) (Test - 17)-08 October 2017
Also, Linear applications of Op-Amp are Summing

V0 =AV(V1 V2) = AV (VSV2) amplifier, voltage-to-current converter, current-to-
voltage converter, Difference amplifier, Integrator,
Vo Differentiator, Active filters, etc.
V0 = A V VS A V
n 1
Non-linear applications of Op-Amp includes
A comparators, Sample-and-hold circuit, precision
V0 1 V = AV VS
n 1 rectifier, Logarithmic amplifier, Antilog amplifier,
V0 AV 1 Schmitt trigger, etc.
AVf = V A

1 1
S 1 V 122. (a)
n 1 n 1 AV
Vmax = Ac(1 + m) = 10 V
1
A vf = n 1. Vmin = Ac(1 m) = 4V
A v 1 1

n 1 AV Vmax + Vmin = Ac + Acm + Ac Acm
A V
120. (c) Vmax Vmin
R
Ac = 7V
When a positive pulse of Vs appears at the gate 2
of E-MOSFET, it starts conducting and thus acts 123. (d)
as a closed switch. This allows the input voltage
E
IC = 8A and IT = 10A
to charge capacitor C i.e. input voltage appears
at the output. m2
When VS becomes zero, E-MOSFET is off and
acts as an open switch. Capacitor C discharges
through the Op-amp follower, which is of high T
IT = IC 1

2
m2 10
2
S
1
input resistance. Thus capacitor C holds the 2 8
charge and voltage across it remains constant.
m2
A
The time periods during which capacitor C 0.5625
charges or positive pulse is applied are called 2
sample periods. m 1.125 1.06
M
The time periods during which voltage across 124. (c)

capacitor C is held constant or gate pulse is
3
absent are called the hold periods. s(t) = 10[1 0.4cos(2 10 t)
0.8 sin(2 10 4 t)]cos(2 108 t)
i
S
m1 = 0.4 and m2 = 0.8
Net modulation index m = m12 m22

IE
m2 = (0.4)2 + (0.8)2 = 0.8

t Modulation Efficiency
MOSFET ON
Vs m2 0.8
MOSFET OFF = 2
28.57%
2m 2 0.8
t 125. (b)
o 4
s(t) = 20[1 0.3 sin(2 10 t)
0.4cos(2 105 t)]cos(2 109 t)
Here, m1 = 0.3, m2 = 0.4

t
m = m12 m22 = 0.3 2 0.4 2 0.5
Thus, the given circuit is sample-and-Hold m2 A 2c m2
circuits. PT = PC 1 1
2 2R 2
121. (d)
(Test - 17)-08 October 2017 (15)
COSTAS receiver can be used only for

20 20 (0.5)2
PT = 1 225W demodulation of DSB-SC signal.
21 2
Also, 134. (a)
Phase detector
fm1 104 Hz and fm2 10 5 Hz
Bandwidth = 2 Highest frequency component S FM(t) LPF V0(t)

of message signal
= 2 105 Hz
VCO
= 200 kHz
Phase locked loop
126. (a)
135. (c)
DSB with carrier or AM wave can be generated
using: At low audio frequencies a noise called flicker
or modulation noise is found in transistor.
(i) Square law Modulator
R
Rest are external noise.
(ii) Switching Modulator
136. (a)
127. (c)
Noise figure of cascaded stage is given as
E
Square law Demodulator and Envelope Detector
are used only to detect AM with m 1. F2 1
F = F1 G
T
128. (d) a1
Square law Demodulator and Envelope Detector

11 1
= 16 18dB
are used only to detect AM with m 1. For any
S 5
value of m, Synchronous Detector can be used.
137. (a)
A
129. (c)
Sampling frequency f s 2f m
Square law Modulator uses diode with its non
linear characteristic fs 2 1.6 KHz
M
V2 = aV1 + bV12.
nfs Rb = 18000
130. (d)
For a square law demodulator: Rb 18000
n = 5.6
fs 3200
S 2
S
=
N max m n= 5
S Rb 18000
For m = 0.1, will be maximum.
IE
N fs = 3.6KHz
n 5
131. (d)
138. (d)
Hilbert Transform or Wide Band Phase Shifter
is used in Phase Discrimination method of Given fm = 10KHz
SSB-SC to provide 90 phase shift for all fs = 2 10 = 20 KHz (Nyquist rate)
components of message signal. L = 32 = 24
132. (b)
n = 5 bits
Wide-band Phase Shifter or Hilbert Transform
Bit Rate = 20KHz 5
circuit is very difficult to construct which is
used in Phase Discrimination Method. Narrow = 100 kbps
Band Phase Shifter can be realised for phase 139. (b)
shifting of one frequency component. Hence,
Noise figure is defined as ratio of signal to
it is useful for generating single tone SSB
noise power supplied to input terminals of
signal.
receiver to signal to noise power supplied to
133. (a) output.
(16) (Test - 17)-08 October 2017
140. (c) 144. (b)

For purpose of comparing different modulation In Mid-rise quantizer, input value between 0
scheme the receiv er perf ormance is and 1 is mapped to an output value of 0.5.
normalised by dividing the output signal to 145. (c)
noise ratio by channel signal to noise ratio.
This is called figure of merit. For BPSK system, probability of error is given
as
(SNR)O
FOM = 1 E
(SNR)C erfc b
Pe =
2
141. (d)
Giv en, receiv er noise resistance = 146. (a)
100 Re q Active filters use amplifier (generally Op-Amp)
with R-C networks. High frequency response of
Noise figure F = 3
active filters is limited by the gain-bandwid and
R
Re q slew rate of Op-Amp. High frequency Op-Amps
We have, F = 1 are expensive. Thus, active filters are not used
Ra
for RF applications.
E
100
3 = 1 R 147. (b)
a
142.
Ra = 50 input resistance of antenna
(b)
T SNR = signal energy/noise energy
(SNR)dB = 10 log
S
S
N
x(t) = 10 cos(2000t)cos(3000t)
when S = N, (SNR)dB = Zero
= 5 cos(1000t) cos(5000 t)
A
148. (c)
Highest frequency component
= 2500Hz In case of TDM system, signals from different
M
channels are not applied to the system

Hence,Nyquist rate = 2 2500 = 5000Hz simultaneously as they are allotted different
1 time slot, hence, immune to interference. The
The Nyquist interval = 0.2msec circuitory needed in TDM system is much
5000
simple than needed is FDM system.
143. (a)
S
For a raised cosine pulses 149. (c)

Assertion is true
1
IE
B = Hz Reason is not true because the o/p is

2Tb
connected back to the i/p in the ring counter
Here we have B = 100 KHz as shown below. Hence reason is false.
1 Q2 Q1
Rb = 0.2Mbps T Q0
o/p
b D2 Q2 D1 Q1 D0 Q0
1
Tb = 6
5 106 second Q2 Q1 Q0
0.2 10
C/K
1
B = 2T 150. (b) Assertion is true
b
Reason is also true
1 = 2B Tb
but both are independent statements so R
1 = 2100103 5 106 is not the explanation of A.
1 = 1 = 0
(Ideal low pass filter)

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ESE-2018 PRELIMS TEST SERIES

Date: 08th October, 2017

1. (d) 31. (b) 61. (d) 91. (d) 121. (d)

3. (b) Fetch Cycle Execution Cycle

block size = 4 bytes 210 1298 210 PC 210 1298 210 PC

Block size = 32 bytes 9. (a)

16 210 214 17. (a)

Virtual address space = 34 bit

(c) Req. for 200 = 228 bytes

Page number offset

Since page table entry contains frame number.

300 Page number represents as 16-bit in Physical

Page table size : 2 byte 222

(d) Req. for 50 21. (b)

200 50 300 50 23. (c)

o/p of gate 2 is AB (NAND operation gets

o/p of gate 5 is C = C(NAND)

0 0 1 0 0 1 1 0 o/p gate 6 is ABC = AB C

(by demorgans law)

device (or) CPU is attempting to place = 50 T + 80 T

procedural, imperative programming

contention. the language used to drive a microprocessor

A 00010010 8421 Code with parity bit : can detect a 1 bit

CS = Master chip select

Self complimentary code. If the sum of

states) to reach its initial. V0 = 2n 2 bi

(PC) PC(PC+1) Memory Database

(2) RLC (without carry) 210

T In CALL instruction, the 16-bit address

A (46)H = (70)10 97. (c)

98. (d) 102. (b)

R2 R2 frequency can be found as

105. (c) 1600 1

Total power = 2R 1 2 Peak amplitude of carrier after modulation =

PLSB = PUSB The above circuit represents a Pulse generator

Also, Linear applications of Op-Amp are Summing

120. (c) Vmax Vmin

The time periods during which voltage across 124. (c)

m1 = 0.4 and m2 = 0.8

Net modulation index m = m12 m22

m2 = (0.4)2 + (0.8)2 = 0.8

Here, m1 = 0.3, m2 = 0.4

COSTAS receiver can be used only for

Bandwidth = 2 Highest frequency component S FM(t) LPF V0(t)

Square law Demodulator and Envelope Detector

140. (c) 144. (b)

channels are not applied to the system

For a raised cosine pulses 149. (c)

B = Hz Reason is not true because the o/p is

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