EE370

Digital Electronics

L11: Logic synthesis _part-1

(minimization)

B. Mazhari
Dept. of EE, IIT Kanpur

172
G-Number
B. Mazhari, IITK
Clock cycles per instruction: CPI

Instruction cycles
LDA 5020 13
ADD B 4
MVIB,20 7
MOVB,M 7
Call 5020 18
RET 10
SPHL 6
LHLD 16

Average cycles/instruction: CPI ~ 7

1 cycle ~ 1/3MHz = 0.33s 1 instruction ~ 2s

No. of instructions/ second ~ 0.5 MIPS

1
Performance = fclk Performance = IPCfclk
CPI 173
G-Number
B. Mazhari, IITK
Instruction pipelining to improve CPI
MOV B, M

1. MOV B, M Fetch Decode Execute

CPI~3
Fetch Decode Execute
2. RLC

174
G-Number
B. Mazhari, IITK
Instruction pipelining to improve CPI
Performance = IPCfclk
1976, 8085 Tr~6500
~(1/7) x 3~0.5 MIPS 1994, Intel Pentium
~1.88 x 100=188 MIPS
Tr~3M
1. MOV B, M Fetch Decode Execute Cache~16kb

2. RLC
Fetch Decode Execute

3. MOVC,A
Fetch Decode Execute
CPI~1

Fetch Decode Execute

Fetch Decode Execute

175
G-Number
B. Mazhari, IITK
Logic vs DRAM Memory delay
60% per year

10% per year

Borker, future of mp

176
G-Number
B. Mazhari, IITK
Logic vs DRAM delay

CPU
DRAM

MVI B, 35H
Loop 2: MVI C,FEH
CPU SRAM DRAM Loop1: DCR C
Cache
JNZ Loop1
DCR B
2ns JNZ Loop2
100ns
177
G-Number
B. Mazhari, IITK
Multi-level Cache

L1
d-Cache L3
CPU L2 i-Cache
Cache main
R L1 memory
i-Cache
1
3 10 DRAM
40
Latency:
180 cycles

178
G-Number
B. Mazhari, IITK
 ~8 billion units sold in 2013
Microcontroller

4K ROM
128 bytes RAM
4 8-bit ports
2 timer counters.

8051
179
G-Number
B. Mazhari, IITK
 Logic Synthesis
S0 a b c d
R1 a R3 c LD5 LD1 LD3
R2 b R4 d R5 R1 R2 R3 R4
LD2 LD4

S1 Sel1
Sel0 Mux1 Mux2 Sel2
R5 R1 + R 2

S2
R5 R5 + R 3
Adder
S3
R5 R5 + R4

P. State N. State LD1-5Sel0-2

S0 S1 11110XXX
S1 S2 00001100
S2 S3 00001001
S3 S0 00001010

180
G-Number
B. Mazhari, IITK
 Boolean expression Gate netlist

Minimization
Two level
Multi-level

Technology mapping

Objective : Minimize area; delay ; power

181
G-Number
B. Mazhari, IITK
Area Minimization

What does area mean at logic abstraction level?

-No. of gates & type of gate (NAND,AOI,XOR.)

-Fan-in of gates (wires?)

-goal of area minimization may be expressed as:

Minimize the number of gates

Minimize the complexity of gates
Minimize the Fan-in of the gates

182
G-Number
B. Mazhari, IITK
Delay Minimization

Delay would be determined by the sum of delays of

gates on the worst-case path through the gate netlist.

Delay would depend on :

Number of levels in the worst case path

Complexity of gates in the path including fan-in
Fan-out of the gates

The number of levels of logic can be traded with

complexity/Fan-in of the gates
183
G-Number
B. Mazhari, IITK
 184
G-Number
B. Mazhari, IITK
Two Levels of Logic

SOP : Y = x1x2x3 + x1x4 +..

Minimize no. of gates minimize no. of product terms

Minimization of Fan-in of gates

minimizing the number of literals in each product term
185
G-Number
B. Mazhari, IITK
Two Level Minimization SOP : Y = x1x2x3 + x1x4 +

minimize the number of product terms

minimize the number of literals in each term

K-map : xy x y x

No. of product terms and no. of literals are reduced

186
G-Number
B. Mazhari, IITK
KMAP

xy x y x

To apply this principle one has to search Boolean exp.

or truth table for suitable pairs of product terms

Kmap facilitates this search process

Q1Q0
x 0 0 0 1 1 1 1 0

0 1 0 0 1

1 0 1 0 1

D1 = Q1 Q0 + x Q0 + x Q1 Q0
187
G-Number
B. Mazhari, IITK