Exercise 1: Introduction to Xilinx Tools

Name: Syed Ahmed

Class: CMPE 660 Reconfigurable Computing
Section: 01
Professor: Marcin Lukowiak
TAs: Cody Tinker, Dan Stafford
Date: September 11th 2017
Abstract

The purpose of this exercise was to get familiarized with digital design using the Xilinx
Vivado Software Tools and the Nexys4 Artix-7 FPGA board. A tutorial for implementing a counter
that counts from 0 to 256 was followed, analyzed and deployed in the Nexys4 board. Following
the tutorial, a generic N-bit sequential up-down counter with asynchronous active-low reset, a
synchronous parallel load, and a clock enable was written. The generic up-down counter was then
instantiated as a 4-bit up-down counter in a test bench and tested with different stimuli such as,
testing for up/down count, testing parallel load, and testing asynchronous reset. The test bench was
then simulated in the Xilinx Vivado simulator and the simulation was checked for functional
correctness. After the simulation was checked to be correct, the design was synthesized in Vivado
and the implementation was run. The bit stream was then generated from the implementation and
programmed into the device. The program was then run in the device and the exercise was found
to be successful after verifying the LED outputs against the waveforms in the simulation.

Design Methodology

First, the code for the up counter in the tutorial was analyzed. The code for the up counter
provided two implementations of the clock process one which ran faster and the other which ran
slower. The faster running clock was used to visualize the waveforms in the simulation and the
slower clock was used in the synthesized design, so that it was easier to see the behavior of the
counter. Figure 1 shows waveforms that demonstrates the functionality of the counter for the faster
running clock.

Figure 1 Waveforms showing counter functionality with the faster clock

From Figure 1, it is seen that the clock divider makes the clock enable HIGH after a certain
count on the sclk_divider. In this case, when the clock divider reaches the value of 2, the clock
enable becomes HIGH. When the clock enable becomes HIGH the counter is incremented by 1. It
is to be noted that the reset functionality is active-high and asynchronous, i.e. the counter becomes
zero as soon as the reset is set to HIGH, but not on the rising edge of the clock. The up-counters
test bench was then simulated in the Xilinx Vivado Simulator and checked for functional
correctness against Figure 1. The design was then synthesized and implemented, and the bit stream
was generated and programmed into the device. The LED outputs was then checked against the
simulation when given different inputs.

After the tutorial was successfully completed, a VHDL design for an up-down counter was
written. The up-down had a synchronous control signal called UP that would select whether to
count forward by 1 or decrement by 1. Moreover, the counter had an asynchronous active-low
reset and a parallel load signal with a load enable. Figure 2 shows the RTL diagram drawn before
writing the VHDL code.

Figure 2 RTL Diagram of Up-Down Counter

A test bench was then written for this up-down counter unit and following test cases were
inserted as stimuli to the circuit:

Test for counting upwards

Test for overflow
Test counting downwards
Test for asynchronous reset
Test for synchronous parallel load

After the simulation was checked for functional correctness, the circuit was then synthesized
and implemented, and the bit stream was generated and programmed into the device. The program
was then run on the device with various inputs and the LED outputs were matched against the
simulation results to verify the circuit.
Results and Analysis

Figure 3 shows the simulation results obtained from simulating the Up counter in the

Figure 3 Simulation Results from Tutorial on Up Counter

tutorial. It can be seen in Figure 3 that the Up counter circuit is functionally correct since, the
waveforms reflect the waveforms derived by analyzing the code in Figure 1.

Figure 4 shows the simulation results obtained from simulating the 4 bit up-down
counter.

Conclusion

Up counting Overflow Parallel Async Down

Load Reset counting

Figure 4 Simulation Results of 4-bit Up/Down Counter

As seen from Figure 4, the up-down counter functions correctly. It first counts to 15 and
then overflows and starts from 0 again, since an unsigned standard logic was used for
incrementing the counter, and thats why the circuit cannot handle signed integers. The parallel
load functionality is demonstrated, when the load enable is HIGH and the value of 2 is present in
the load_in signal. The counter loads the value of two in the rising edge of the clock. Similarly,
the functionality of the asynchronous reset signal is demonstrated when the reset is LOW and the
counter immediately sets to zero. Moreover, the down counting functionality is demonstrated
when the up signal is LOW and the circuit correctly counts to 0 and overflows. Figure 5 shows
the generated RTL schematic from the synthesized code.
 Figure 5 Generated RTL Diagram of Up/Down Counter
As seen from Figure 5, the circuit is similar to Figure 2 and hence is correct.

Conclusion

In this exercise, Xilinx Vivado Software Tools were used to design, simulate, synthesize
and deploy counters on the Nexys4 Artix-7 FPGA board. The designed circuits were verified
through simulation in Vivado simulator. By inputting different values in the programmed FPGA
board, the simulation and LED outputs were checked for parity and the circuits were verified to
be correct. Moreover, design cycle of a digital logic unit in FPGA was learned in this exercise.