CS211 Digital System

Introduction to VHDL

JaeGeuk Kim
jgkim@camars.kaist.ac.kr
Hardware Description Lang. (HDL)
Hardware Description Language (HDL)
A software programming language that is used to model a piece of
hardware
Verilog-HDL, VHDL, SystemC, ABEL
VHDL(VHSIC HDL)
1980 USA Department of Defense
1987 IEEE Standard 1076
Verilog HDL
1981 Gateway Design Automation
1995 IEEE Standard 1364
Difference between VHDL and Verilog
9On the surface, not that much.
9Both are IEEE standards and are
supported by all the major EDA vendors.
9Both can be used for designing ASICs and
simulating systems.
9VHDL requires longer to learn and is not
so amenable to quick-and-dirty coding.
9Many engineers will one day be bi-lingual
in both VHDL and Verilog.

Introduction to VHDL 2 / 30
Introduction to VHDL
Designed to describe the behavior of the digital
systems
Used as an input to commercial synthesis tools(only
subsets of VHDL are synthesizable)
VHDL is concurrent
4 value logic(0, 1, x, z)
HDL which provides a wide range of levels of
abstraction
Architectural, Algorithmic, RTL, Gate, Switch
VHDL has hierarchical design units

Introduction to VHDL 3 / 30
Levels of abstraction
Behavioral level
Describes a system in terms of what it does(or how it behaves)]
Specifies the relationship between the input and output signals
Structural level
Describes a system as interconnection of gates and components
Compared to a schematic of interconnected logic gates

Introduction to VHDL 4 / 30
Test bench
Objectives
VHDL simulator generates test results from the VHDL source code
and test bench
Test bench puts the input stimulus and gets output signals, and
present the results into text or waveform
Automatically provide pass/fail indication
Writing in the same HDL as the hardware model
No need to learn a special tool
Transportable across different design tools

Input Output
VHDL design
stimulus signals

Introduction to VHDL 5 / 30
 Dynamic timing analysis

Typical Design Flow

Use input vector(relies on quality and coverage of testbench)
Long run time: bottleneck for large complex design
Static timing analysis
Exhaustive method of analyzing, validating the performance
Identification of critical paths
HDL design : behavioral or
False path induce violations structural description of design
RTL Simulation verifies logic
model & data flow. The simulation
is typically performed to confirm
that the code is functioning as
intended. At this step, no timing
information is provided.
Post-Synthesis Simulation :
SDF(standard delay format)-timing
info. of each cell in the design.
The place and route tools are
used for layout generation.
HDL Timing Simulation(Post-
Layout Sim) : after the design has
completed the PnR, simulation
with back-annotated information.

Introduction to VHDL 6 / 30
Synthesis
Logic synthesis
Translating VHDL to a circuit and then optimizing the represented circuit

translation optimization mapping

Translation and optimization

if (S=‘1’) then
Y <= ‘1’ ‘1’ A Y
A S
else
Y <= A;
end if
S
Mapping
Modifying to optimized logic circuits using components of target library
Netlist of generic gates netlist of specific technology gates

Introduction to VHDL 7 / 30
Synthesis results

Introduction to VHDL 8 / 30
Typical Design Flow in FPGA
synthesis implementation Programming file generation

Synthesis
Generating netlist of generic gate
Implementation
Optimization, mapping, place and route
Place and route in FPGA
Determining that which parts need to be activated in already existing
layout of FPGA chip
Programming file generation
Generate and store bit-stream file from the implemented results

Introduction to VHDL 9 / 30
VHDL Program structure
Circuit module
Entity declaration + architecture body

A VHDL entity is a simple declaration of a module’s inputs and

outputs.
A VHDL architecture is a detailed description of module’s
internal structure or behavior.

Introduction to VHDL 10 / 30
Basic lexical conventions of VHDL
Entity exampl1 IS
PORT (x1,x2,x3: IN BIT; -- input signals
f : OUT BIT); -- output signal
END example1;

Comments
begin with two hyphens (--) and end at the end of a line
VHDL
defines many special character strings called Reserved words (keywords).
User defined identifiers
begin with a letter and contain letters, digits, and underscores.
E.g., 7AB, PI_, SUM__1
Reserved words and identifiers are not case sensitive.
Introduction to VHDL 11 / 30
Syntax of a VHDL entity declaration
Entity entity-name is
port ( signal-names : <mode> <signal type>;
…
signal-names : <mode> <signal type>);
End entity-name;
Entity-name
a user selected identifier to name the entity.
Port
models data input/output
Signal-names
a comma-separated list of one or more user-selected identifiers to
name external-interface signal.
Introduction to VHDL 12 / 30
Syntax of a VHDL entity declaration
Mode : specifying the signal direction
In : the signal is an input to the entity.
Out : the signal is an output of the entity.
Buffer: the signal is an output of the entity, and its value can also
be read and written inside the entity’s architecture.
Inout: the signal can be read as an input or an output of the entity.
This mode is typically used for three-state input/output pins.
Signal types
IEEE std_logic_1164
integer, real, character, boolean, etc.
std_logic(bit) : ‘1’, ‘0’, Unknown value, High Impedance, etc
std_logic_vector(bit vector)
for 8bit data type : std_logic_vector(7 downto 0)

Introduction to VHDL 13 / 30
Predefined operators
Integer Operators: Boolean Operators:
+ addition and AND
- Subtraction or OR
* Multiplication nand NAND
/ division nor NOR
mod modulo division xor exclusive OR
rem modulo remainder xnor exclusive nor
Abs absolute value not complementation
** exponentiation & concatenation

Introduction to VHDL 14 / 30
HDL Descriptions
Behavior description
abstraction of working, little regard to implementation, similar to
programming language
Architecture behavior of MUX41 is
Begin
case sel is
when “00” => Z <= i0;
when “01” => Z <= i1;
when “02” => Z <= i2;
when “03” => Z <= i3;
end case;
End process;

Introduction to VHDL 15 / 30
HDL Descriptions
Structural description
Describe consisting modules and interconnections, hierarchical
design D1
I3 Y B D1 Y
I2 Z
architecture structure of MUX41 is D0 D0
component MUX21 S
port (D1, D0, S : in std_logic; D1 A
I1 Y
Y : out std_logic); I0
end component; D0 S
signal A, B : std_logic;
begin sel(0) sel(1)
U0 : MUX21 port map (D0 => I0, D1 => I1, S=>sel(0), Y=>A);
U1 : MUX21 port map (D0 => I2, D1 => I3, S=>sel(0), Y=>B);
U2 : MUX21 port map (D0 => A, D1=>B, S=>sel(1), Y=>Z);
end structure;

Introduction to VHDL 16 / 30
Process statement
Logic circuit description in architecture body

process
concurrent statement
sequential statement
… …
sequential statement
concurrent statement

Consists of concurrent statement and sequential statement

Process contains several sequential statement
Process itself is a sort of concurrent statement
Process have three different state : suspended, active, running

Introduction to VHDL 17 / 30
Process statement
Process states
event selected
suspended active running

process execution complete

Event represented by wait clause or sensitivity list

wait clause
wait on <sig_list>;
wait until <condition>;
wait for <time>;
wait ;
Sensitivity list
[label] : process (sensitivity_list)
begin ~ end process;

Introduction to VHDL 18 / 30
Procedural assignment
Blocking vs. Non-blocking
Blocking assignment(=) : order dependent
Non-blocking assignment(<=) : order independent
always@(rising_edge clk)
Begin
firstReg <= data;
secondReg <= firstReg;
thirdReg <= secondReg;
End
Don’t get confused : <= and =>
<= signal assignment operator
=> not operator, used for port mapping

Introduction to VHDL 19 / 30
Procedural assignment
What’s the difference?
architecture con of drv is architecture seq of drv is
begin begin
A <= B; Process(B, C)

A <= C; begin
A <= B
end con;
A <= C
end process;
end con2;
Multiple driver
Several signal assignment to a single signal driver
Signal driver
A source which determines a value of each signal
A signal is updated by the driver at every source update
std_logic and std_ulogic
std_logic defines resolution function
std_ulogic does not allow the multiple driver

Introduction to VHDL 20 / 30
Delta delays
Delta time is the time between two sequential events.
The time to take from assigning a value till updated
A delta delay can be thought of as an infinitesimal unit of time
“orthogonal” to simulation time.
An infinite # of delta time steps can occur between tags in the current
time T.
“Which delta cycle” is not accessible in the language; “do something
immediately” means “do it during the next cycle, which will be a delta
cycle”

Introduction to VHDL 21 / 30
Delta delays
Delta delays are used to order events.

Introduction to VHDL 22 / 30
Delta delays

Introduction to VHDL 23 / 30
Synthesis of if statements
if without else
infer a latch

if-else implies
multiplexer

If-elseif imply
priority logic

Introduction to VHDL 24 / 30
Introduction to VHDL 25 / 30
Latch
D-latch의 VHDL description

Library IEEE;
Use IEEE.std_logic_1164.all;

Entity Latch is
Port(LE, Din : in std_logic;
Dout : out std_logic);
End Latch;

Architecture Latch_arch of Latch is

Begin
Process (Din, LE)
Begin
If (LE=‘1’) then
Dout <= Din;
End if;
End process;
End Latch_arch;

Introduction to VHDL 26 / 30
D-flip flop
Rising edge에서 trigger 되는 D-flip flop

library IEEE;
use IEEE.std_logic_1164.all;

entity d-ff is
port(clk, d: in std_logic;
q : out std_logic);
end d-ff;

architecture d-ff_arch of d-ff is

begin
process(clk) Rising_edge(clk)
begin
if(clk'event and clk = '1') then
q <= d;
end if;
end if
end process;
end d-ff_arch

Introduction to VHDL 27 / 30
Register
8bit Register

Library IEEE; architecture Reg_arch of Reg is

use IEEE.std_logic_1164.all; begin
process(clk, rst)
begin
entity Reg is
if(rst = '1') then
port(clk : in std_logic;
q <= (others => '0');
rst : in std_logic; elsif(clk'event and clk ='1') then
ld : in std_logic; if(ld = '1') then
d : in std_logic_vector(7 q <= d;
downto 0); end if;
q : out std_logic_vector(7 end if;
downto 0)); end process;
end Reg; end Reg_arch;
Introduction to VHDL 28 / 30
8bit johnson counter
입력
Clock
Reset
Enable
출력
LED를 통한 출력

Library IEEE;
use IEEE.std_logic_1164.all;

entity johnson is
port(
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end johnson;
Introduction to VHDL 29 / 30
8bit johnson shift counter
architecture john_arch of johnson is Clk : 153 (SW_CLK)
signal Q_reg : std_logic_vector(7 downto 0); Rst : 187 (DIP SW 2번)
begin Enable : 188 (DIP SW 1번)
Q <=Q_reg; Q[0] : 161 (LED0)
U0 : process(clk) Q[1] : 160 (LED1)
begin Q[2] : 159 (LED2)
if(clk'event and clk = '1') then Q[3] : 158 (LED3)
if(rst = '1')then Q[4] : 156 (LED4)
Q_reg <= (others => '0'); Q[5] : 144 (LED5)
else Q[6] : 143 (LED6)
if(enable = '1') then Q[7] : 141 (LED7)
Q_reg <= (not q_reg(0)) & Q_reg(7 downto 1);
else
Q_reg <=Q_reg;
end if;
end if;
end if;
end process;
end john_arch;
Introduction to VHDL 30 / 30