Analogue to Digital Conversion

Digital Signal Processing

A digital signal is an approximation of an analog

one
Levels of signal are sampled and converted to a
discrete bit pattern.
Resistor networks can be used to convert digital
signals into analogue voltages
Step (discrete) approximation

stair-step
approximation of
sample original signal

level

more samples give greater accuracy

time
hold time for sample
This Lecture

Methods of analogue to digital conversion

flash
counter ramp
successive approximation
Sample interval and aliasing problems
Sample and hold circuits
The Comparator
Most A-D converters use a comparator as part of the
conversion process
A comparator compares 2 signals A and B
if A > B the comparator output is in one logic state (0, say)
if B > A then it is in the opposite state (1, say)
A comparator can be built using an op amp with no
feedback

analogue +
input

reference -
voltage
 Flash Converter +
G

Uses a reference and a comparator for each 7V

-

of the discrete levels represented in the digital +

F

output 6V -

Number of comparators = number of +

E

quantisation levels 5V -

encoder digital
Not practical for more than 10 bit converters +
D
output

generally fast but expensive 4V

-

+
Converter Comparator Outputs Encoder Output C

input 3V -

range (V) A B C D E F G
<1 0 0 0 0 0 0 0 000 +
B
>1-2 1 0 0 0 0 0 0 001
2V -
>2-3 1 1 0 0 0 0 0 010
>3-4 1 1 1 0 0 0 0 011 +
A
>4-5 1 1 1 1 0 0 0 100
>5-6 1 1 1 1 1 0 0 101 1V
-

>6-7 1 1 1 1 1 1 0 110
input signal
>7 1 1 1 1 1 1 1 111
 Counter-ramp Converter
Comprises a D-A converter, a single comparator, a counter, a clock
and control logic
When a conversion is required
A signal (conversion request) is sent to the converter and the counter is
reset to zero
a clock signal increments the counter until the reference voltage
generated by the D-A converter is greater than
the analogue input
At this point in time the output of analogue input +
the comparator goes to a
logic 1, which notifies the -
control logic the
conversion has finished comparitor
D-A
The value of the counter Converter
is output as the digital
value
Counter clock and
control logic
 Counter-ramp Converter
conversion
request
The time between the start and comparitor
output
end of the conversion is known
as the conversion time d.c input voltage

A drawback of the counter-ramp

converter is the length of time D-A converter
output
required to convert large
voltages
0 1 2 3 4 5 6 6 6 6 6 6 counter output
We must assume the worst case
clock
when calculating conversion
times
Successive Approximation Converter
Counter replaced by a register
Contents of register decided by clock and control logic
When a conversion is required:
contents of register cleared analogue input +
Vin Vc
Vd = 0
-
MSB set to a 1
comparitor
if Vc = 0 then Vd < Vin D-A Vd
=> leave MSB set Converter
if Vc =1 then Vd > Vin
=> clear MSB
4-bit reg clock and
Repeat previous step for other bits b3 b2 b1 b0 control logic
in MSB to LSB order
The successive approximation A-D
converter

Example:
A 4-bit successive approximation A-D converter has a
full-scale input of +15V. Show how the A-D converter
would convert the analogue voltages 10.9V and 3.1V
into their digital equivalents
Total conversion time = n+1 cycles where n = the
number of bits in the code word
ADC Conversion Error

Assume D-A converter output

has stepped up to V1. V2
Because Vi > V1, the output VI
V1
has stayed at a logic 0.
On the next clock pulse the D-
A output rises to V2.
V2 > Vi, comparator output
becomes logic 1 and
conversion is completed.
Maximum possible error = q.
Quantisation
7V 111
6V 110

Output from an A-D converter can 5V 101

4V 100
only be one of a limited number of
3V 011
possible codes 2V 010
Hence quantisation errors will arise. 1V 001

Possible to reduce this error to half by 0V 000

adding q/2 to the output of the D-A 7V

converter 111
6V
110
Equivalent of rounding decimal 5V
101
numbers. 4V
100
3V
011
2V
010
1V
001
0V 000
Quantisation
Quantization errors can be reduced by increasing
the number of bits
Common for A-D converters to have 16 bit or
better resolution
However the accuracy of the reference voltage
must be of the same precision
Example:
Consider a A-D converter where Vref is only accurate to
within 1%
Quantization Noise

Each conversion has an average uncertainty of one-

half of the step size (A / 2N)

This quantization error places an upper limit on the

signal to noise ratio that can be realized.

Maximum (ideal) SNR 6 N + 1.8 decibels (N = # bits)

e.g. 8 bit 49.8 db, 10 bit 61.8 db
Quantization Noise

Some audio examples

In each successive example the noise power is
reduced by a factor of two (3 db reduction), thus
increasing the signal to noise ratio by 3 db each
time.

Example 1 Example 2 Example 3 Example 4

Summary
Device Comment Conversion time
Best Average Worst
Flash fast and expensive 1 1 1

Counter ramp simple but slow 1 2n/2 2n

Sucessive approx widely used n+1 n+1 n+1

One way to reduce quantization errors is to use a larger number

of bits in the code word
absolute accuracy of conversion may not be as good as the
resolution if the error tolerance for reference voltages gets too
large
A multiplexer enables one A-D converter to be switched between
several signal inputs
Multiplexers
The A-D converters described above have all been single-input
devices
It is often necessary to convert several analogue signals to binary
code words
Integrated circuit multiplexers are available which can select one of
its analogue inputs at a time and present it to a single A-D
converter 1
Analogue
inputs 2
3
Selected
4 analogue
output

digital
control switch decoding
lines logic
Conversion of a.c. signals
The A-D converters that we have looked at present no special
problems with d.c.
What about a.c. signals?
Example consider reading room temperature and plotting
against time
Not possible to sample at every instant in time
rate at which we take samples is known as the sampling rate
sampling too fast can be temp
inefficient
A3

A2

A1

time
Conversion of a.c. signals
Sampling too slowly can cause information to be lost

temp

A2

A1

t1 t2 time
Sample Time vs Frequency
Consider what happens when the signal
frequency is higher than the sampling
frequency.
voltage

time

sample frequency is number of samples / second

Conversion of a.c. signals
Effects of under-sampling voltage

possible to interpolate high

frequency components as
low frequency ones
these errors are said to be
caused by aliasing
important to preceed A-D
converter with a low pass time
filter to remove high Sample frequency must be at least twice
frequencies the highest signal frequency (2f is also
known as an anti-aliasing called the Nyquist Frequency).
filter
Example
What is the maximum frequency of input signal
that can be converted by an A-D convertor with a
conversion time of 0.25 mS?

samples per second = 1000 / 0.25 = 40,000

Maximum frequency in input signal has to be

half this or 20kHz.
Sample-and-hold devices
Sampling rule tells us at what rate to make conversions, but there
is still another problem associated with changing signals

voltage

t1 t2 time
Sample-and-hold devices
voltage

t1 t2 time

To remove the problem a sample and hold device which

samples the input and holds this value until the end of the
conversion is often used
switch

storage
capacitor
Sample-and-hold devices
A number of problems exist with the previous sample
and hold circuit
load placed on the input of the circuit by charging the
capacitor during the sample phase
current flowing from the capacitor used in the conversion will
reduce the voltage stored on the capacitor
-
-
+
+
C

sample/hold
control line
 Proportional Signals

Simple Equation Vmax 1..1 = 2n-1

Assume minimum voltage of 0 V.

Vmax = maximum voltage of the
analog signal
a = analog value
n = number of bits for digital
encoding
2n = number of digital codes
M = number of steps, either 2n or 2n 1
d = digital encoding

a / Vmax = d / M 0V 0..0 = 0
 Resolution
Let n = 2
Vmax 3=11

M = 2n 1 r

3 steps on the digital scale 3=11

d0 = 0 = 0b00
2=10
dVmax = 3 = 0b11

M = 2n 2=10

4 steps on the digital scale

1=01
d0 = 0 = 0b00
1=01
dVmax - r = 3 = 0b11 (no dVmax )

r, resolution: smallest analog change

0V 0=00 0=00
resulting from changing one bit
Example using successive approximation

Given an analog input signal whose voltage should

range from 0 to 15 volts, and an 8-bit digital
encoding, calculate the correct encoding for 5 volts.
Then trace the successive-approximation approach
to find the correct encoding.
Assume M = 2n 1
a / Vmax = d / M
5 / 15 = d / (256 - 1)
d = 85 or binary 01010101
Example using successive approximation

Step 1-4: determine bits 0-3

(Vmax Vmin) = 7.5 volts

0 0 0 0 0 0 0 0
Vmax = 7.5 volts.
(7.5 + 0) = 3.75 volts
0 1 0 0 0 0 0 0
Vmin = 3.75 volts.

(7.5 + 3.75) = 5.63 volts 0 1 0 0 0 0 0 0

Vmax = 5.63 volts

(5.63 + 3.75) = 4.69 volts 0 1 0 1 0 0 0 0

Vmin = 4.69 volts.

Embedded Systems Design: A Unified Hardware/Software

Introduction, (c) 2000 Vahid/Givargis
Example using successive approximation

Step 5-8: Determine bits 4-7

(5.63 + 4.69) = 5.16 volts 0 1 0 1 0 0 0 0

Vmax = 5.16 volts.
(5.16 + 4.69) = 4.93 volts 0 1 0 1 0 1 0 0
Vmin = 4.93 volts.

(5.16 + 4.93) = 5.05 volts 0 1 0 1 0 1 0 0

Vmax = 5.05 volts.
(5.05 + 4.93) = 0 1 0 1 0 1 0 1
4.99 volts