LD -2

MULTD -5
DIV 20
ADDD 2
Inteiros - 1

Instruction status: Execution Write Busy Address

Issue
Instruction j k complete Result Load1 Yes 0+R2
LD F0 0 R2 1 3 4 Load2 Yes 0+R3
LD F4 0 R3 2 4
MULTD F0 F0 F4 3
ADDD F2 F0 F2 4
DIVD F6 F2 F4
DADDUI R5 R5 #8
BNEQZ R5 Loop

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
Add1 Yes Addd A(F2) Load1
Add2 No
Add3 No
Mult1 Yes Mult Load1 Load2
Mult2 No
Register result status
Clock: 1 a 4 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Load1 Addd Load2
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result
LD F0 0 R2 1 3 4 Load2 Yes 0+R3
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3
ADDD F2 F0 F2 4
DIVD F6 F2 F4 5
DADDUI R5 R5 #8
BNEQZ R5 Loop

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
Add1 Yes Addd A(F2) Mult
Add2 No
Add3 No
Mult1 Yes Mult M(F0) Load2
Mult2 Yes Div Addd Load2
Register result status
Clock: 5 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Mult Addd Load2 Div
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result Daddui yes R5+8
LD F0 0 R2 1 3 4
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3
ADDD F2 F0 F2 4
DIVD F6 F2 F4 5
DADDUI R5 R5 #8 6 7 8
BNEQZ R5 Loop 7

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
Add1 Yes Addd A(F2) Mult
Add2 No
Add3 No
5_4_3 Mult1 Yes Mult M(F0) M1
Mult2 Yes Div M1 Addd
Register result status
Clock: 6-8 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Mult Addd Div
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result Bneqz yes
LD F0 0 R2 1 3 4
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3 10 11
ADDD F2 F0 F2 4
DIVD F6 F2 F4 5
DADDUI R5 R5 #8 6 7 8
BNEQZ R5 Loop 7 9 10

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
Add1 Yes Addd A(F2) Mult
Add2 No
Add3 No
0 Mult1 Yes Mult M(F0) M1
Mult2 Yes Div M1 Addd
Register result status
Clock: 9-11 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Mult Addd Div
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result
LD F0 0 R2 1 3 4
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3 10 11
ADDD F2 F0 F2 4
DIVD F6 F2 F4 5
DADDUI R5 R5 #8 6 7 8
BNEQZ R5 Loop 7 9 10

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
3 Add1 Yes Addd M2 A(F2)
Add2 No
Add3 No
Mult1 No
Mult2 Yes Div M1 Addd
Register result status
Clock: 12 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Addd Div
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result
LD F0 0 R2 1 3 4
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3 10 11
ADDD F2 F0 F2 4 14 15
DIVD F6 F2 F4 5
DADDUI R5 R5 #8 6 7 8
BNEQZ R5 Loop 7 9 10

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
0 Add1 Yes Addd M2 A(F2)
Add2 No
Add3 No
Mult1 No
Mult2 Yes Div M1 Addd
Register result status
Clock: 13-15 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Addd Div
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result
LD F0 0 R2 1 3 4
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3 10 11
ADDD F2 F0 F2 4 14 15
DIVD F6 F2 F4 5
DADDUI R5 R5 #8 6 7 8
BNEQZ R5 Loop 7 9 10

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
Add1 Yes
Add2 No
Add3 No
Mult1 No
20 Mult2 Yes Div D1 M1
Register result status
Clock: 16 F0 F2 F4 F6 F8 F10 F12 ... F30
FU Div
Instruction status: Execution Write Busy Address
Issue
Instruction j k complete Result
LD F0 0 R2 1 3 4
LD F4 0 R3 2 4 5
MULTD F0 F0 F4 3 10 11
ADDD F2 F0 F2 4 14 15
DIVD F6 F2 F4 5 35 36
DADDUI R5 R5 #8 6 7 8
BNEQZ R5 Loop 7 9 10

Reservation Stations: S1 S2 FU for j FU for k

Time Name Busy Op Vj Vk Qj Qk
0 Add1 No
Add2 No
Add3 No
0 Mult1 No
Mult2 No
Register result status
Clock: 35-36 F0 F2 F4 F6 F8 F10 F12 ... F30
FU