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Xilinx Manual:

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the
developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a
design's reaction to different stimuli, and configure the target device with the programmer.

In our Lab, the scope is limited to design and analyze the design using test benches & simulation.

The following is the step by step procedure to design in the Xilinx ISE:

PROCEDURAL STEPS:

The following procedure will guide you to develop a Xilinx ISE project.

a. Create a New Project:

The first step of any design in ISE is to create a new ISE project. In each ISE project, the target FPGA device
needs to be defined. Although this laboratory work does not require hardware, you are suggested to create a new
ISE project which targets at the FPGA device on the Spartan-3 Startup Kit by following the steps below:

1. Open the Project Navigator of Xilinx software.

2. Select File New Project The New Project Wizard appears.

3. Type Logic gates in the Project Name field.

4. Enter or browse to a location of your choice for the new project. A Logic gates subdirectory is created
automatically.
5. Verify that HDL is selected from the Top-Level Source Type list.

6. Click Next to move to the device properties page.

7. Fill in the properties in the table as shown below:

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Fig 1.2 (a): Device Properties

8. Say Next for 3 times, then click on Finish. When you find new project result, project summary, click finish.

9. Click Next to proceed to the Create New Source window in the New Project Wizard. Then proceed to section

b. Create a new HDL Source:

In this section, you will create the top-level HDL file for your design.

Create a VHDL source file for the project

1. Click the New Source button in the New Project Wizard.

2. Select Verilog Module as the source type.

3. Type in the file name.

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Fig 1.2 (b): New Source Wizard

4. Verify that the Add to project checkbox is selected.

5. Click Next.

6. Declare the ports for the lgates design that you are going to make by filling in the port information as below:

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Fig 1.2 (c): Port Information

7. Write Verilog code in HDL edition and save.

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Fig 1.2 (d): VHDL Code in Xilinx

c. Check Syntax:

1. In process window go to sources for window and select behavioral simulation.

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Fig 1.2 (e): VHDL Code check syntax

d. To Create Test Bench Wave form:


1. For this right click on create a new source in process window and select.

Fig 1.2(f): Different File name

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Fig 1.2 (g): Test bench waveform

2. Select the desired parameters for simulating your design and click ok.

3. Assign all the signals to test bench wave form and save the file.

e. Simulation Process:

1. In source window from the dropdown menu select behavioral simulation to see the created
test bench file.
2. Select the test bench file from the source process window, click Xilinx ISE simulator. Now
double click simulate behavioral module.

Experiment 1:
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LOGIC GATES

Aim: To Design Logic Gates using VHDL and simulate the same using Xilinx ISE Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

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Theory:

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT, NAND,
NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth tables.

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AND GATE:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used
to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB.

OR GATE:

The OR gate is an electronic circuit that give s a high output (1) if one or more of its inputs are high. A plus (+)
is used to show the OR operation.

NOT GATE:

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also
known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as
A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND
logic gate can be configured to produce a NOT gate. It can be done using NOR logic gates in the same way.

NAND GATE: This is a NOT - AND gate which is equal to an AND gate followed by a NOT gate. The outputs
of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the
output. The small circle represents inversion.

NOR GATE: This is a NOT - OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output.
The small circle represents inversion.

EXOR GATE: The 'Exclusive-OR' gate is a circuit which will give a high output if

either, but not both, of its two inputs are high.An encircled plus sign is used to show the EOR operation.

EXNOR GATE: The 'Exclusive-NOR'gate circuit does the opposite to the EOR gate. It will give a low output if
either, but not both , of its two inputs are high. The symbol is an EXOR gate with a small circle on the output.

The small circle represents inversion.

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The NAND and NOR gates are called universal functions since with either one the AND and OR functions and
NOT can be generated.

Note: A function in sum of products form can be implemented using NAND gates by replacing all AND and OR
gates by NAND gates. A neither function in product of sums form can be implemented using NOR gates by
replacing all AND and OR gates by NOR gates.

VHDL Code:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity logic gates is
Port (A: in STD_LOGIC;
B: in STD_LOGIC;
AND1: out STD_LOGIC;
OR1: out STD_LOGIC;
NOT1: out STD_LOGIC;
XOR1: out STD_LOGIC;
NAND1: out STD_LOGIC;
NOR1: out STD_LOGIC;
XNOR1: out STD_LOGIC);
End logic gates;
Architecture Behavioral of logic gates is
Begin
AND1<=A AND B;
OR1<=A OR B;
NOT1<=NOT A;
XOR1<=A XOR B;
NAND1<= A NAND B;
NOR1<=A NOR B;
XNOR1<=A XNOR B;
end Behavioral;
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Simulation Results:

Result: Logic Gates are designed using VHDL and simulated the same using Xilinx ISE Simulator.

Viva Questions:
1. What are universal gates?
2. What are special purpose gates?
3. Design XOR gate using NAND gates?
4. How many NOR gates required to design NAND gate?

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Experiment: 2

2-TO-4 DECODER

Aim: To Design 2-To-4 decoder using VHDL and simulate the same using Xilinx ISE Simulator.

Tools Required: 1.PC


2.Xilinx ISE

Schematic Diagram:

Truth table:

INPUT OUTPUTS

A B Y[3] Y[2] Y[1] Y[0]

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

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Block diagram:

Fig 2.1 : Block Diagram of 2 to 4 decoder

Theory:

DECODERS : A decoder is a combinational circuit that converts coded inputs to another coded outputs. The
famous examples of decoders are binary n-to-2n decoders and seven-segment decoders. A binary decoder has n
inputs and a maximum of 2n outputs. As we know, an n-bit binary number provides 2n minterms or maxterms.
This type of decoder produces one of the 2n minterms or maxterms at the outputs based on the input
combinations. Lets take the 2-to-4 decoder as an example, the block diagram and the truth table of this decoder
is shown in Figure 2.1

From the truth table, you can observe the basic operation of n-to-2n decoders, there is only one active output
( minterm ) for each input combination. The Boolean expression of the output signals are : D0 = E x' y', D1= E
x' y, D2 = E x y' and D3= E x y Now, the logic diagram for the 2-to-4 decoder can obtained as shown in Figure
2.2.

Fig2.2 : Internal Circuit Diagram of 2 to 4 decoder


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In the same way, we can obtained the logic diagram for any n-to-2n type decoder. The commercially available
decoders are normally built using NAND gates instead of using AND gates because they are easy and less
expensive to build. An example of a commercial n-to-2n line decoder is the 74139 chip.

This chip has two 2-to-4 decoders with active low enable for each , They constructed using the NAND
gates (see its pinout diagram and Function Table ) Because any Boolean function can be expressed as a sum of
products (minterms) or a product of sums (maxterms), we can use a decoder to implement any Boolean
function.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
process(En,I)
begin
if En='0' then Y<="0000";
else
case I is
when "00" =>Y[0]<="0001";
when "01" =>Y[1]<="0010";
when "10" =>Y[2]<="0100";
when "11" =>Y[3]<="1000";
when others =>Y<="ZZZZ";
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end case;
end if;
end process;
end Behavioral;

Simulation Results:

Result: 2-To-4 Decoder is designed using VHDL and simulated the same using Xilinx ISE Simulator

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Viva Questions:
1.what is a decoder?

2.Define mean term and max term.

3. Mention the differences between combinational and sequential circuits.

4. What is pos and sop?

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Experiment: 3(a)

8-TO-3 ENCODER WITHOUT PRIORITY

Aim: To Design 8-To-3 Encoder without Priority using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram and Truth Table :

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Theory:
ENCODER :
An encoder is a device, circuit, transducer, software program, algorithm or person that converts information
from one format or code to another. The purpose of encoder is standardization, speed, secrecy, security, or
saving space by shrinking size. Encoders are combinational logic circuits and they are exactly opposite of
decoders. They accept one or more inputs and generate a multibit output code. Encoders perform exactly
reverse operation than decoder. An encoder has M input and N output lines. Out of M input lines only one is
activated at a time and produces equivalent code on output N lines. If a device output code has fewer bits than
the input code has, the device is usually called an encoder. Octal to binary encoder Octal-to-Binary take 8 inputs
and provides 3 outputs, thus doing the opposite of what the 3-to-8 decoder does. At any one time, only one input
line has a value of 1. The figure below shows the truth table of an Octal-to-binary encoder.

Fig 3.1: Truth Table of octal to binary encoder (Without Priority)

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:

Y0 = I1 + I3 + I5 + I7

Y1= I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 +I7

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VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_without_priority is
Port ( En : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (7 downto 0);
Q : out STD_LOGIC_VECTOR (2 downto 0));
end encoder_without_priority;
architecture Behavioral of encoder_without_priority is
begin
process(En,D)
begin
if En='0' then Y<="XXX";
else
case D is
when "00000001"=>Q<="000";
when "00000010"=>Q<="001";
when "00000100"=>Q<="010";
when "00001000"=>Q<="011";
when "00010000"=>Q<="100";
when "00100000"=>Q<="101";
when "01000000"=>Q<="110";
when "10000000"=>Q<="111";

when others=>Q<="ZZZ";
end case;
end if;
end process;
end Behavioral;

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Simulation Results:

Result: 8-To-3 Encoder without Priority is designed using VHDL and simulated the same using Xilinx ISE
Simulator

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Experiment 3(a)

8-TO-3 ENCODER WITH PRIORITY

Aim: To Design 8-To-3 Encoder with Priority using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Theory:

PRIORITY ENCODER:

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number
of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero
of the most significant input bit. They are often used to control interrupt requests by acting on the highest
priority request. It includes priority function. If 2 or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence. Internal hardware will check this condition and priority is set.
Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit priority
encoder which has eight active LOW (logic "0") inputs and provides a 3-bit code of the highest ranked input at
its output. Priority encoders output the highest order input first for example, if input lines "D2", "D3" and "D5"
are applied simultaneously the output code would be for input "D5" ("101") as this has the highest order out of
the 3 inputs. Once input "D5" had been removed the next highest output code would be for input "D3" ("011"),
and so on.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Encoder_with_priority is
Port ( En : in STD_LOGIC;
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D : in STD_LOGIC_VECTOR (7 downto 0);


Q : out STD_LOGIC_VECTOR (2 downto 0));
end Encoder_with_priority;
architecture Behavioral of Encoder_with_priority is
begin
process(En,D)
begin
if En='0' then Y<="XXX";
elsif D(7)='1' then Q<="111";
elsif D(6)='1' then Q<="110";
elsif D(5)='1' then Q<="101";
elsif D(4)='1' then Q<="100";
elsif D(3)='1' then Q<="011";
elsif D(2)='1' then Q<="010";
elsif D(1)='1' then Q<="001";
elseif D(0)=1 then Q<="000";
else Q<=ZZZ;
end if;
end process;
end Behavioral;

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Simulation Results:

Result: 8-To-3 Encoder with Priority is designed using VHDL and simulated the same using Xilinx ISE
Simulator
Viva Questions:

1. Which gates are used to 8X3 encoder?


2. What are the uses of encoder?
3. What is the difference between encoder with priority and with priority?
4. Which IC is used for encoder?
5. Which Of the following encode used for many code conversions?
(a) Octal to binary (b) Decimal to BCD (C) Hex to binary
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Experiment: 4

8-TO-1 MULTIPLEXER

Aim: To Design 8-To-1 Multiplexer using VHDL and simulate the same using Xilinx ISE Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

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Truth Table:

Internal Circuit Diagram:

Fig4.2 : Internal Circuit Diagram of 8 to 1 Multiplexer

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Fig4.3 : Block Diagram of 8 to 1 Multiplexer

Theory:

MULTIPLEXER:

In electronics, a multiplexer or mux is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines,which are used to
select which input line to send to the output. An electronic multiplexer can be considered as a multiple-input,
single-output switch i.e. digitally controlled multi-position switch. The digital code applied at the select inputs
determines which data inputs will be switched to output.

A common example of multiplexing or sharing occurs when several peripheral devices share a single
transmission line or bus to communicate with computer. Each device in succession is allocated a brief time to
send and receive data. At any given time, one and only one device is using the line. This is an example of time
multiplexing since each device is given a specific time interval to use the line.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Mux_8_1 is
Port ( En_L : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (2 downto 0);
D : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC);
end Mux_8_1;
architecture Behavioral of Mux_8_1 is
begin
process(S,D,En_L)
begin
if En_L='1' then Y<='0';
else
case S is
when "000"=>Y<=I(0);
when "001"=>Y<=I(1);
when "010"=>Y<=I(2);
when "011"=>Y<=I(3);
when "100"=>Y<=I(4);
when "101"=>Y<=I(5);
when "110"=>Y<=I(6);
when "111"=>Y<=I(7);
when others=>Y<='Z';
end case;
end if;
end process;
end Behavioral;

Simulation Results:

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Result: 8-To-1 Multiplexer is designed using VHDL and simulated the same using Xilinx ISE Simulator.

Viva Questions:

1. Why MUX is called universal element?

2. To implement 64X1 MUX how many number of 2X1 MUX required?

3. To implement 2nX1 MUX how many number of 2X1 MUX required?

4. To implement NOT gate, how many number of 2X1 MUX required?

5. To implement half adder how many number of 2X1 MUX required?

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Experiment: 5
BINARY-TO-GRAY CODE CONVERTER

Aim: To Design Binary-To-Gray Code Converter using VHDL and simulate the same using Xilinx ISE
Simulator

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

Truth Table:

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Internal Circuit Diagram:

Fig5.1 : RTL Diagram of 4 Bit Binary to Gray conversion

Fig5.2: Internal circuit diagram for 4 Bit Binary to Gray conversion

Theory:

4 Bit Binary to Gray conversion:

The reflected binary code, also known as Gray code/Cyclic Code/Unique Distance Code after Frank Gray, is
a binary numeral system where two successive values differ in only one bit. It is a nonweighted code.

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The reflected binary code was originally designed to prevent spurious output from electromechanical switches.
Today, Gray codes are widely used to facilitate error correction in digital communications such as digital
terrestrial television and some cable TV systems.

Many devices indicate position by closing and opening switches. If that device uses natural binary codes, these
two positions would be right next to each other:

...

011

100

...

The problem with natural binary codes is that, with real (mechanical) switches, it is very unlikely that switches
will change states exactly in synchrony. In the transition between the two states shown above, all three switches
change state. In the brief period while all are changing, the switches will read some spurious position. Even
without key bounce, the transition might look like 011 001 101 100. When the switches appear to be in
position 001, the observer cannot tell if that is the"Real" position 001, or a transitional state between two other
positions. If the output feeds into a Sequential system (possibly via combinational logic) then the sequential
system may store a false value. The reflected binary code solves this problem by changing only one switch at a
time, so there is never any ambiguity of position.

Dec Binary Gray

0 000 000

1 001 001

2 010 011

3 011 010

4 100 110

5 101 111

6 110 101

7 111 100

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Notice that state 7 can roll over to state 0 with only one switch change. This is called the "cyclic"

property of a Gray code. In the standard Gray coding the least significant bit follows a repetitive pattern

of 2 on, 2 off ( 11001100 ); the next digit a pattern of 4 on, 4 off; and so forth.

More formally, a Gray code is a code assigning to each of a contiguous set of integers, or to

each member of a circular list, a word of symbols such that each two adjacent code words differ by one

symbol. These codes are also known as single-distance codes, reflecting the Hamming distance of 1

between adjacent codes. There can be more than one Gray code for a given word length, but the term

was first applied to a particular binary code for the non-negative integers, the binary-reflected Gray

code, or BRGC, the three-bit version of which is shown above.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Binary_to_gray is
Port ( B : in STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC_VECTOR (3 downto 0));
end Binary_to_gray;
architecture Behavioral of Binary_to_gray is
begin
G(3)<=B(3);
G(2)<=B(3) XOR B(2);
G(1)<=B(2) XOR B(1);
G(0)<=B(1) XOR B(0);
end Behavioral;

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Simulation Results:

Result: Binary-To-Gray Code Converter is designed using VHDL and simulated the same using Xilinx ISE
Simulator.

Viva Questions:

1. Why gray code is called cyclic code or unique distance code?

2. Give application of gray code.

3. Convert 1010 binary code to gray code.

4. Convert 1110 gray code to binary code.

5. Solve the Boolean expression AB+A bar B bar


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Experiment: 6
4-BIT COMPARATOR

Aim: To Design 4-Bit Comparator using VHDL and simulate the same using Xilinx ISE Simulator

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram and Truth Table:

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Internal Circuit Diagram:

Fig : RTL Diagram For 2 Bit Comparator Truth Table


Theory:

2 BIT Binary Comparator:

A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as
input in binary form and determines whether one number is greater than, less than or equal to the other number.
Comparators are used in a central processing units (CPU) and microcontrollers Examples of digital comparator
include the CMOS 4063 and 4585 and the TTL 7485 and 74682-'89.

The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers have analog
comparators on some of their inputs that can be read or trigger an interrupt.

The purpose of a two-bit binary comparator is quite simple. It determines whether one 2-bit input number is
larger than, equal to, or less than the other. The circuitry accomplishes this through several logic gates that
operate on the principles of Boolean algebra. Since the circuitry is based upon an algebraic system it can not
only be made simpler through mathematical manipulation, but there is also no absolute solution to the given
task.

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DESIGN:

The first step in the creation of the comparator circuit is the generation of a truth table that lists the

input variables, their possible values, and the resulting outputs for each of those values. The truth table

used for this experiment is shown

Fig : 2 Bit Comparator Truth Table

From the truth table, canonical minterm equations were generated for each output variable. These equations
were then simplified to represent as few logic gates as possible The final equations were then used to sketch a
circuit schematic for each variable. Once eachvariable had a schematic, common values were found and the
three schematics were combined to createa single circuit diagram The three minterm equations were able to be
simplified down to

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The other problem with the circuit design is its inability to interpret signed numbers. For example, when A is 10
and B is 00, the circuit shows that A is greater than B. If A is interpreted as a signednumber its value is negative
two. In this case, the comparator should show L as a high as A would be less than B.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
AEQB : out STD_LOGIC;
AGTB : out STD_LOGIC;
ALTB : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
process(A,B)
begin
if A=B then AEQB<='1';AGTB<='0';ALTB<='0';
elsif A>B then AEQB<='0';AGTB<='1';ALTB<='0';
else AEQB<='0';AGTB<='0';ALTB<='1';
end if;
end process;
end Behavioral;

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Simulation Results:

Result: 4-Bit Comparator Converter is designed using VHDL and simulated the same using Xilinx ISE

Viva Questions:

1. Explain what is the differnce between decoder and demultiplexer?

2. Which gates are used to implement Demultiplexier?

3. To Design 1X8 De-Mux. How many number of 1X2 De-Mux required.

4. Write the output expression for 2-bit comparator?

5. What are the applications of comparator?

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Experiment7(a)
FULL ADDER USING DATAFLOW STYLE

Aim: To Design Full Adder Using Dataflow Style using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

Truth Table:

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Internal Circuit Diagram:

Fig7.1 : Internal Circuit Diagram of Full Adder

Fig7.2: Internal Circuit Diagram of Full Adder

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Theory:

FULL ADDER:

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds
three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from
the next less significant stage. The full-adder is usually a component in a cascade of adders, which add 8, 16,
32, etc. binary numbers. The circuit produces a two-bit output sum typically represented by the signals Cout and
S.

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder,
connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two
carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Cout could be made the
three-bit majority function of A, B, and Ci.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Full_Adder_Dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder_Dataflow;
architecture Dataflow of Full_Adder_Dataflow is
signal X: STD_LOGIC;
begin
X<= (A xor B) and Cin;

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Sum<= A xor B xor Cin;


Cout<=X or (A and B);
end Dataflow;

Simulation Results:

Result: Full Adder Using Dataflow Style is designed using VHDL and simulated the same using Xilinx ISE
Simulator

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Experiment7(b)

FULL ADDER USING BEHAVIORAL STYLE

Aim: To Design Full Adder Using Behavioral Style using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

Truth Table:

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Internal Circuit Diagram:

Fig7.3 : Internal Circuit Diagram of Full Adder

Fig7.4 : Internal Circuit Diagram of Full Adder

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VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Full_Adder_Behavioral is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder_Behavioral;
architecture Behavioral of Full_Adder_Behavioral is
signal P:Std_logic_vector(2 downto 0);
begin
P<=A&B&Cin;
process(A,B,p,Cin)
begin
case p is
when "000"=>Sum<='0';Cout<='0';
when "001"=>Sum<='1';Cout<='0';
when "010"=>Sum<='1';Cout<='0';
when "011"=>Sum<='0';Cout<='1';
when "100"=>Sum<='1';Cout<='0';
when "101"=>Sum<='0';Cout<='1';
when "110"=>Sum<='0';Cout<='1';
when "111"=>Sum<='1';Cout<='1';
when others=>Sum<='Z';Cout<='Z';
end case;
end process;
end Behavioral;

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Simulation Results:

Result: Full Adder Using Behavioral Style is designed using VHDL and simulated the same using Xilinx ISE
Simulator

Viva Questions:
1. How many number of NAND and NOR gates are required to implement Full adder?

2. Write the other expressions for Sum and Carry for full adder and full subtractor?

3. Design Full adder using 3X8 Decoder.

4. What are the difference between combinational circuits and sequential circuits?

5. What is the main difference between Half adder and Full adder?
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Experiment: 7 (c)

FULL ADDERS USING STRUCTURAL STYLE

Aim: To Design Full Adder Using Structural Style using VHDL and simulate the same using Xilinx ISE
Simulator

Tools Required: 1.PC


2. Xilinx ISE

Internal Circuit Diagram:

Fig7.5: Internal Circuit Diagram of Full Adder

VHDL Code:

-------VHDL Code for Xor Gate----


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;
architecture Behavioral of or_gate is
begin
c<=a or b;
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end Behavioral;
-------VHDL Code for and Gate----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_g is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_g:
architecture Behavioral of and_g is
begin

c<=a and b;
end Behavioral;
-------VHDL Code for Or Gate----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_g is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_g;

architecture Behavioral of xor_g is


begin
c<=a xor b;
end Behavioral;
-------VHDL Code for Full Adder----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder_structural is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;

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Cin : in STD_LOGIC;
SUM : out STD_LOGIC;
Cout : out STD_LOGIC);
end fulladder_structural;
architecture Behavioral of fulladder_structural is
component or_gate is
port(a,b:in std_logic;
c:out std_logic);
end component;
component and_g is
port(a,b:in std_logic;
c:out std_logic);
end component;
component xor_g is
port(a,b:in std_logic;
c:out std_logic);
end component;
signal y1,y2,y3:std_logic;
begin
X1:xor_g port map (A, B, y1);
a1:and_g port map (A, B, y2);
X2:xor_g port map (y1, Cin, sum);
a2:and_g port map (y1, Cin, y3);
r1:or_gate port map (y2, y3, Cout);
end Behavioral;

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Simulation Results:

Result: Full Adder Using Structural Style is designed using VHDL and simulated the same using Xilinx ISE
Simulator.

Viva Questions:
1. How many number of NAND and NOR gates are required to implement Full adder?

2. Write the other expressions for Sum and Carry for full adder and full subtractor?

3. Design Full adder using 3X8 Decoder.

4. What are the difference between combinational circuits and sequential circuits?

5. What is the main difference between Half adder and Full adder?

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Experiment:8(a)

D FLIP FLOP WITH ASYNCHRONOUS RESET

Aim: To Design D Flip Flop with Asynchronous Reset using VHDL and simulate the same using Xilinx
ISE Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Internal Block Diagram:

Theory:

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state

information. The circuit can be made to change state by signals applied to one or more control inputs and will

have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a

fundamental building block of digital electronics systems used in computers, communications, and many other

types of systems.
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Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state,

and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state

depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be

used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple

ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices

are described as flip-flops.

FLIP-FLOP TYPES

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"[16]), T ("toggle"), and
JK types are the common

ones.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF_Asyn is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF_Asyn;
architecture Behavioral of DFF_Asyn is
begin
process(clk,D,Rst)
begin
if Rst='1' then Q<='0';
elsif clk'event and clk='1' then
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Q<=D;
end if;
end process;
end Behavioral;

Simulation Results:

RESULT: D Flip Flop with Asynchronous Reset is designed using VHDL and simulated the same using
Xilinx ISE Simulator

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Experiment.8(b)

D FLIP FLOP WITH SYNCHRONOUS RESET

Aim: To Design D Flip Flop with Synchronous Reset using VHDL and simulate the same using Xilinx
ISE Simulator

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

Truth Table:

Internal Circuit Diagram:


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Fig8.2: D Flip Flop with Synchronous Reset

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF_Syn is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF_Syn;
architecture Behavioral of DFF_Syn is
begin
process
begin
wait until clkevent and clk=1;
if Rst='1' then Q<='0';
elsif clk'event and clk='1' then
Q<=D;
end if;
end process;
end Behavioral;

Simulation Results:
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Result: D Flip Flop with Synchronous Reset is designed using VHDL and simulated the same using
Xilinx ISE Simulator

Experiment.:8(c)
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T FLIP FLOP WITH ASYNCHRONOUS RESET

Aim: To Design T Flip Flop with Asynchronous Reset using VHDL and simulate the same using Xilinx
ISE Simulator

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram with Truth table:

Inputs Outputs Comments

E T Qn Qn+1

1 0 Q Q No change

1 1 Q Q Toggle

VHDL Code:

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library ieee;

use ieee.std_logic_1164.all;

entity tff_async_reset is

port ( data :in std_logic; clk :in std_logic; reset :in std_logic; q :out std_logic -- Q output );

end entity;

architecture rtl of tff_async_reset is

signal t :std_logic;

begin

process (clk, reset) begin

if (reset = '0') then

t <= '0';

elsif (rising_edge(clk)) then

t <= not t;

end if;

end process;

q <= t;

end architecture;

Simulation Results:
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Result: T Flip Flop with Asynchronous Reset is designed using VHDL and simulated the same using
Xilinx ISE Simulator.

Experiment:8(d)

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T FLIP FLOP WITH SYNCHRONOUS RESET

Aim: To Design T Flip Flop with Synchronous Reset using VHDL and simulate the same using Xilinx ISE
Simulator

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

Truth table:

Inputs Outputs Comments

E T Qn Qn+1

1 0 Q Q No change

1 1 Q Q Toggle

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VHDL Code:
library ieee;
use ieee.std_logic_1164.all;

entity tff_sync_reset is
port ( data :in std_logic ; clk :in std_logic; reset :in std_logic; q :out std_logic -- Q output );
end entity;
architecture rtl of tff_sync_reset is
signal t :std_logic;
begin
process (clk) begin
if (rising_edge(clk)) then
if (reset = '0') then
t <= '0';
else
t <= not t;
end if;
end if;
end process;
q <= t;
end architecture;

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Simulation Results:

Result: T Flip Flop with Synchronous Reset is designed using VHDL and simulated the same using Xilinx
ISE Simulator

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Experiment:8(e)

JK FLIP FLOP WITH ASYNCHRONOUS RESET

Aim: To Design JK Flip flop with Asynchronous Reset using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram and Truth table:

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Truth Table:

VHDL Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JKFF3 is
Port ( CLOCK : in std_logic;
J : in std_logic;
K : in std_logic;
RESET : in std_logic;
Q : out std_logic;
QBAR : out std_logic);
end JKFF3;
architecture Behavioral of JKFF3 is
signal state: std_logic;
signal input: std_logic_vector (1 downto 0);
begin
input <= J & K;
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p: process(CLOCK,RESET) is
begin
if RESET = '1' then
state <= '0';
elsif (rising_edge(CLOCK)) then
case (input) is
when"11" =>
state <= not state;
when"10" =>
state <= '1';
when"01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
end Behavioral;

Simulation Results

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Experiment:8(f)

JK FLIP FLOP WITH SYNCHRONOUS RESET

Aim: To Design JK Flip flop with Synchronous Reset using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram and Truth table:

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VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF_VHDL is
port( J,K: in std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end JK_FF_VHDL;

architecture Behavioral of JK_FF_VHDL is


signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
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elsif (J='1' and K='1') then


temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;

Simulation Results

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Experiment:8(g)

SR FLIP FLOP WITH AYNCHRONOUS RESET

Aim: To Design SR Flip flop with Asynchronous Reset using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram and Truth table:

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VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sr_flip_flop is
port(
s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC
);
end sr_flip_flop;
architecture sr_flip_flop_arc of sr_flip_flop is
begin
srff : process (s,r,clk,reset) is
begin
if (reset='1') then
q <= '0';
qb <= '1';
elsif (rising_edge (clk)) then
if (s/=r) then
q <= s;
qb <= r;
elsif (s='1' and r='1') then
q <= 'Z';
qb <= 'Z';
end if;
end if;
end process srff;
end sr_flip_flop_arc;

Simulation Results:

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Experiment:8(h)

SR FLIP FLOP WITH SYNCHRONOUS RESET

Aim: To Design SR Flip flop with Synchronous Reset using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram and Truth table:

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VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sr_flip_flop is
port(
s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC
);
end sr_flip_flop;
architecture sr_flip_flop_arc of sr_flip_flop is
begin
srff : process (s,r,clk,reset) is
begin
if (reset='1') then
q <= '0';
qb <= '1';
elsif (rising_edge (clk)) then
if (s/=r) then
q <= s;
qb <= r;
elsif (s='1' and r='1') then
q <= 'Z';
qb <= 'Z';
end if;
end if;
end process srff;
end sr_flip_flop_arc;

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Simulation Results:

Results: Different Types of Flip Flops designed using VHDL and simulated the same using Xilinx ISE
Simulator.

Viva Questions:

1. What is a Flip Flop?


2. What are the types of Flip Flops?
3. What are advantages of T Flip Flop.
4. Write applications of Flip Flops.
5. Draw the Schematic diagrams of Flip Flops.

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Experiment:9(A)

BCD COUNTER WITH ASYNCHRONOUS RESET

Aim: To Design BCD Counter with Asynchronous Reset using VHDL and simulate the same using Xilinx
ISE Simulator

Tools Required: 1.PC


2. Xilinx ISE

Theory:
COUNTERS : Counters are sequential circuits that cycle through some states. They can be implemented using
flip-flops.

Implementation is simple using T flipflops (with toggle output) or with any other flip-flops that can be
connected to give the required function.

Counters are available in two categories Ripple counters (Asynchronous) and Synchronous.

Ripple counters (Asynchronous)

The flip-flop output transition serves as a source for triggering other flip-flops i.e the C input of some or all
flip-flops are triggered NOT by the common clock pulses.

Eg:- Binary ripple counters,BCD ripple counters

Synchronous counters

The C inputs of all flip-flops receive the common clock pulses E.g.:-Binary counter Up-down Binary counter
BCD Binary counter Ring counter Johnson counter.

BCD RIPPLE COUNTER, DECADE COUNTER :

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This counter counts upwards on each negative edge of the input clock signal starting from "0000" until it
reaches an output "1001. Both outputs Q A and Q D are now equal to logic "1" and the output from the NAND
gate changes state from logic "1" to a logic "0" level when the clock goes to level one and whose output is also
connected to the CLEAR (CLR) inputs of all the J-K Flip-flops.

BCD is called decade counter (0-9). To count from 0-99 2-decade counters are needed, and to count up to 999
3-decade counters are need.

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Schematic Diagram:

Truth table:

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VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_Counter_Asyn is
Port ( Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR (3 downto 0));
end BCD_Counter_Asyn;
architecture Behavioral of BCD_Counter_Asyn is
begin
process(Rst,Clk,Q)
begin
if Rst='1' then Q<="0000";
elsif Clk'event and clk='1' then
Q<=Q+1;
if Q="1111" then Q<="0000";
end if;
end if;
end process;
end Behavioral;

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Simulation Results:

Result: BCD Counter with Asynchronous Reset is designed using VHDL and simulated the same using Xilinx
ISE Simulator

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Experiment:9(b)

BCD COUNTER WITH SYNCHRONOUS RESET

Aim: To Design BCD Counter with Synchronous Reset using VHDL and simulate the same using Xilinx ISE
Simulator.

Tools Required: 1.PC


2. Xilinx ISE

Schematic Diagram:

Truth table:

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Theory:
COUNTERS : Counters are sequential circuits that cycle through some states. They can be implemented using
flip-flops.
Implementation is simple using T flipflops (with toggle output) or with any other flip-flops that can be
connected to give the required function.
COUNTERS are available in two categories Ripple counters (Asynchronous) and Synchronous.
Ripple counters (Asynchronous)
The flip-flop output transition serves as a source for triggering other flip-flops i.e the C input of some or all flip-
flops are triggered NOT by the common clock pulses .
Eg:- Binary ripple counters, BCD ripple counters
Synchronous counters
The C inputs of all flip-flops receive the common clock pulses E.g.:-Binary counter Up-down Binary counter
BCD Binary counter Ring counter Johnson counter

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_Counter_Syn is
Port ( Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
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Q : Buffer STD_LOGIC_VECTOR (3 downto 0));


end BCD_Counter_Syn;
architecture Behavioral of BCD_Counter_Syn is
begin
process
begin
wait until clkevent and clk=1;;
if Rst='1' then Q<="0000";
elsif Clk'event and clk='1' then
Q<=Q+1;
if Q="1111" then Q<="0000";
end if;
end if;
end process;
end Behavioral;

Simulation Results:

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Result: BCD Counter with Synchronous Reset is designed using VHDL and simulated the same using Xilinx
ISE Simulator

Viva Questions:
1. Expand BCD.
2. What are the types counters
3. Asynchronous counter otherwise know as
4. What is difference between synchronous and asynchronous BCD counter

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Experiment:10

FINITE STATE MACHINE DESIGN

Aim: To Design Mealy Finite State Machine using VHDL and simulate the same using Xilinx ISE Simulator.

Tools Required: 1.PC


2. Xilinx ISE

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State Transition diagram and State Table

Theory:
In the theory of computation, a Mealy machine is a finite state transducer that generates an output based on its
current state and input. This means that the state diagram will include both an input and output signal for each
transition edge. In contrast, the output of a Moore finite state machine depends only on the machine's current
state; transitions are not directly dependent upon input. The use of a Mealy FSM leads often to a reduction of
the number of states. However, for each Mealy machine there is an equivalent Moore machine.

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VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEALY is
port (X,CLOCK: in BIT;Z:out BIT);
end;
architechture BEHAVIOUR OF MEALY is
type STATE_TYPE is (S0,S1,S2,S3);
signal CURRENT_STATE,NEXT_STATE: STATE_TYPE;
begin
Process to hold combinational logic.
COMBIN:process ( CURRENT_STATE,X)
Begin
Case CURRENT_STATE is
When S0=>
If X=0; then Z<=0;
NEXT_STATE<=S0;
Else

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Z<=1;
NEXT_STATE<=S2;
End if ;
When S1=>
If X=0; then Z<=0 ;
NEXt_STATE<=S0;
Else Z<=0;
NEXT_STATE<=S2
end if;
when S2=>
if X=0 then Z<=1;
NEXT_STATE<=S2;
Else
Z<=0;
NEXT_STATE<=S3;
End if;
When S3=>
If X=0 then Z<=0;
NEXT_STATE<=S3;
Else
Z<=1;
NEXT_STATE<=S1;
End if ;
End case;
End process;
Process to hold synchronous elements ( flip flops)
SYNCH: process
Begin
Wait until CLOCKevent and CLOCK =1;

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CURRENT_STATE<=NEXT_STATE;
End process;
End behavior;

Results: Finite State Machine is designed using VHDL and simulated the same using Xilinx ISE Simulator

Viva Questions:

1. What is Finite state machine


2. What are the types of Finite state machines?
3. What is the difference between mealy and moore state machine.
4. Advantages of moore state machine.

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