Introduction

There are two objectives in this laboratory. The first objective is to design and build a 16-bit
adder module using fundamental NMOS and PMOS devices in Verilog. The second objective in
this laboratory is to design and build a 3-bit comparator using these same NMOS and PMOS
devices in Verilog.

Design and Implementation

The 16-bit Adder

There are several levels of abstraction in use in a system. In this scenario, the transistors are used
to implement the gates needed for the 1-bit adder, which is necessary for the implementation of
the 16-bit adder. These are different abstract layers that make up the design process.

Using the time in the laboratory, we analyzed the 16-bit adder system by observing the operation
of the 1-bit adder. In this process, there are two 1-bit inputs to be added, a possible carry input,
and a possible carry output. The truth table shown here is for the outputs (SUM, COUT) of our
system:

a b cin sum cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Figure 4.1 Truth Table

From these results, we can easily see that the Boolean expressions for the two system outputs are:

sum = a b cin
cout = a b + a cin + b cin
These two expressions require several logic gates:

COUT (carry output)

By inspection, the COUT output requires 2-input AND gates, and a 3-input OR gate; however,
the sum-of-products expression can be modeled using 2 and 3-input NAND gates, as shown here:

Page of
 Figure 4.2. Equivalent circuits

Because of this fact, all that is needed for the cout output is simply the 2 and 3-input NAND gates
(NAND gates have small, simple transistor models). The 3-input NAND, however, was modeled
using two 2-input NAND gates and a CMOS inverter, as shown here:

Figure 4.3.The 3-input NAND gate using 2-input NANDS and CMOS inverter.

This completes the gate-level requirements for the COUT output.

SUM
This output requires a three-input XOR gate. Thanks to the associative property of the Boolean
XOR operation, the three input XOR gate is simply two cascaded 2-input XOR gates.
Fundamentally, we need to implement the 2-input XOR gate using transistors.

Not surprisingly, we found that the XOR gate can be modeled using NAND gates and inverters.
This simplifies the problem, because, once again, the NAND gate and INVERTER are the
simplest of CMOS transistor implementations. The XOR gate simplifies to this:

Figure 4.4. The 2-input XOR gate with NANDs.

Page of
Now that we have the gate-level design requirements, we must implement the following gates
using transistors (device-level):

2-input NAND gate

Inverter

These are the only two gates needed for this laboratory, because the 2 and 3-input XOR gates are
built from these two fundamental constructs. The CMOS transistor-models for the above gates
are shown here:

Figure 4.5. Transistor Implementation: (a) CMOS Inverter (b) NAND gate.

With the ability to build the inverter and NAND gate from transistors, we can use these two
circuits to implement the Boolean logic functions for the COUT and SUM. The next step is to
design the 16-bit adder module necessary to complete the system.

Here is a simple implementation of the 16-bit adder using 16 1-bit adders:

Figure 4.6. The adder16 module.

Page of
The 3-bit Comparator
The Comparator module designed in Laboratory Experiment #2 can be used in this part, as we
will mimic the behavior using PMOS and NMOS modules. The behavior is as follows:

If a > b, outA should be high, outB should be low.

If b > a, outB should be high, outA should be low.
If b = a, both outputs should be low.

Using the design from Laboratory #2, the ‘switch-over’ was simple, as the only change was to
implement the same logic using NAND, NOT, and XNOR gates, in lieu of AND, OR and XNOR
gates.

The Dynamic Logic Modules

We were told in class that these modules will not be required for turn-in on this laboratory report
deadline. These processes involve load capacitors that cannot be implemented in Verilogger with
the skills we have acquire thus far in the curriculum.

Results and Logs

The simulation results are printed on the following pages, along with the Verilog code printed
directly out of the lab.

Page of
Conclusion

In this laboratory, we designed a 16-bit adder using transistor logic. The several different levels
of abstraction came into effect during the design process:

Device-level
Gate-level
Module-level

Each of the above design levels were used in this project. The resulting 16-bit adder has optimal
performance and timing. The module was tested using various input values, including a set that
would cause an over-flow (set the system’s carry_out flag). The results were very desirable.

The 3-bit comparator was a simple re-implementation of previous design, integrating the PMOS
and NMOS modules in Verilogger. The new implementation was tested for verisimilitude, and
likeness to previous lab experiment output values.

Page of
 CEEN 3100 – Digital Design and Interface
Lab 4
Simple System Design using Transistor-Level
Modeling

Rance Fredericksen
Steve Volz

Submitted: 9-30-2004
Due Date: 9-30-2004

Department of Computer and Electronics Engineering

University of Nebraska – Lincoln
Peter Kiewit Institute – Omaha, NE

Page of