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VHDL

Practical File
INDEX
S.NO. NAME OF THE EXPERIMENT DATE SIGNATURE

1. Model a flipflop and register using VHDL with


asynchronous reset.

2. Implement Binary and BCD Counter using


VHDL.

3. Design a Combinational circuit:2-4 decoder


and encoder.Also a binary to gray convertor
using VHDL.

4. Implement Serial In Parallel Out Shift Register


using VHDL.

5. Implement a Data Demultiplexer using VHDL


. Data is received on a high speed 4-bit input
bus and is output on three 4-bit output buses
one after the other.

6. Design aTrafiic light controller using VHDL.

7. Design of a state machine : Circuit to detect if


an incoming serial number is divisible by 5.
Simulate the incoming serial number with a
clock and Data in which is set to high or low.
The incoming data is entering from the right.

8. Model a Arithmetic Logic Unit (ALU) using


VHDL.
1)Model a flip-flop and register using VHDL with asynchronous reset
D-Flip Flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
Port ( d : in STD_LOGIC;
res : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end dff;

architecture Behavioral of dff is


begin
process(clk,res)
begin
if(res='1') then
q<='0';
else if(clk'event and clk='0') then
q<=d;
end if;
end if;
end process;
end Behavioral;
4-bit Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reg is
Port ( myin : in STD_LOGIC_VECTOR (3 downto 0);
clk1 : in STD_LOGIC;
res1 : in STD_LOGIC;
myout : out STD_LOGIC_VECTOR (3 downto 0));
end reg;

architecture Behavioral of reg is

component dff is
Port ( d : in STD_LOGIC;
res : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end component;
begin

if res1=0 then
myout<=myin;
else
myout<=0000;
end Behavioral;
2)Implement Binary and BCD Counter using VHDL

Binary Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity upcount is
Port ( myclk : in STD_LOGIC;
myres : in STD_LOGIC;
E : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end upcount;
architecture Behavioral of upcount is
signal count :STD_LOGIC_VECTOR(3 downto 0);
begin
process(myclk,myres)
begin
if myres='0' then
count<="0000";
elsif(myclk'event and myclk='1') then
if E='1' then
count<=count + 1;
else
count <=count-1;
end if;
end if;
end process;
q<=count;
end Behavioral;
BCD Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_counter is
Port ( myclk1 : in STD_LOGIC;
rst : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end BCD_counter;
architecture Behavioral of BCD_counter is
type state is (zero,one,two,three,four,five,six,seven,eight ,nine);
signal pr_state,nx_state : state;
begin
process (rst,myclk1)
begin
if (rst='1') then
pr_state <= zero;
elsif (myclk1'event and myclk1='0') then
pr_state <= nx_state;
end if;
end process;
process (pr_state)
begin
if pr_state=zero then
count <= "0000";
nx_state <= one;
elsif pr_state=one then
count <= "0001";
nx_state <= two;
elsif pr_state=two then
count <= "0010";
nx_state <= three;
elsif pr_state=three then
count <= "0011";
nx_state <= four;
elsif pr_state=four then
count <= "0100";
nx_state <= five;
elsif pr_state=five then
count <= "0101";
nx_state <= six;
elsif pr_state=six then
count <= "0110";
nx_state <= seven;
elsif pr_state=seven then
count <= "0111";
nx_state <= eight;
elsif pr_state=eight then
count <= "1000";
nx_state <= nine;
elsif pr_state=nine then
count <= "1001";
nx_state <= zero;
end if;
end process;
end Behavioral;
3) Design a Combinational circuit: 2-4 decoder and encoder.Also a binary to
gray convertor using VHDL
2 -4 decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;

architecture Behavioral of decoder is

output(0)<=not(in1) and not(in2) ;


output(1)<=in1 and not(in2);
output(2)<=not(in1) and in2 ;
output(3)<=in1 and in2;
end Behavioral;
Encoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encoder55 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
Enable : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (1 downto 0));
end encoder55;

architecture Behavioral of encoder55 is


begin
Output(0)<=A(3) or A(1)when Enable='1' else '0';
Output(1)<=A(2) or A(3) when Enable='1' else '0';
end Behavioral;
Binary to Gray code convertor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary2gray is
Port ( Input : in STD_LOGIC_VECTOR (3 downto 0);
RES : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (3 downto 0));
end binary2gray;
architecture Behavioral of binary2gray is
begin
Output(3)<=Input(3) when res='1' else '0';
Output(2)<=Input(3) xor Input(2) when res='1' else '0';
Output(1)<=Input(2) xor Input(1) when res='1' else '0';
Output(0)<=Input(1) xor Input(0) when res='1' else '0';
end Behavioral;
4)Implement Serial In Parallel Out Shift Register using VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating


---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity serin_parout is
Port ( myinput : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (3 downto 0));
end serin_parout;

architecture Behavioral of serin_parout is


signal temp:STD_LOGIC_VECTOR(3 downto 0);
begin
process(clock,reset,myinput)
begin
if (clock'event AND clock='1') then

temp(0)<=myinput;
temp(1)<=temp(0);
temp(2)<=temp(1);
temp(3)<=temp(2);

end if;
end process;
output<=temp;
end Behavioral;
5)Implement a Data Demultiplexer using VHDL . Data is received on a high
speed 4-bit input bus and is output on three 4-bit output buses one after the
other
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity my_demultiplexer is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
OUT1 : out STD_LOGIC_VECTOR (3 downto 0);
OUT2 : out STD_LOGIC_VECTOR (3 downto 0);
OUT3 : out STD_LOGIC_VECTOR (3 downto 0));
end my_demultiplexer;

architecture Behavioral of my_demultiplexer is


type state is (zero,one,two,three);
signal pr_state,nx_state : state;
begin
process (clk)
begin
if (clk'event and clk='0') then
pr_state <= nx_state;
else pr_state<=pr_state;
end if;
end process;

process (pr_state)
begin
if pr_state=zero then
OUT1<=A;
OUT2<="0000";
OUT3<="0000";
nx_state <= one;
elsif pr_state=one then
OUT2<=A;
OUT1<="0000";
OUT3<="0000";nx_state <= two;
elsif pr_state=two then
OUT3<=A;
OUT2<="0000";
OUT1<="0000";
nx_state <= three;
elsif pr_state=three then
OUT1<="0000";
OUT2<="0000";
OUT3<="0000";
nx_state <= zero;
end if;
end process;
end Behavioral;
6)Design aTrafiic light controller using VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity traffic is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
red : out STD_LOGIC;
yellow : out STD_LOGIC;
green : out STD_LOGIC);
end traffic;

architecture Behavioral of traffic is


type state is (ini, rd, yel,gn);
signal nstate, pstate : state;
signal tym : integer range 0 to 100;
signal count : integer range 0 to 100;
begin

process(clk,rst,nstate)
begin
if rst = '1' then
pstate <= ini;
else
if clk'event and clk = '1' then
if tym = count then
pstate <= nstate;
count <= 0;
else
count <= count +1;
end if;
end if;
end if;
end process;

process(clk)
begin
case pstate is

when ini =>


tym <= 1;
red <= '1';
yellow <= '0';
green <= '0';
nstate <= rd;

when rd =>
tym <= 60;
red <= '1';
yellow <= '0';
green <= '0';
nstate <= yel;
when yel =>
tym <= 10;
red <= '0';
yellow <= '1';
green <= '0';
nstate <= gn;

when gn =>
tym <= 40;
red <= '0';
yellow <= '0';
green <= '1';
nstate <= rd;

when others =>


tym <= 1;
red <= '1';
yellow <= '0';
green <= '0';
nstate <= ini;

end case;
end process;
end Behavioral;
7)Design of a state machine for a circuit to detect if an incoming serial
number is divisible by 5. Simulate the incoming serial data,which is set to
high or low, with a clock. The incoming data is entering from the right.

Divide by 5

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity myby5 is

Port ( x : in STD_LOGIC;

clk : in STD_LOGIC;

z : out STD_LOGIC);

end myby5;

architecture Behavioral of myby5 is

type state is(A,B,C,D);

signal ps:state;

begin

process(clk)

begin

if(clk 'event and clk='1') then

case ps is

when A =>

if(x='0') then

ps<=A; z<='0';

else ps<=B;z<='0';

end if;
when B =>

if(x='0') then

ps<=C; z<='0';

else ps<=B; z<='0';

end if;

when C =>

if(x='0') then

ps<=A; z<='0';

else ps<=D; z<='1';

end if;

when D =>

if (x='0') then

ps<=D; z<='1';

else ps<=B; z<='0';

end if;

end case;

end if;

end process;

end Behavioral;
8)Model a Arithmetic Logic Unit (ALU) using VHDL
entity arithunit is

Port ( input1 : in STD_LOGIC_VECTOR (07 downto 0);

input2 : in STD_LOGIC_VECTOR (07 downto 0);

output : out STD_LOGIC_VECTOR (07 downto 0);

selectline: in STD_LOGIC_VECTOR (02 downto 0);

cin : in STD_LOGIC);

end arithunit;

architecture Behavioral of arithunit is

begin

output <= input1 +input2 + cin when selectline = "000" else

input1 + input2 when selectline = "001" else

input1 - input2 - cin when selectline = "010" else

input1 - input2 when selectline = "011" else

input1 or input2 when selectline = "100" else

input1 and input2 when selectline = "101" else

not(input1) when selectline = "110" else

not input2 when selectline = "111"

end Behavioral;