Chapter 6 Multiplexer Commented [PK1]:

A multiplexer or mux is a device that selects one of several analog or digital input signals and
forwards that selected input signal into a single line as output. A multiplexer of 2n inputs has n
select lines, which are used to select, which input line we get at the output.

Multiplexers can be used for the implementation of Boolean functions, combinational

circuits. They can also be used for parallel to serial conversion.

Multiplexer is also called data selector or universal circuit.

All three variable Boolean equations can be implemented by using 8 1 multiplexer

without using any additional gates. Some but not all three variable Boolean equations can
also be implemented with 41 mux without using any additional gates.

Multiplexers, or MUXs, can be either digital circuits made from high speed logic gates used to
switch digital or binary data, or they can be analog types using transistors, MOSFETs or relays
to switch one of the voltage or current inputs through to a single output.
The most basic type of multiplexer device is that of a many to one-way rotary switch as shown in
Fig. 7.1.

Fig.6.1Basic Multiplexer and demultiplexers

The rotary switch also called a wafer switch is used to select individual data or signal lines
simply by turning its inputs ON or OFF. But how each data input can be automatically
selected using a digital device?
The answer to this question is multiplexers. Multiplexers are used as data selectors because it
selects each input line constructed from individual Analog switch encapsulated in a single IC
package.
This is done so as to reduce the number of logic gates required in a circuit designs, or when a
single data line or data bus is required to carry two or more different digital signals in time
division slots. For example, in a single 8-channel multiplexer, one channel is selected at a
particular time. Other channels are selected at different times.
The selection of each input line in a multiplexer is controlled by an additional set of inputs
called control lines or selection lines and according to the binary condition of these control
inputs, either HIGH or LOW the appropriate data input is connected directly to the output.
Normally, a multiplexer has an even number of 2n data input lines and a number of control
inputs n that correspond with the number of data inputs.
Multiplexers are different in operation to Encoders. Encoders are used to switch an n-bit input
signal line to multiple output lines that represent the binary coded (BCD) output equivalent of
the active input. The simple 2-line to 1-line (2-to-1) multiplexer can be built from basic logic
NAND gates as shown in Fig.6.2.

2-input Multiplexer Design

Fig. 6.2 2-to 1 selector

The input A of 2:1 line multiplexer circuit is a control input which is constructed from standard
NAND gates and control which input (I0 or I1) gets passed to the output at Q.
From the truth table given above, we can see that when the control input A is LOW i.e 0, input
I1 passes its data through the NAND gate multiplexer circuit to the output, while input I0 is
blocked. When the control input A is HIGH i.e 1, the input I0 passes data to the output Q while
input I1 is blocked.
So by the application of either a logic 0 or a logic 1 at A, the appropriate input, I0 or I1 gets
selected with the circuit acting as a single pole double throw (SPDT) switch.
In this example, since there is only one control line (A), it can switch 21=2 (I0, I1) inputs only and
the 2-input multiplexer connects one of the two 1-bit sources to a common output, producing a 2-
to-1-line multiplexer. The Boolean expression for input variables I1 and I0 in the form of
minterms with the control line A is given below:
Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1

The above equation can be oversimplified for the 2-input multiplexer circuit as;
Q = A.I1 + A.I0

Similarly, the increased number of data input lines can be selected. The larger multiplexer
circuits can be implemented using smaller 2-to-1 multiplexers as their basic building blocks. So a
4-input multiplexer requires two data select lines as 4-inputs represents 22 data control lines that
give a circuit with four inputs, I0, I1, I2, I3 and two data select lines A and B as shown in Fig. 6.3.

Fig. 6.3 4-to-1 channel selector (MUX)

The Boolean expression for this 4:1 MUX above with inputs A to D and data select lines a, b is
given as:
A = + + +

In this example at any one instant in time only ONE of the four analogue switches is closed,
connecting only one of the input lines A to D to the single output line Q. The control lines a
and b decides which switch is to be closed, so for this example to select input B to the output
at Q, the control lines should be a = 1 and b = 0.
The selection of the data through the multiplexer can be shown as a function of the data select
bits as shown in Fig. 6.3.Fig. 6.4 shows all combination of selection one by one from A to D.

Multiplexer Input Line Selection

Fig. 6.4 4-to-1 selector with control inputs

The more the control lines (n), the more the input lines can be used as a multiplexer can switch
2n inputs but each control line configuration will connect only ONE input to the output.
Then the implementation of the Boolean expression above using individual logic gates would
require the use of seven individual gates consisting of AND, OR and NOT gates as shown Fig.
6.5.

Fig. 6.5 4 channel selector with Gates only

The symbol used in logic diagrams to identify a multiplexer is as in Fig. 6.6.

Multiplexer Symbol
 Fig. 6.6 Circuit symbol of the MUX

Multiplexers are not only used to give a single output, but they can also be used to give multiple
outputs such as 4:2, 8:3 or even 16:4 etc. configurations and an example of a simple Dual
channel 4 input multiplexer (4:2) is shown in Fig. 6.7.

Fig. 6.7 4-to-2 channel selector (MUX)

4 input channels (S1A, S2A, S1B, S2B) are switched to 2 individual output lines (QA and QB).
Larger arrangements are also possible. Application of 4:2 MUX is to switch audio signals for
stereo pre-amplifiers or mixers.

Demultiplexer: A decoder with enable input, acts as demultiplexer. The demultiplexer is

alogical circuit that takes a single input source and sends it to one of several 2n possible
outputlines. The selection of specific output line is controlled by the bit values of n selection
lines.

Fig. 6.8 Line representation of Demultiplexer

Applications of Multiplexer
Multiplexers have very wide applications in digital systems where multiple data can be
transmitted using a single line. The important applications are:

Parallel to serial data conversion: A multiplexer is used to convert the parallel data into
serial data. In parallel data, we simultaneously get all the bits, whereas in serial data the
bits are made to occur one after the other.
Communication System: Multiplexers are used to increase the amount of data that is to
be sent over the network within a certain amount of time and bandwidth.
Multiplexers are also used as a switch or data selector which has a wide applications like
in telephone network.
Multiplexers are also used as a memory device to keep bulk amount of data.
Logic Function Generator: A mux can be used to generate any combinational logic
function.

Multiplexer Summary
From this article it can be inferred that Multiplexers are a combinational circuit because it is
memory less as there is no signal feedback path & is used as a switch. The multiplexer is a very
useful electronic circuit that has uses in many different applications such as signal routing, data
communications and data bus control applications.
A demultiplexer can be used to transmit parallel data in serial form via a single data link such as
a fibre-optic cable or telephone line and converted back into parallel data once again. The
advantage is that only one serial data line is required instead of multiple parallel data lines.
Therefore, multiplexers are sometimes referred to as data selectors.

Decoder

Binary Decoders are combinational logic circuits that is used to decode the coded information
from one format into another i.e from a digital input signal lines into an equivalent decimal code.
Binary decoders may have of 2-bit, 3-bit or 4-bit input codes depending upon the number of data
input lines. A decoder having n-bit code, can be represented through 2n possible values. Thus, a
decoder generally decodes a binary value into a non-binary one by putting only one of
its n outputs to logic 1.
If a binary decoder receives n inputs, it activates one and only one of its 2n outputs based on
that input with all other outputs deactivated.
Thus, a standard combinational logic decoder is a n-to-m decoder, where m 2n, and whose
output, Y is dependent only on its present input states.
There can be two types of decoders. One in which only one of its output is activated at a time.
This is called 1-of-n decoder. The other is code translator, in which multiple outputs can be
activated at the same time like in seven segment display.

An example of a 2-to-4 line decoder along with its truth table is given below.
A 2-to-4 Binary Decoders

Fig 6.9 2 to 4 binary decoder

From the truth table we can infer that,

 Y0 = AB

Y1= AB

Y2= AB

Y3= AB

In this example, a 2-to-4 line binary decoder consists of an array of four AND gates. The 2
binary inputs A and B are decoded into one of 4 outputs. This is a type of 1-of-n decoder
The binary inputs A and B determine which output (Y0 to Y3) is activated at one time. So,
whichever output line is HIGH, identifies the binary code present at the input, in other words it
de-codes the binary input.
Enable- EN is used to controls the outputs from the device. This extra input allows the decoders
outputs to be turned ON or OFF as required.
So basically a binary decoder is a demultiplexer with an additional data line (EN) that is used to
enable the decoder.
We saw above a 2-to-4 line binary decoder. Similarly there are 3-to-8 line decoder having 3
inputs & 23=8 outputs, 4-to-16 line decoder having 4 inputs & 24=16 output lines, and so on.
Let us see a 4-to-16 binary decoder made up from two 3-to-8 decoder.

4-to-16 Binary Decoder Configuration.

Fig. 6.10 4-to-16 decoder using 3-to-8 decoder

Enable E is used to select the decoder from the two 3 to 8 decoder given, & the inputs A, B,
C are used to select the outputs from the selected decoder.
However, there is a limit to the number of inputs that can be used for one particular decoder,
because as n increases, the number of AND gates required to produce an output also becomes
larger resulting in the fan-out of the gates used to drive them becoming large.
Decoders can also be implemented with NAND gates.

2-to-4 Line NAND Binary Decoder

Since NAND is the inverted form of AND gate, so, only one output will be LOW and all the
other outputs HIGH at any given time.

Fig. 6.11 2-to-4 decoder using NAND Gates

Encoder
Multiplexer selects one individual data input line and then sends that data to a single output line
or switch. A Binary Encoder takes ALL its data inputs one at a time and then converts them
into a single encoded output. So we can say that, a binary encoder is a multi-input combinational
logic circuit which converts the logic level 1 data at its inputs into an equivalent binary code at
its output.

An n-bit binary encoder has 2n input lines and n-bit output lines, like 4-to-2 encoder, 8-to-3
encoder, 16-to-4 encoder and so on.
The output lines of a digital encoder generate the binary equivalent of the input line whose value
is equal to 1 and are available to encode either a decimal or hexadecimal input pattern to
typically a binary or B.C.D (binary coded decimal) output code.
4-to-2 Bit Binary Encoder

Fig.6.12 4-to-2 bit Encoder

The disadvantage of standard digital encoders is that they can generate the wrong output code
when more than one input is high i.e at 1. This problem is overcome by Priority Encoder.

Priority Encoder
The Priority Encoder allocates a priority level to each input. The priority encoders output
corresponds to the currently active input which has the highest priority. So when an input with a
higher priority is present, all other inputs with a lower priority will be ignored.

8-to-3 Bit Priority Encoder

Fig.6.13 8-to-3 bit priority Encoder

Priority encoders output the highest order input first for example, if input lines D1, D4 and
D6 are applied simultaneously the output code would be for input D6 (110) as this has the
highest order out of the 3 inputs. Once input D6 had been removed the next highest output
code would be for input D4 (100), and so on.
The truth table for 8:3 Priority Encoder is shown above. Here X =dont care, which can be
either 0 or 1.D0-D7 are inputs & Q0 -Q2 are outputs.
Output Q1

Output Q2

Then the final Boolean expression for the priority encoder including the zero inputs is defined as:

In practice these zero inputs would be ignored allowing the implementation of the final Boolean
expression for the outputs of the 8-to-3 priority encoder. We can constructed a simple encoder
from the expression above using individual OR gates as follows.
Digital Encoder using Logic Gates

Fig,6.14 Digital Encoder using Logic Gates

Digital Encoder Summary

Then to summarise, the Digital Encoder is a combinational logic circuit that generates a specific
code at its outputs such as binary or BCD in response to one or more active inputs. The two types
of digital encoder are Binary Encoder and Priority Encoder.
We have seen that the Binary Encoder converts one of 2n inputs into an n-bit output. Then a
binary encoder has fewer output bits than the input code. Binary encoders can be constructed
from simple AND or OR gates.The main disadvantages of a binary encoder is that it would
produce an error if more than one inputs are high at the same time. This problem was overcome
by Priority Encoder.
The Priority Encoder generates an output code based on the highest prioritised input. Priority
encoders are used extensively in digital and computer systems as microprocessor interrupt
controllers where they detect the highest priority input.
Example 1. The Boolean expression for a 3 input function in min term form is
Y(A,B,C) = m(2,3,4,6).
Implement the above function using a multiplexer.
Solution: Since the no. of inputs is 3, so we require an 8:1 MUX . The variables C,B,A are
connected to selection lines S2, S1 and S0 respectively. The input lines are connected to logic 1(i.e
+Vcc) & the rest are connected to 0 and grounded. Fig. shows the implementation.
The complete expression for the output is
Y(A,B,C)= ABC + ABC + ABC + ABC

Fig 6.15

Example 2 Implement the following Boolean function using 8:1 multiplexer with C as the input
line and A,B,D as selection lines.

Solution: The truth table of the above function is shown in figure 6.9(a). An 8:1 MUX is
used. The rows with C & C have one input while the other input variable A,B,D remains the
same.
Row A B C D Y
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1

(a) Truth Table

 Fig 6.15 (b) Implementation

I0 I1 I2 I3 I4 I5 I6 I7
C 0 1 4 5 8 9 12 13

C 2 3 6 7 10 11 14 15

C 0 0 1 1 1 0 1
 Fig 6.16

Fig 6.16

Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers A & B to
determine whether: A > B, or A = B, or A < B.
Fig 6.17 Fig 6.18 1-bit magnitude comparator
The circuit diagram for the 1-bit magnitude comparator is shown above.
The truth table is given below:

For 2-bit numbers, we compare first the MSBs & then further the next significant
bits are compared. For example: Let A = A1A0 and B=B1B0. If A1 is not equal to B1,
then either A is greater than B for A1 =1 & B1= 0 ,or A is less than B for A1= 0 & B1=1.
At this stage the process of comparison ceases. If the MSBs are equal, i.e., A1=B1 only
then we need to compare the next significant bits A0 and B0 and decide whether the
number is greater than, less than or equal. Similarly a 4-bit comparator works.
The schematic diagram of 4-bit comparator is shown below, where the two 4 bits
numbers are taken as, A = A3 A2 A1 A0 and B3 B2 B1 B0 where A3 and B3 are the most
significant bits.
Fig 6.19 4-bit magnitude converter

Questions for Practice:

Q1. Design an eight bit 2:1 MUX with the help of basic gates.

Q2. Design 16:1 MUX with a clock and explain it.

Q3. State the applications of multiplexer.

Q4. Realize the following function using 8:1 MUX,

f(ABCD) = m(1,2,5,6,7,8,10,12,13,15)

Q5. Write the difference between MUX and DEMUX.

Q6. Implement a one bit full adder using 8:1 MUX.

Q7. Using 8:1 MUX, implement the following functions:

f(A,B,C,D) = BC + ABD + ACD

Q8. Explain the operation of multiplexer.
Q9. What is the role of select lines in multiplexer.
Q10. How can a decoder be used as a demultiplexer? Explain.
Q11. Form a multiplexer tree to give 4:1 MUX using three 2:1 multiplexers.
Q12. Explain the use of decoder driver ICs in digital circuits.
Q13. Derive 1 to 16 DEMUX from 3 to 8 decoders.
Q14. Design a hexadecimal to binary encoder.
Q15. Design a multilevel 8 line to 256 line decoder.
Q16. What is an encoder? Draw the logic circuit of decimal to BCD encoder and explain its
working.
Q17. What is meant by priority encoder? How is it different from encoder?
Q18. What is a multilevel decoder? What is the advantage of multilevel decoding?
Q19. Draw the block diagram of two level 4:16 line decoder.
Q20. What is magnitude comparator?
Q21 Draw the circuit of a two bit magnitude comparator. Taking 11 and 10 as input find the
output.