Quartus II v7.

2 : The
SignalTap II Logic Analyzer
Lab
Exercises SignalTap II Logic Analyzer 7.2

SignalTap II v7.2 LAB

Requirements:
Quartus II v. 7.2 production release
Altera Development kit, e.g. Altera Cyclone III Starter Board

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The SignalTap II Logic Analyzer 7.2 Exercises

Lab 1: SignalTap II Logic

Analyzer Basics
Objectives:
Configuring basic and advanced trigger conditions for the SignalTap II Logic
Analyzer
Compare and contrast the sequential and custom state-based triggering flows.
Use segmented buffers with sequential and state-based trigger flows

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Exercises SignalTap II Logic Analyzer 7.2

Initial Setup
This project uses a simple pattern generator with pre-loaded data patterns to be used with each of the
exercises. The project is developed on a Cyclone III starter board, however, it is not specific to any
particular device architecture.

1. Restore the project SignalTap72_lab.qar into a working directory.

2. Open the project pattern_gen.qpf within the working directory
3. If necessary, reassign the device to target your hardware setup. If you reassign the
device, make sure that you set Reserve all unused pins to As input tri-stated with
weak pull-up resistor

Figure 1

4. If you changed the device, open up the Pin Planner and assign a pin location to the clk
node. This signal should be connected to a clock pin that is appropriate to your
hardware setup.
Note: If youve switched devices, In order to get the clk node to appear within Pin
Planner, you must run Analysis and Elaboration first.

Clock pin locations for commonly used device kits

Cyclone III Starter Board B9
Cyclone II Starter Board L1
Cyclone II NIOS dev. Kit B25
Stratix II NIOS dev. Kit B13
Stratix NIOS dev. Kit K17

5. Compile your design.

6. Open the SignalTap_Lab.stp file, located in the working directory of your project.

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The SignalTap II Logic Analyzer 7.2 Exercises
This design contains a small counter connected to the address port of a ram block. A few pre-stored
patterns are loaded into the ram-block using a set of tcl commands from the in-system memory content
editor. The STP file that you just opened contains the address and data signal groups that are connected
to the SignalTap II Logic Analyzer instance. The output signal group is the pre-stored ram data output
that we will be using for data analysis for all of the exercises provided in this lab.

Figure 2

Basic Trigger Conditions

Basic Trigger conditions allow you to quickly setup a comparison of the signal group to a desired value.
For basic trigger conditions, note that all comparisons that you setup are logically ANDed together.

1. In the setup tab, create a basic trigger condition for the output signal group when it
equals 0xE6. Leave all of the options on the signal configuration pane at their default
values.
2. Save the STP file. A prompt will ask you whether or not you want to enable the stp
file for the current project. Click yes.
3. Compile the project.
Note: If you receive a compilation error, refer to the notes provided in the solutions document.

4. Connect the programming hardware to your target setup. Program your device using
the most recent .sof file that youve just generated. You can do so by using the JTAG
Chain Configuration window in the SignalTap II GUI.

Figure 3

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Exercises SignalTap II Logic Analyzer 7.2
5. In the <unzip_directory> \LAB_instructions directory, double-click on the Patterns.bat
file to run the stored-patterns script. This should bring up the Patterns buttons panel.
Each button on the patterns panel will perform a burst transaction of a pre-stored
pattern once onto the output bus.

Figure 4

6. Make sure that the settings on JTAG configuration window match your target setup.
On the SignalTap II GUI, click the Start Analysis icon ( )
7. On the Patterns button panel, click Pattern1. The SignalTap II logic Analyzer should
have triggered the acquisition buffer and displayed the data contents to the screen on
the Data tab. Note that sample # 0 is always the point where the logic analyzer
triggers.
8. Question : What is the value of the output signal group one clock cycle after the
trigger position (sample # 1)?

Advanced Trigger Conditions

Advanced Trigger conditions allow greater flexibility as compared with basic trigger conditions. With
Advanced Trigger conditions you can build trigger conditions from a combination of relational operators,
logical operators and delay operators to capture the event of interest.
In this second exercise, we will use an advanced trigger condition to compare the data stream of two
signal groups. The output signal group using pattern1 in this case represents the count signal group
inverted with two pipeline delays. However there is a stuck bit on one of the signals on the output bus.
We will find the stuck bit by using an advanced trigger condition.

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The SignalTap II Logic Analyzer 7.2 Exercises

Figure 5
Within the advanced trigger condition editor, we can use a delay operator to align the count signal group
to the output group so that we can do real time comparisons between the two signal groups. After we
have delay matched the two buses, we can invert the count bus to compare it with the output signal group
and specify that the SignalTap II logic Analyzer triggers whenever there is a mismatch.

1. Within the setup tab on the SignalTap II GUI, change trigger condition 1 to an
advanced trigger condition. The advanced trigger condition editor should appear.
2. In the node list on the upper left hand side, drag both signal groups into the Advanced
trigger condition editor.
3. To delay count signal group, double click on the signal group to bring up the Object
Properties list. Under Existing parameter settings, select data delay and configure
the parameter to 2.

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Exercises SignalTap II Logic Analyzer 7.2

Figure 6

4. Connect the count signal bus to a bitwise complement operator. (In the object Library
under bitwise operator -> bitwise complement). Use an inequality operator (
comparison -> inequality) to compare the bitwise complement output and the output
signal group. Then, connect the output of the comparison operator to Result.

The Result object connects directly to the SignalTap II Logic Analyzer instance. The SignalTap II
Logic Analyzer instance will trigger the acquisition buffer when Result is true.

If the Result object does not appear on screen, Right click in the condition editor
window and choose Arrange all objects. Your setup should look like Figure 7

Figure 7

5. Recompile the project and program your device using the regenerated .sof file.
6. On the Patterns button panel, click Pattern1 to initialize the values on the count and
result signal groups.
7. Start data analysis on the embedded logic analyzer.
8. On the Patterns button panel, click Pattern1.
9. Question : Based on the trigger position on the resulting waveform, which bit value is
stuck at 1 on the output signal group?
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The SignalTap II Logic Analyzer 7.2 Exercises

Trigger Flow
Setting up a trigger flow allows you to trigger the acquisition buffer after a number of events occur.
There are two types of trigger flows sequential and the custom state-based. Well take a look at the
sequential triggering flow first.
The sequential triggering flow allows you to quickly setup a flow that triggers on a simple sequence of
events. Pattern2 on the Patterns button panel, contains a burst cycle with two simple sequences
embedded within the transaction. The sequences are delineated by the pattern 0xAA->0xBB->0xCC, as
shown in figure 7. The next set of exercises will use a triggering flow to capture the data patterns in
Pattern2.

Figure 8 : Pattern2 data format

Sequential Triggering Flow:

1. In the Signal Configuration pane, make the acquisition buffer segmented, with 2 32
sample segments.
2. Verify that the Trigger flow control field is set to Sequential
3. Under Trigger Conditions, enable three trigger condtions.
4. Set three basic trigger conditions to trigger on the 0xAA 0xBB 0xCC sequence in
Figure 8.
5. Compile the changes and program the device with the new .sof file.
6. Run data analysis.
7. Click on the pattern2 button on the pre-stored patterns panel.
The data tab shows the result of data analysis only after all trigger conditions have evaluated true
and all acquisition segments have triggered. Since we chose a segmented buffer in this case, the
data tab will display each acquisition segment within the waveform. The segmented buffer markers
appear in blue above the sample numbers to demarcate the boundaries between segments.

Figure 9

8. Question : What is the data on the output signal group one clock cycle after
triggering the first time (sample #1 first segment)?

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Exercises SignalTap II Logic Analyzer 7.2

9. Question : How about after the triggering the second time (sample#1 second
segment)?

10. Question : Does the second acquisition segment match the second sequence
(containing segment Y) in Figure 8? If not, what did the second acquisition buffer
capture?

Notice that the second buffer doesnt contain the 0xAA->0xBB->0xCC sequence around
the trigger point it only contains the last trigger condition that you have specified; that
is, trigger condition 3. The sequential triggering flow is useful for setting up a sequence
of conditions that occur once; however, it may not be as useful when used with segmented
acquisition buffers. The sequential trigger flow goes through the full evaluation of all
your trigger conditions on the first segment in your acquisition buffer; subsequent
buffers are triggered on the last condition you have specified. Further, the sequential
triggering maybe a limitation especially in the case that you want to capture multiple
recurring conditions of the same sequence. The State-based trigger flow is introduced in
the Quartus II software v7.2 to address this limitation.

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The SignalTap II Logic Analyzer 7.2 Exercises

State-based Trigger Flow:

The State-based trigger flow allows you to define precisely the manner in which the triggering conditions
evaluate. In the previous example, If we wanted to capture the y data value, we would have had to define
6 trigger conditions. Using the state-based trigger flow, we can define a flow to capture the both x and y
data patterns in Figure 8 without defining more than three trigger conditions.

1. In the Signal Configuration Pane, select state-based for the trigger flow control. The
State-Based Trigger Flow Tab should appear. All other parameters on the setup tab
should remain from the previous exercise.
2. Complete the partial trigger flow description given in the state description boxes.
You can use the tooltips that appear in the state boxes to help guide text entry. A
detailed reference to the state-based description language can be found in the
SignalTap II chapter in the Quartus II software handbook
3. Compile the changes to the STP file and program the device with the new .sof file.
4. Run data analysis.
5. Click on the pattern2 button on the Patterns button panel.
6. Question : What is the data on the output signal group one clock cycle after
triggering (sample #1 first segment)?

7. Question : How about after the second trigger (sample#1 second segment)

Another useful example is to use the state-based flow to trigger on an event after an event that occurs a
number of times. The state-based flow description supports the use of status and counter flags to help
guide the trigger flow. Counters in the trigger flow make it easy to keep track of recurring events.

8. Configure the Logic Analyzer to trigger when the pattern AA occurs five times on the
output signal group. Set the number of states in the State-based trigger flow to 1
state and copy the following flow description into State.
if (c1 == 5 )
trigger;
else if ( condition1 )
increment c1;

Note that since the conditional statements are priority based, the conditional statement to check the
counter value appears first.

9. Compile the project with the trigger flow modifications. Program the hardware and
reanalyze pattern2.
Notice that the SignalTap II LA only used a single acquisition segment (with sample
depth 32). The trigger command stopped acquisition even though there was another
segment available to write to.

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Exercises SignalTap II Logic Analyzer 7.2

10. Question : What data value is on the output signal group after the logic analyzer
triggered (sample #1)?

You have just completed lab 1!

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The SignalTap II Logic Analyzer 7.2 Exercises

Lab 2: State-based trigger

flow exercises

Objectives:
Using segmented buffers with the state based trigger flow to efficiently capture
disjointed events
Using advanced trigger conditions in conjunction with the state-based trigger
flow.

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Exercises SignalTap II Logic Analyzer 7.2

Exercise #1:
The state-based trigger flow is useful for detecting any type of data pattern that is non-
contiguous. For example, a trigger condition or set of trigger conditions can be used to
mark a specific pattern in the data stream, such as an address value or some recognizable
preamble in a packet based transmission scheme. A separate trigger condition can then
mark the start of the payload data that you want to look at. After you have defined your
trigger conditions, you can use the state-based trigger flow to organize the trigger
conditions to capture on desired data patterns.
In this exercise, Pattern3 on the Patterns button panel will consist of a number of
headers in the form of 0xAA, 0xBB, 0xCC, and 0xDD. The payload values of interest
reside some clock cycles away from the marker bit, as specified by Figure 10. Define a
trigger flow to capture the data values W, X, Y, and Z. For the acquisition buffer, you are
limited to a sample depth of 64.

Figure 10

Hint: Divide the acquisition buffer into four segmented buffers. For data values that are less than 16
clock cycles from the header, use a post-count argument with the buffer control action. For data
values that are greater than 16 clock cycles from the header, initialize a counter to delay the clock
cycle count to trigger precisely on the data packet that youre trying to find. You should only need to use
basic trigger conditions and the State-based trigger flow.

What is the data value W:X:Y:Z ?

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The SignalTap II Logic Analyzer 7.2 Exercises

Exercise #2:
The state-based triggering flow can be used in conjunction with the Advanced trigger
condition editor for increased flexibility of finding desired events. The use of advanced
trigger conditions is especially useful for finding something in a data-stream that does not
match a particular pattern.
In this exercise, pattern4 on the Patterns button panel represents an alphanumeric ASCII
sequence (Range of values for alphanumeric characters in the sequence is between 0x30
and 0x7A) There are a string of values embedded within the data stream that is not
alphanumeric. Using the state-based triggering and an advanced trigger condition, find the
length of the non-alphanumeric sequence.

Figure 11

What is value of the non-alphanumeric character?

What is the length of the non-alphanumeric sequence?

You have just completed lab 2!

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