INDEX

SN. CONTENT PAGE

I INTRODUCTION TO POWER ELECTRONIC DEVICES

1. SCR 2
2. TRAIC 9
3. UJT 11
4. MOSFET 15

II STUDY OF POWER ELECTRONIC DEVICES

1. CHARACTERISTICS OF DIAIC 22
2. CHARACTERISTICS OF UJT 24
3. CHARACTERISTICS OF SCR 26
4. CHARACTERISTICS OF TRIAC 28
5. CHARACTERISTICS OF MOSFET 31
6. UJT RELAXATION OSCILLATOR 34
7. R AND RC GATE PULSING OF SCR 36
8. SCR COMMUTATION METHODS 43
9. TEMPRATURE CONTROL USING MOSFET/SCR 44
10. FAN SPEED CONTROL USING MOSFET 46
11. MOSFET/SCR AS A SWITCH 49

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 INTRODUCTION TO POWER ELECTRONICS DEVICES

SCR
INTRODUCTION:
Although the large semiconductor diode was a predecessor to thyristors, the modern power
electronics area truly began with advent of thyristors. One of the first developments was the
publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell
Laboratories, probably for use in Bells Signal application. However, engineers at General Electric
quickly recognized its significance to power conversion and control and within nine months
announced the first commercial Silicon Controlled Rectifier in 1957. This had a continuous current
carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also known as the Silicon
Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high
power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating
in excess of 4kA are available. They have reigned supreme for two entire decades in the history of
power electronics. Along the way a large number of other devices with broad similarity with the
basic thyristor (invented originally as a phase control type device) have been developed. They
include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light activated SCR (LASCR),
Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac and the Gate turn
off thyristor (GTO).
From the construction and operational point of view a thyristor is a four layer, three terminal,
minority carrier semi-controlled device. It can be turned on by a current signal but can not be turned
off without interrupting the main current. It can block voltage in both directions but can conduct
current only in one direction. During conduction it offers very low forward voltage drop due to an
internal latch-up mechanism. Thyristors have longer switching times (measured in tens of s)
compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using a control
input, have all but eliminated thyristors in high frequency switching applications involving a DC
input (i.e, choppers, inverters). However in power frequency ac applications where the current
naturally goes through zero, thyristor remain popular due to its low conduction loss its reverse
voltage blocking capability and very low control power requirement. In fact, in very high power (in
excess of 50 MW) AC DC (phase controlled converters) or AC AC (cyclo-converters) converters,
thyristors still remain the device of choice.

Constructional Features of a Thyristor:

Fig.1 shows the circuit symbol, schematic
construction and the photograph of a typical
thyristor.

Fig.1: Constructional features of a thysistor

(a) Circuit Symbol, (b) Schematic Construction

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Fig. 1 (b) the primary crystal is of lightly doped n- type on either side of which two p type layers
with doping levels higher by two orders of magnitude are grown. As in the case of power diodes and
transistors depletion layer spreads mainly into the lightly doped nregion. The thickness of this layer
is therefore determined by the required blocking voltage of the device. However, due to conductivity
modulation by carriers from the heavily doped p regions on both side during ON condition the ON
state voltage drop is less. The outer n+ layers are formed with doping levels higher then both the p
type layers. The top p layer acls as the Anode terminal while the bottom n+ layers acts as the
Cathode. The Gate terminal connections are made to the bottom p layer. As it will be shown
later, that for better switching performance it is required to maximize the peripheral contact area of
the gate and the cathode regions. Therefore, the cathode regions are finely distributed between gate
contacts of the p type layer. An Involute structure for both the gate and the cathode regions is a
preferred design structure.

Basic operating principle of a thyristor:

The underlying operating principle of a thyristor is best understood in terms of the two transistor
analogy as explained below.

Fig. 2: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic
division in component transistor (c) Equivalent circuit in terms of two transistors.

Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive
with respect to the cathode and the gate terminal open. With this voltage polarity J1 & J3 are forward
biased while J2 reverse biased.
Under this condition.
Ic1 =1 IA + Ico1 --------(1)
Ic2 =2 IK + Ico2 --------(2)
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Where 1 & 2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation
currents of the CB junctions of Q1 & Q2 respectively.
Now from Fig. 2 (c).
Ic2 + Ic2 = IA ---------(3)
IA = IK (IG = 0) ----------(4)

Combining Eq (1) & (4)

IA = [( Ico1 + Ico2 )/ { 1- (1 + 2 )} ] -----------(5)
= [Ico/ { 1- (1 + 2 )} ]
Where Ico = Ico1 + Ico2 is the total reverse leakage current of J2

Now as long as VAK is small Ico is very low and both 1 & 2 are much lower than unity.
Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased up
to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche
multiplication process. As Ico increases both 1 & 2 increase and 1 + 2 approaches unity.
Under this condition large anode current starts flowing, restricted only by the external load
resistance. However, voltage drop in the external resistance causes a collapse of voltage across the
thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage drop
across the device settles down to approximately equivalent to a diode drop. The thyristor is said to be
in ON state.
Just after turn ON if Ia is larger than a specified current called the Latching Current IL, 1 and 2
remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF
is by bringing IA below a specified current called the holding current (IH) where upon 1 & 2
starts reducing. The thyristor can regain forward blocking capacity once excess stored charge at J2 is
removed by application of a reverse voltage across A & K (ie, K positive with respect A).
It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to
cathode) without increasing the forward voltage across the device up to the forward break-over level.
With a positive gate current equation 4.4 can be written as
IA + IG = IK
Combining with Eqns. (1) to (3)
IA = [(2 * IG + Ico )/ { 1- (1 + 2 )} ]
Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence
VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a
thyristor is turned ON. When a reverse voltage is applied across a thyristor (i.e, cathode positive with
respect to anose.) junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the
junction J3 has a very low reverse break down voltage since both the n+ and p regions on either side
of this junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported
by junction J1. The maximum value of the reverse voltage is restricted by a) The maximum field
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strength at junction J1 (avalanche break down) b) Punch through of the lightly doped n- layer. Since
the p layers on either side of the n- region have almost equal doping levels the avalanche break down
voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break down voltage of a
thyristor are almost equal.Up to the break down voltage of J1 the reverse current of the thyristor
remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics
of a thyristor is similar to that of a single diode.
If a positive gate current is applied during reverse bias condition, the junction J3 becomes forward
biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles of their
respective emitters and collectors interchanged. However, the reverse 1 & 2 being significantly
smaller than their forward counterparts latching of the thyristor does not occur. However, reverse
leakage current of the thyristor increases considerably increasing the OFF state power loss of the
device. If a forward voltage is suddenly applied across a reverse biased thyristor, there will be
considerable redistribution of charges across all three junctions. The resulting current can become
large enough to satisfy the condition 1 + 2 = 1 and consequently turn on the thyristor. This is
called dv /dt turn on of a thyristor and
should be avoided
Static output i-v characteristics of a
thyristor

The circuit symbol in the left hand side

inset defines the polarity conventions of
the variables used in this figure. With ig =
0, VAK has to increase up to forward
break over voltage VBRF before
significant anode current starts flowing.
However, at VBRF forward break over
takes place and the voltage across the
thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK)
remains almost constant at VH (1-1.5v) while the anode current is determined by the external load.
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break
over voltage (VBRF) as a function of the gate current (Ig) After Turn ON the thyristor is no more
affected by the gate current. Hence, any current pulse (of required magnitude) which is longer than
the minimum needed for Turn ON is sufficient to effect control. The minimum gate pulse width is
decided by the external circuit and should be long enough to allow the anode current to rise above the
latching current (IL) level.
The left hand side of Fig. 3 shows the reverse i-v characteristics of the thyristor. Once the thyristor is
ON the only way to turn it OFF is by bringing the thyristor current below holding current (IH). The
gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens
automatically during negative zero crossing of the supply voltage. This is called natural
commutation or line commutation. However, in dc circuits some arrangement has to be made to
ensure this condition. This process is called forced commutation. During reverse blocking if ig = 0
then only reverse saturation current (Is) flows until the reverse voltage reaches reverse break down
voltage (VBRR). At this point current starts rising sharply. Large reverse voltage and current
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generates excessive heat and destroys the device. If ig > 0 during reverse bias condition the reverse
saturation current rises as explained in the previous section. This can be avoided by removing the
gate current while the thyristor is reverse biased. The static output i-v characteristics of a thyristor
depends strongly on the junction
temperature as shown in Fig. 4.

Fig. 4: Effect of junction

temperature (Tj) on the output i v
characteristics of a thyristor.

Thyristor ratings
Some useful specifications of a
thyristor related to its steady state characteristics as found in a typical manufacturers data sheet
will be discussed in this section.
(A) Voltage ratings
Peak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i.e,
anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand
during working. It is useful for calculating the maximum RMS voltage of the ac network in which
the thyristor can be used. A margin for 10% increase in the ac network voltage should be considered
during calculation.
Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transient voltage
that a thyristor can block repeatedly in the OFF state. This rating is specified at a maximum
allowable junction temperature with gate circuit open or with a specified biasing resistance between
gate and cathode. This type of repetitive transient voltage may appear across a thyristor due to
commutation of other thyristors or diodes in a converter circuit.
Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value of the
forward transient voltage that does not repeat. This type of over voltage may be caused due to
switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply network.
Its value is about 130% of VDRM. However, VDSM is less than the forward break over voltage
VBRF

Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negative
with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the peak
negative value of the ac supply voltage.
Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may
occur repeatedly during reverse bias condition of the thyristor at the maximum junction temperature.
Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reverse transient
voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less than reverse
break down voltage VBRR.

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Fig. 5 shows different thyristor voltage ratings on a comparative scale.

Fig. 5: Voltage ratings of a thyristor.

(B) Current ratings

Maximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallic
joints, leads and interfaces depends on the forward RMS current Irms. RMS current rating is used as
an upper limit for dc as well as pulsed current waveforms. This limit should not be exceeded on a
continuous basis. Maximum average current (Iav): It is the maximum allowable average value of the
forward current such that
i. Peak junction temperature is not exceeded
ii. RMS current limit
is not exceeded
Manufacturers usually
provide the forward average
current derating
characteristics which shows
Iav as a function of the case
temperature (Tc ) with the
current conduction angle as
a parameter. The current wave
form is assumed to be formed
from a half cycle sine wave of
power frequency as shown in
Fig. 6.
Maximum Surge current
(ISM): It specifies the
maximum allowable non repetitive current the device can withstand. The device is assumed to be
operating under rated blocking voltage, forward current and junction temperation before the surge
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current occurs. Following the surge the device should be disconnected from the circuit and allowed
to cool down. Surge currents are assumed to be sine waves of power frequency with a minimum
duration of cycles. Manufacturers provide at least three different surge current ratings for different
durations.
For example
IsM = 3000 A for cycle
IsM = 2100 A for 3 cycles
IsM = 1800 A for 5 cycles
Alternatively a plot of IsM vs. applicable cycle numbers may also be provided.
Maximum Squared Current integral (i2 dt): This rating in terms of A2 S is a measure of the
energy the device can absorb for a short time (less than one half cycle of power frequency). This
rating is used in the choice of the protective fuse connected in series with the device.
Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode current
reaches this level. Otherwise, upon removal of gate pulse, the device will turn off.
Holding Current (IH): The anode current must be reduced below this value to turn off the thyristor.
Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous
forward current at a given junction temperature.
Average power dissipation (Pav): Specified as a function of the average forward current (Iav) for
different conduction angles as shown in the fig. 7. The current wave form is assumed to be half cycle
sine wave (or square wave) for power frequency.

Fig. 7: Average power dissipation vs average forward current in a thyristor.

In the above diagram

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Gate Specifications
Gate current to trigger (IGT): Minimum value of the gate current below which reliable turn on of
the thyristor can not be guaranteed. Usually specified at a given forward break over voltage.
Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below which
reliable turn on of the thyristor can not be guaranteed. It is specified at the same break over voltage
as IGT.
Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below which the
thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit must
be below this level.
Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate
and the cathode terminals without damaging the junction.
Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathode junction
should not exceed this value for gate current pulses wider than 100 s. Peak forward gate current
(IGRM): The forward gate current should not exceed this limit even on instantaneous basis.

TRIAC
The TRIAC is a member of the thyristor family. But unlike a thyristor which conducts only in one
direction (from anode to cathode) a TRIAC can conduct in both directions. Thus a TRIAC is similar
to two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case
of a thyristor, the conduction of a TRIAC is initiated by injecting a current pulse into the gate
terminal. The gate loses control over conduction once the TRIAC is turned on. The TRIAC turns off
only when the current through the main terminals become zero. Therefore, a TRIAC can be
categorized as a minority carrier, a bidirectional semi-controlled device. They are extensively used in
residential lamp dimmers, heater control and for speed control of small single phase series and
induction motors.

Construction and operating principle

Fig. 1 (a) and (b) show the circuit symbol and schematic cross section of a TRIAC respective. As the
TRIAC can conduct in both the directions the terms anode and cathode are not used for TRIAC
s. The three terminals are marked as MT1 (Main Terminal 1), MT2 (Main Terminal 2) and the gate
by G. As shown in Fig. (b) the gate terminal is near MT1 and is connected to both
N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2 and P2 regions while MT2
is connected to N4 and P1 regions

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Fig. 1. Circuit symbol and schematic construction of a TRIAC (a) Circuit symbol (b) Schematic
construction.
Since a TRIAC is a bidirectional device and can have its terminals at various combinations of
positive and negative voltages, there are four possible electrode potential combinations as given
below 1. MT2 positive with respect to MT1, G positive with respect to MT1 2. MT2 positive with
respect to MT1, G negative with respect to MT1 3. MT2 negative with respect to MT1, G negative
with respect to MT1 4. MT2 negative with respect to MT1, G positive with respect to MT1 The
triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However, for
bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used.
Trigger mode 4 is usually averded. Fig. 2 (a) and (b) explain the conduction mechanism of a TRIAC
in trigger modes 1 & 3 respectively.

(a) (b)
Fig. 2 : Conduction mechanism of a TRIAC in trigger modes 1 and 3 (a) Mode 1 , (b) Mode 3 .
In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinary thyristor.
When the gate current has injected sufficient charge into P2 layer the TRIAC starts conducting
through the P1 N1 P2 N2 layers like an ordinary thyristor.
In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number of
electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on
completely.
Steady State Output Characteristics and Ratings of a TRIAC

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 Fig. 3 : Steady state V I characteristics of a TRIAC
From a functional point of view a TRIAC is similar to two thyristors connected in anti parallel.
Therefore, it is expected that the V-I characteristics of TRIAC in the 1st and 3rd quadrant of the V-I
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 3, with no signal
to the gate the TRIAC will block both half cycle of the applied ac voltage provided its peak value is
lower than the break over voltage (VBO) of the device. However, the turning on of the TRIAC can
be controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in
the first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the
thyristor characteristics apply to the TRIAC (ie, latching and holding current). However, in a TRIAC
the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact with each other in the
structure of the TRIAC. Therefore, the voltage, current and frequency ratings of TRIACs are
considerably lower than thyristors. At
present, TRIAC with voltage and
current ratings of 1200V and 300A
(rms) are available. TRIACs also
have a larger on state voltage drop
compared to a thyristor.
Manufacturers usually specify
characteristics curves relating rms
device current and maximum
allowable case temperature as
shown in Fig. 4. Curves relating the
device dissipation and RMS on
state current are also provided for different conduction angles.

Fig. 4 : RMS ON state current Vs maximum case temperature.

UJT:
A unijunction transistor (UJT) is a three-terminal semiconductor switching device. This device has a
unique characteristic that when it is triggered, the emitter current increases re-generatively until it is
limited by emitter power supply. Due to this characteristic, the unijunction transistor can be
employed in a variety of applications e.g., switching, pulse generator, saw-tooth generator etc.
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Construction of UJT:
Fig.1 shows the basic structure of a unijunction transistor. It consists of an n-type silicon bar with an
electrical connection on each end. The leads to these connections are called base leads B1 (base-one)
and B2 (base two). Part way along the bar between the two bases, nearer to B2 than B1, a pn junction
is formed between a p-type emitter and the bar. The lead to this junction is called the emitter lead E.
Fig. 1 (b) shows the symbol of unijunction transistor. Note that emitter is shown closer to B2 than
B1. The following points are worth noting :
(i) Since the device has one pn-junction and three leads, it is commonly called a unijunction
transistor.
(ii) With only one pn-junction, the device is really a form of diode. Because the two base
terminals are taken from one section of the diode, this device is also called double-based
diode.

Fig. 1 (a) (b) (c)

(iii) The emitter is heavily doped having many holes. The n region, however, is lightly doped. For
this reason, the resistance between the base terminals is very high ( 5 to 10 k) when emitter lead is
open.

Fig 2. Basic Circuit Operation of UJT

Fig. 2 shows the basic circuit operation of a unijunction transistor. The device has normally B2
positive w.r.t. B1.
(i) If voltage VBB is applied between B2 and B1 with emitter open [See Fig. 2 (i)], a voltage
gradient is established along the n-type bar. Since the emitter is located nearer to B2,
more than half of VBB appears between the emitter and B1. The voltage V1 between
emitter and B1 establishes reverse bias on the pn junction and the emitter current is cut
off. Of course, a small leakage current flows from B2 to emitter due to minority carriers.

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 (ii) If a positive voltage is applied at the emitter [See Fig. 2 (ii)], the pn junction will remain
reverse biased so long as the input voltage is less than V1. If the input voltage to the
emitter exceeds V1, the pn junction becomes forward biased. Under these conditions,
holes are injected from p-type material into the n-type bar. These holes are repelled by
positive B2 terminal and they are attracted towards B1 terminal of the bar. This
accumulation of holes in the emitter to B1 region results in the decrease of resistance in
this section of the bar. The result is that internal voltage drop from emitter to B1 is
decreased and hence the emitter current IE increases. As more holes are injected, a
condition of saturation will eventually be reached. At this point, the emitter current is
limited by emitter power supply only. The device is now in the ON state. (iii) If a
negative pulse is applied to the emitter, the pn junction is reverse biased and the emitter
current is cut off. The device is then said to be in the OFF state.

Equivalent Circuit of a UJT

Fig. 3 shows the equivalent circuit of a UJT. The resistance of the silicon bar is called the interbase
resistance RBB.

Fig. 3 Equivalent Circuit of UJT

(a) RB2 is the resistance of silicon bar between B2 and the point at which the emitter junction
lies.
(b) RB1 is the resistance of the bar between B1 and emitter junction. This resistance is shown
variable because its value depends upon the bias voltage across the pn junction. The pn
junction is represented in the emitter by a diode D. The circuit action of a UJT can be
explained more clearly from its equivalent circuit.

(i) With no voltage applied to the UJT, the inter-base resistance is given by ;
RBB = RB1 + RB2
The value of RBB generally lies between 4 k and 10 k.
(ii) If a voltage VBB is applied between the bases with emitter open, the voltage will
divide up across RB1 and RB2. Voltage across RB1,

V1 = [RB1 / (RB1 + RB2) ] * VBB

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or V1/VBB = RB1/(RB1+RB2)
The ratio V1/VBB is called intrinsic stand-off ratio and is represented by . value of usually lies
between 0.51 and 0.82.
So Voltage across RB1 = VBB
The voltage VBB appearing across RB1 reverse biases the diode. Therefore, the emitter current is
zero.
(iii) If now a progressively rising positive voltage is applied to the emitter, the diode will
become forward biased when input voltage exceeds VBB by VD, the forward
voltage drop across the silicon diode i.e.
VP = VBB + VD
where VP = peak point voltage
VD = forward voltage drop across silicon diode (j 0.7 V)
When the diode D starts conducting, holes are injected from p-type material to the n-type
bar. These holes are swept down towards the terminal B1. This decreases the
resistance between emitter and B1 (indicated by variable resistance symbol for RB1)
and hence the internal drop from emitter to B1. The emitter current now increases
regeneratively until it is limited by the emitter power supply.
Characteristics of UJT
Fig. 4 shows the curve between emitter
voltage (VE) and emitter current (IE ) of a
UJT at a given voltage VBB between the
bases. This is known as the emitter
characteristic of UJT. The following points
may be noted from the characteristics :
(i) Initially, in the cut-off region, as VE
increases from zero, slight leakage
current flows from terminal B2 to
the emitter. This current is due to the
minority carriers in the reverse
biased diode.

Fig. 4 UJT Characteristics

Above a certain value of VE, forward IE begins to flow, increasing until the peak voltage VP and
current IP are reached at point P.
(ii) After the peak point P, an attempt to increase VE is followed by a sudden increase in emitter
current IE with a corresponding decrease in VE. This is a negative resistance portion of the
curve because with increase in IE, VE decreases. The device, therefore, has a negative
resistance region which is stable enough to be used with a great deal of reliability in many
areas e.g., trigger circuits, sawtooth generators, timing circuits.

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 Fig. 5 UJT Peak and Valley Points

(iii) The negative portion of the curve lasts until the valley point V is reached with valley-point
voltage VV and valley-point current IV. After the valley point, the device is driven to
saturation. Fig. 5 shows the typical family of VE / IE characteristics of a UJT at different
voltages between the bases. It is clear that peak-point voltage (= VBB + VD) falls steadily
with reducing VBB and so does the valley point voltage VV. The difference VP VV is a
measure of the switching efficiency of UJT and can be seen to fall off as VBB decreases. For
a general purpose UJT, the peak - point current is of the order of 1 A at VBB = 20 V with a
valley-point voltage of about 2.5 V at 6 mA
MOSFET :
Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc) have
been the front runners in the quest for an ideal power electronic switch. Ever since the invention of
the transistor, the development of solid-state switches with increased power handling capability has
been of interest for expending the application of these devices. The BJT and the GTO thyristor have
been developed over the past 30 years to serve the need of the power electronic industry. Their
primary advantage over the thyristors have been the superior switching speed and the ability to
interrupt the current without reversal of the device voltage. All bipolar devices, however, suffer from
a common set of disadvantages, namely, (i) limited switching speed due to considerable
redistribution of minority charge carriers associated with every switching operation; (ii) relatively
large control power requirement which complicates the control circuit design. Besides, bipolar
devices can not be paralleled easily.
The reliance of the power electronics industry upon bipolar devices was challenged by the
introduction of a new MOS gate controlled power device technology in the 1980s. The power MOS
field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The new
device promised extremely low input power levels and no inherent limitation to the switching speed.
Thus, it opened up the possibility of increasing the operating frequency in power electronic systems
resulting in reduction in size and weight. The initial claims of infinite current gain for the power
MOSFET were, however, diluted by the need to design the gate drive circuit to account for the pulse
currents required to charge and discharge the high input capacitance of these devices. At high
frequency of operation the required gate drive power becomes substantial. MOSFETs also have
comparatively higher on state resistance per unit area of the device cross section which increases
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with the blocking voltage rating of the device. Consequently, the use of MOSFET has been restricted
to low voltage (less than about 500 volts) applications where the ON state resistance reaches
acceptable values. Inherently fast switching speed of these devices can be effectively utilized to
increase the switching frequency beyond several hundred kHz.
From the point of view of the operating principle a MOSFET is a voltage controlled majority carrier
device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the
voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer
from the bulk semiconductor body. The electric field produced by the gate voltage modulate the
conductivity of the semiconductor material in the region between the main current carrying terminals
called the Drain (D) and the Source (S). Power MOSFETs, just like their integrated circuit
counterpart, can be of two types (i) depletion type and (ii) enhancement type. Both of these can be
either n- channel type or p-channel type depending on the nature of the bulk semiconductor. Fig 1 (a)
shows the circuit symbol of these four types of MOSFETs along with their drain current vs gate-
source voltage characteristics (transfer characteristics).

Fig 1: Different types of power MOSFET ( Circuit symbols and transfer characteristics)
From Fig 1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e,
with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient
in many power electronic applications. Therefore, the enhancement type MOSFETs (particularly of
the n-channel variety) is more popular for power electronics applications. This is the type of
MOSFET which will be discussed in this lesson. Fig 1 (b) shows the photograph of some
commercially available n-channel enhancement type Power MOSFETs.
Constructional Features of a Power MOSFET
As mentioned in the introduction section, Power MOSFET is a device that evolved from MOS
integrated circuit technology. The first attempts to develop high voltage MOSFETs were by
redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology
was called lateral double deffused MOS (DMOS). However it was soon realized that
much larger breakdown voltage and current ratings could be achieved by resorting to a vertically
oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually all
16 | P a g e
manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has vertically
oriented three layer structure of alternating p type and n type semiconductors as shown in Fig 2 (a)
which is the schematic representation of a single MOSFET cell structure. A large number of such
cells are connected in parallel (as shown in Fig 2 (b)) to form a complete device.

Fig. 2: Schematic construction of a power MOSFET (a) Construction of a single cell. (b)
Arrangement of cells in a device.
The two n+ end layers labeled Source and Drain are heavily doped to approximately the same
level. The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3
orders of magnitude lower than n+ regions on both sides). The n- drain drift region has the lowest
doping density. Thickness of this region determines the breakdown voltage of the device. The gate
terminal is placed over the n- and p type regions of the cell structure and is insulated from the
semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the
drain region of all cells on a wafer are connected to the same metallic contacts to form the Source
and the Drain terminals of the complete device. Similarly all gate terminals are also connected
together. The source is constructed of many (thousands) small polygon shaped areas that are
surrounded by the gate regions. The geometric shape of the source regions, to same extent, influences
the ON state resistance of the MOSFET.

Fig. 3: Parasitic BJT in a MOSFET cell.

17 | P a g e
 n + n + n + n- D Body spreading resistance Parasitic BJT S G p One interesting feature of the
MOSFET cell is that the alternating n+ n- p n+ structure embeds a parasitic BJT (with its base and
emitter shorted by the source metallization) into each MOSFET cell as shown in Fig 3. The nonzero
resistance between the base and the emitter of the parasitic npn BJT arises due to the body spreading
resistance of the p type substrate. In the design of the MOSFET cells special care is taken so that this
resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective
short circuit between the body and the source the BJT always remain in cut off and its collector-base
junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a
Power MOSFET
Operating principle of a MOSFET
At first glance it would appear that there is no path for any current to flow between the source and
the drain terminals since at least one of the p n junctions (source body and body-Drain) will be
reverse biased for either polarity of the applied voltage between the source and the drain. There is no
possibility of current injection from the gate terminal either since the gate oxide is a very good
insulator. However,
application of a positive voltage at the gate terminal with respect to the source will covert the silicon
surface beneath the gate oxide into an n type layer or channel, thus connecting the Source to the
Drain as explained next.
The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide
layer and the p-body silicon forms a high quality capacitor. When a small voltage is application to
this capacitor structure with gate terminal positive with respect to the source (note that body and
source are shorted) a depletion region forms at the interface between the SiO2 and the silicon as
shown in Fig 4 (a).

18 | P a g e
Fig. 4: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron
accumulation; (c) Formation of inversion layer.
The positive charge induced on the gate metallization repels the majority hole carriers from the
interface region between the gate oxide and the p type body. This exposes the negatively charged
acceptors and a depletion region is created. Further increase in VGS causes the depletion layer to
grow in thickness. At the same time the electric field at the oxide-silicon interface gets larger and
begins to attract free electrons as shown in Fig 4 (b). The immediate source of electron is electron-
hole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of
the depletion region. The extra holes are neutralized by electrons from the source. As VGS increases
further the density of free electrons at the interface becomes equal to the free hole density in the bulk
of the body region beyond the depletion layer. The layer of free electrons at the interface is called the
inversion layer and is shown in Fig 4 (c). The inversion layer has all the properties of an n type
semiconductor and is a conductive path or channel between the drain and the source which permits
flow of current between the drain and the source. Since current conduction in this device takes place
through an n- type channel created by the electric field due to gate source voltage it is called
Enhancement type n-channel MOSFET. The value of VGS at which the inversion layer is
considered to have formed is called the Gate Source threshold voltage VGS (th). As VGS is
increased beyond VGS(th) the inversion layer gets some what thicker and more conductive, since the
density of free electrons increases further with increase in VGS. The inversion layer screens the
depletion layer adjacent to it from increasing VGS. The depletion layer thickness now remains
constant.
Steady state output i-v characteristics of a MOSFET
The MOSFET, like the BJT is a three terminal device where the voltage on the gate terminal controls
the flow of current between the output terminals, Source and Drain. The source terminal is common
between the input and the output of a MOSFET. The output characteristics of a MOSFET is then a
plot of drain current (iD) as a function of the Drain Source voltage (vDS) with gate source voltage
(vGS) as a parameter. Fig 5 (a) shows such a characteristics

19 | P a g e
Fig. 5: Output i-v characteristics of a Power MOSFET (a) i-v characteristics; (b) Components of ON-
state resistance; (c) Electron drift velocity vs Electric field; (d) Transfer
With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET operates in the
cut-off mode. No drain current flows in this mode and the applied drain source voltage (vDS) is
supported by the body-collector p-n junction. Therefore, the maximum applied voltage should be
below the avalanche break down voltage of this junction (VDSS) to avoid destruction of the device.
When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS (vDS
< (vGS vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation is called
ohmic mode of operation. In power electronic applications a MOSFET is operated either in the cut
off or in the ohmic mode. The slope of the vDS iD characteristics in this mode is called the ON
state resistance of the MOSFET (rDS (ON)). Several physical resistances as shown in Fig 5 (b)
contribute to rDS (ON). Note that rDS (ON) reduces with increase in vGS. This is mainly due to
reduction of the channel resistance at higher value of
VGS. Hence, it is desirable in power electronic applications, to use as large a gate-source voltage as
possible subject to the dielectric break down limit of the gate-oxide layer. At still higher value of
vDS (vDS > (vGS vGS (th)) the iD vDS characteristics deviates from the linear relationship of
the ohmic region and for a given vGS, iD tends to saturate with increase in vDS. The exact
mechanism behind this is rather complex. It will suffice to state that, at higher drain current the
voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer
end. In addition, at large value of the electric field, produced by the large Drain Source voltage, the
drift velocity of free electrons in the channel tends to saturate as shown in Fig 5 (c). As a result the
drain current becomes independent of VDS and determined solely by the gate source voltage vGS.
This is the active mode of operation of a MOSFET. Simple, first order theory predicts that in the
active region the drain current is given approximately by
20 | P a g e
iD= K(VGS - VGS (th))2 ----------- (1)
Where K is a constant determined by the device geometry.
At the boundary between the ohmic and the active region
VDS = VGS - VGS (th) ------------- (2)
Therefore,
ID = K (VDS )2 ---------------(3)
Equation (3) is shown by a dotted line in Fig 5 (a). The relationship of Equation (1) applies
reasonably well to logic level MOSFETs. However, for power MOSFETs the transfer characteristics
(iD vs vGS) is more linear as shown in Fig 5 (d).
At this point the similarity of the output characteristics of a MOSFET with that of a BJT should be
apparent. Both of them have three distinct modes of operation, namely, (i)cut off, (ii) active and (iii)
ohmic (saturation for BJT) modes. However, there are some important differences as well.
Unlike BJT a power MOSFET does not undergo second break down.
The primary break down voltage of a MOSFET remains same in the cut off and in the active
modes. This should be contrasted with three different break down voltages (VSUS, VCEO & VCBO)
of a BJT.
The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient
which allows paralleling of MOSFET without any special arrangement for current sharing. On the
other hand, vCE (sat) of a BJT has negative temperature coefficient making parallel connection of
BJTs more complicated.
As in the case of a BJT the operating limits of a MOSFET are compactly represented in a Safe
Operating Area (SOA) diagram as shown in Fig 6. As in the case of the FBSOA of a Version 2 EE
IIT, Kharagpur 12 BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is
restricted by the absolute maximum permissible value of the drain current (IDM) which should not
be exceeded even under pulsed operating condition. To the left, operating restriction arise due to the
non zero value of rDS(ON) corresponding to vGS = vGS(Max). To the right, the first operating
restriction is due to the limit on the maximum permissible junction temperature rise which depends
on the power dissipation inside the MOSFET. This limit is different for DC (continuous) and pulsed
operation of different pulse widths. As in the case of a BJT the pulsed safe operating areas are useful
for shaping the switching trajectory of a MOSFET. A MOSFET does not undergo second break
down and no corresponding operating limit appears on the SOA. The final operation limit to the
extreme right of the SOA arises due to the maximum permissible drain source voltage (VDSS) which
is decided by the avalanche break down voltage of the drain -body p-n junction. This is an
instantaneous limit. There is no distinction between the forward biased and the reverse biased SOAs
for the MOSFET. They are identical.

21 | P a g e
Due to the presence of the anti parallel body diode, a MOSFET can not block any reverse voltage.
The body diode, however, can carry an RMS current equal to IDM. It also has a substantial surge
current carrying capacity. When reverse biased it can block a voltage equal to VDSS.
For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS (Max)) must
be observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide
layer and permanent failure of the device. It should be noted that even static charge inadvertently put
on the gate oxide by careless handling may destroy it. The device user should ground himself before
handling any MOSFET to avoid any static charge related problem.

CHARACTERISTICS OF POWER ELECTRONICS DEVICES

Experiment 1

Characteristics of DIAC
Aim:

To draw the V-I characteristics of DIAC and obtain the break over voltage (VBO)

Theory:

A DIAC is a two terminal three layer bidirectional device which can be switched from its off state to
on state for either polarity of applied voltage. The operation of DIAC is identical both in forward and

22 | P a g e
reverse conduction. The DIAC does not conduct until the applied voltage of either
polarity reaches the break over voltage VBO.
Procedure to plot VI Characteristics of DIAC:
1. Forward Direction of DIAC

1. Make connections as
shown in the figure.
Connect voltmeter and
Ammeter also. ( i.e.
DIAC is connected in
forward direction).

The input supply is increased in step

by step.
The corresponding ammeter and
voltmeter readings are noted and
tabulated.
The Breakdown of DIAC occurs at
30V. (Practically between 29 to 35
V).
After Break down the voltage drops to
20V. (Practically between 20-25 V).

2. Reverse Direction of DIAC

For the reverse direction connect the circuit as the circuit shown below and repeat the above
procedure.

23 | P a g e
 Observation Table:

VI Characteristics Graph:

Results: The VI characteristics of

DIAC has been plotted.

Experiment 2
Characteristics of UJT
AIM: To Plot and study the characteristics of UJT.
PROCEDURE:
1. Make connections as shown in the figure. Connect voltmeter and Ammeter also

24 | P a g e
2. Set VB1B2 = 0V, vary VEB1, & note down the readings of IE & VEB1
3. Set VB1B2 = 5V (+5 Fixed power supply can be used ) , vary VEB1 , & note down the readings of
IE & VEB1
4. Plot the graph : IE Versus VEB1 for constant VB1B2.
5. Repeat the procedure for different voltage.

Observation Table:
(I) Vb2 b1 = ___________

SN Veb Ie

(II) Vb2 b1 = ___________

SN Veb Ie

25 | P a g e
VI Characteristics plot:

RESULT: The characteristics of given UJT was Plotted.

SCR Characteristics

AIM: To study the SCR Characteristics

Procedure:
1. Make connections as shown in the figure. Connect voltmeter and Ammeter also

2. Adjust the value of Ig to zero or some minimum value.

3. By varying the voltage Vak from 0 to 10 volts with a step of 2 volts, note down
corresponding values of Ia
4. Now apply the gate voltage gradually, until SCR fires, then note down the values of Ig
and also the values of Ia and Vak
26 | P a g e
 5. Increase Vaa to some value and note down Ia and Vak

6. Reduce gate voltage to zero, observe ammeter reading by reducing Vaa which gives
the values of Ih (holding current) at the point at which, current suddenly drops to zero
7. Repeat the steps 2, 3, 4, 5 & 6 for different values of break over voltage

8. Plot a graph of Vak v/s Ia

Observation Table:
(I) Ig = ______

SN Iak Vak

(II) Ig = ______

SN Iak Vak

27 | P a g e
VI Characteristics Plot:

Result: The VI Characteristics of SCR has been Plotted.

Experiment 4
Characteristics of TRIAC
Aim:
To draw the V-I characteristics of TRIAC and obtain the breakover voltage (VBO).
Procedure :
Forward Direction

1. Make connection as shown in the figure.

28 | P a g e
 2. Adjust the value of Ig to zero or some minimum value

3. By varying the voltage Vmt2mt1 from 0 to 10 volts with a step of 2 volts,

note down corresponding values of I1

4. Now apply the gate voltage gradually, until TRIAC fires, then note down the
values of Ig and also the values of I1 and Vmt2mt1.

5. Increase Vm to some value and note down I1 and Vmt2mt1.

6. Reduce gate voltage to zero, observe ammeter reading by reducing Vm

which gives the values of Ih (holding current) at the point at which, current
suddenly drops to zero

7. Repeat the steps 2, 3, 4, 5 & 6 for different values of break over voltages

8. Plot a graph of Vmt1mt2 v/s I1

9. Repeat the steps 1, 2, 3, 4, 5, 6 & 7 for different modes .

Reverse Direction :

29 | P a g e
Procedure:
1. Connections are made as shown in the circuit diagram
2. Repeat the forward direction procedure for the readings.

Observation Table:
1. Forward direction:
(A) Ig = _________

SN Vak Iak

(B) Ig = _________

SN Vak Iak

Reverse Direction

(A) Ig = _________

SN Vak Iak

30 | P a g e
(B) Ig = _________

SN Vak Iak

VI Characteristics Plot:

Result : VI Characteristics of TRIAC has been plotted.

Experiment 3
MOSFET CHARACTERISTICS
AIM : To study the VI Characteristics of MOSFET.

Procedure:

Transconductance Characteristics :

31 | P a g e
 1. Make Connections as shown in the figure.

2. Initially keep V1 and V2 zero.

3. Set VDS = say 1 V

4. Slowly vary V2 (VGE) with a step of 0.5 volts, note down corresponding ID and VDS
readings for every 0.5v and are tabulated in the tabular column

5. Repeat the experiment for different values of VDS & draw the graph of ID v/s VGS

6. Plot the graph of VGS v/s ID

Observation Table:
(I) VDS = _______

SN VGS ID

(I) VDS = _______

SN VGS ID

32 | P a g e
Plot:

Drain Characteristics
1. Connections are made as shown in the circuit diagram.

2. Adjust the value of VGS slightly more than threshold voltage Vth

3. By varying V1, note down ID & VDS and are tabulated in the tabular column

4. Repeat the experiment for different values of VGS and note down ID v/s VDS

5. Draw the graph of ID v/s VDS for different values of VGS.

Observation Table:
(I) VGS = _______

SN VDS ID

(II) VGS = _______

SN VDS ID

33 | P a g e
Plot:

Result : The VI Characteristics of MOSFET has been plotted.

UJT relaxation oscillator

AIM : To Study the UJT relaxation oscillator.

Theory:

34 | P a g e
 (i) UJT Relaxation Oscillator

(ii) Output Wave Forms

Fig. shows UJT relaxation oscillator where the discharging of a capacitor through UJT can
develop a saw-tooth output as shown. When battery VBB is turned on, the capacitor C charges
through resistor R1. During the charging period, the voltage across the capacitor rises in an
exponential manner until it reaches the peak - point voltage. At this instant of time, the UJT
switches to its low resistance conducting mode and the capacitor is discharged between E and
B1. As the capacitor voltage flys back to zero, the emitter ceases to conduct and the UJT is
switched off. The next cycle then begins, allowing the capacitor C to charge again. The
frequency of the output saw-tooth wave can be varied by changing the value of R1 since this
controls the time constant R1C of the capacitor charging circuit. The time period and hence the
frequency of the saw-tooth wave can be calculated as follows. Assuming that the capacitor is
initially uncharged, the voltage VC across the capacitor prior to breakdown is given by :
VC = VBB (1 e t/R1*C )
where R1*C = charging time constant of resistor-capacitor circuit
t = time from the commencement of waveform.
The discharge of the capacitor occurs when VC is equal to the peak-point voltage VBB i.e.
VBB = VBB (1 e t/R1*C )
or = (1 e t/R1*C )
or (e t/R1*C ) = 1
or t = R1 * C loge (1 / 1 )

35 | P a g e
 Time period, t = 2.3 R1* C log10 (1 / 1 )
So the frequency of saw-tooth wave, f = ( 1 / t )Hz
Procedure:
1. Connect the circuit as circuit given below.
2. Observe the oscillator and capacitor discharge waveform on CRO.

SCR R & RC TRIGGERING

Resistance Firing Circuit

The circuit below shows the resistance triggering of SCR where it is employed to drive the
load from the input AC supply. Resistance and diode combination circuit acts as a gate
control circuitry to switch the SCR in the desired condition.
As the positive voltage applied, the SCR is forward biased and doesnt conduct until its
gate current is more than minimum gate current of the SCR.
When the gate current is applied by varying the resistance R2 such that the gate current
should be more than the minimum value of gate current, the SCR is turned ON. And hence
the load current starts flowing through the SCR.
The SCR remains ON until the anode current is equal to the holding current of the SCR.
And it will switch OFF when the voltage applied is zero. So the load current is zero as the
SCR acts as open switch.
The diode
protects the
gate drive
circuit from
reverse gate
voltage
during the
negative half
cycle of the
input. And
Resistance
R1 limits the

36 | P a g e
 current flowing through the gate terminal and its value is such that the gate current should
not exceed the maximum gate current.
It is the simplest and economical type of triggering but limited for few applications due to
its disadvantages.
In this, the triggering angle is limited to 90 degrees only. Because the applied voltage is
maximum at 90 degrees so the gate current has to reach minimum gate current value
somewhere between zero to 90 degrees.

Resistance Capacitacne (RC) Firing Circuit

The limitation of resistance firing circuit can be overcome by the RC triggering circuit
which provides the firing angle control from 0 to 180 degrees. By changing the phase and
amplitude of the gate current, a large variation of firing angle is obtained using this circuit.
Below figure shows the RC triggering circuit consisting of two diodes with an RC network
connected to turn the SCR.
By varying the variable resistance, triggering or firing angle is controlled in a full positive
half cycle of the input signal.
During the negative half cycle of the input signal, capacitor charges with lower plate
positive through diode D2 up to the maximum supply voltage Vmax. This voltage remains
at -Vmax across the capacitor till supply voltage attains zero crossing.
During the positive half cycle of the input, the SCR becomes forward biased and the
capacitor starts charging through variable resistance to the triggering voltage value of the
SCR.
When the capacitor charging voltage is equal to the gate trigger voltage, SCR is turned ON
and the capacitor holds a small voltage. Therefore the capacitor voltage is helpful for
triggering the SCR even after 90 degrees of the input waveform.
In this, diode D1 prevents the negative voltage between the gate and cathode during the
negative half cycle of the input through diode D2.
PROCEDURE
RESISTANCE TRIGGERING:
1. Connect the circuit as the circuit shown below.

2. Rotate the potentiometer.

3. When the gate signal reaches to the threshold value the scr turns on.
4. The effect is seen on the bulb.

37 | P a g e
RESISTANCE- CAPACITANCE TRIGGERING:
1. Connect the circuit as shown in above figure.
2. Only use capacitor on place of Resistors only.
3. Rotate the potentiometer.
4. When the gate signal reaches to the threshold value the scr turns on.
5. The effect is seen on the bulb.

Conditions to turn OFF the conducting SCR

The anode / forward current of SCR must be reduced to zero or below the level of holding
current &
A sufficient reverse voltage must be applied across the SCR to regain its forward blocking
state.

When the SCR is turned OFF by reducing forward current to zero. There exist excess charge
carriers in different layers. To regain the forward blocking state of an SCR, these excess carriers
must be recombined. Therefore, this recombination process is accelerated by applying a reverse
voltage across the SCR.

SCR Turn OFF Methods

The reverse voltage which causes to commutate the SCR is called commutation voltage.

The commutation methods are classified into two major types.

1. Natural commutation (Source/ line or class F commutation)
2. Forced commutation

1. Natural commutation.
This type of commutation occurs when the power source is an AC voltage source.
In natural commutation, the source of commutation voltage is the supply source itself. If the SCR
is connected to an AC supply, at every end of the positive half cycle the anode current goes
through the natural current zero and also immediately a reverse voltage is applied across the
SCR. These are the conditions to turn OFF the SCR.
This commutation is possible with line commutated inverters, controlled rectifiers, cyclo
converters and AC voltage regulators because the supply is the AC source in all these converters.

38 | P a g e
 2. Forced Commutation

In case of DC circuits, there is no natural current zero to turn OFF the SCR. In such circuits,
forward current must be forced to zero with an external circuit to commutate the SCR
hence named as forced commutation. This commutation is mainly used in chopper and
inverter circuits.
This commutating circuit consist of components like inductors and capacitors called as
commutating components. These commutating components cause to apply a reverse
voltage across the SCR that immediately bring the current in the SCR to zero.

Forced commutation is classified into different types

class A, B, C, D, and E.

Class A
Class A Commutation

This is also known as self commutation, or resonant commutation, or load commutation. In this
commutation, the source of commutation voltage is in the load. This load must be an under
damped R-L-C supplied with a DC supply so that natural zero is obtained.
The commutating components L and C are connected either parallel or series with the load
resistance R as shown below with waveforms of SCR current, voltage and capacitor voltage.

39 | P a g e
The value of load resistance and commutating components are so selected that they forms a
under damped resonant circuit to produce natural zero. When the thyristor or SCR is triggered,
the forward currents starts flowing through it and during this the capacitor is charged up to the
value of E.

Once the capacitor is fully charged (more than the supply source voltage) the SCR becomes
reverse biased and hence the commutation of the device. The capacitor discharges through the
load resistance to make ready the circuit for the next cycle of operation. The time for switching
OFF the SCR depends on the resonant frequency which further depends on the L and C
components.

Class B Commutation

This is also a self commutation circuit in which commutation of SCR is achieved automatically
by L and C components, once the SCR is turned ON. In this, the LC resonant circuit is connected
across the SCR but not in series with load as in case of class A commutation and hence the L and
C components do not carry the load current.

When the DC supply is applied to the circuit, the capacitor charges with an upper plate positive
and lower plate negative up to the supply voltage E. When the SCR is triggered, the current
flows in two directions, one is through E+ SCR R E- and another one is the commutating
current through L and C components.

Once the SCR is turned ON, the capacitor is starts discharging through C+ L T C-. When
the capacitor is fully discharged, it starts charging with a reverse polarity. Hence a reverse
voltage applied across the SCR which causes the commutating current IC to oppose load current
IL.
When the commutating current Ic is higher than the load current, the SCR will automatically turn
OFF and the capacitor charges with original polarity.

40 | P a g e
In the above process, the SCR is turned ON for some time and then automatically turned OFF for
some time. This is a continuous process and the desired frequency of ON/OFF depends on the
values of L and C. This type of commutation is mostly used in chopper circuits.

Class C Commutation

In this commutation method, the main SCR is to be commutated is connected in series with the
load and an additional or complementary SCR is connected in parallel with main SCR. This
method is also called as complementary commutation.
In this , SCR turns OFF with a reverse voltage of a charged capacitor. The figure below shows
the complementary commutation with appropriate waveforms.

Initially, both SCRs are in OFF state so the capacitor voltage is also zero. When the SCR1 or
main SCR is triggered, current starts flowing in two directions, one path is E+ R1 SCR1 E-
and another path is the charging current E+ R2- C+ C- SCR1 E- . Therefore, the capacitor
starts charging up to the value of E.

When the SCR2 is triggered, SCR is turned ON and simultaneously a negative polarity is applied
across the SCR1. So this reverse voltage across the SCR1 immediately causes to turn OFF the
SCR1. Now the capacitor starts charging with a reverse polarity through the path of E+ R1- C+
C- SCR2 E-. And again, if the SCR 1 is triggered, discharging current of the capacitor turns
OFF the SCR2.

This commutation is mainly used in single phase inverters with a centre tapped transformers. The
Mc Murray Bedford inverter is the best example of this commutation circuit. This is a very
reliable method of commutation and it is also useful even at frequencies below 1000Hz.

41 | P a g e
Class D Commutation

This is also called as auxiliary commutation because it uses an auxiliary SCR to switch the
charged capacitor. In this, the main SCR is commutated by the auxiliary SCR. The main SCR
with load resistance forms the power circuit while the diode D, inductor L and SCR2 forms the
commutation circuit.

When the supply voltage E is applied, both SCRs are in OFF state and hence the capacitor
voltage is zero. In order to charge the capacitor, SCR2 must be triggered first. So the capacitor
charges through the path E+ C+ C- SCR2- R- E-.

When the capacitor is fully charged the SCR2 becomes turned OFF because no current flow
through the SCR2 when capacitor is charged fully. If the SCR1 is triggered, the current flows in
two directions; one is the load current path E+ SCR1- R- E- and another one is commutation
current path C+ SCR1- L- D- C.

As soon as the capacitor completely discharges, its polarities will be reversed but due to the
presence of diode the reverse discharge is not possible. When the SCR2 is triggered capacitor
starts discharging through C+ SCR2- SCR1- C-. When this discharging current is more than
the load current the SCR1 becomes turned OFF.

Again, the capacitor starts charging through the SCR2 to a supply voltage E and then the SCR2
is turned OFF. Therefore, both SCRs are turned OFF and the above cyclic process is repeated.
This commutation method is mainly used in inverters and also used in the Jones chopper circuit.

42 | P a g e
Class E Commutation

This is also known as external pulse commutation. In this, an external pulse source is used to
produce the reverse voltage across the SCR. The circuit below shows the class E commutation
circuit which uses a pulse transformer to produce the commutating pulse and is designed with
tight coupling between the primary and secondary with a small air gap.

If the SCR need to be commutated, pulse duration equal to the turn OFF time of the SCR is
applied. When the SCR is triggered, load current flows through the pulse transformer. If the
pulse is applied to the primary of the pulse transformer, an emf or voltage is induced in the
secondary of the pulse transformer.
This induced voltage is applied across the SCR as a reverse polarity and hence the SCR is turned
OFF. The capacitor offers a very low or zero impedance to the high frequency pulse.

EXPERIMENT 7
1. CLASS A Commutation
AIM: To Study the Class A commutation of SCR
Procedure:
1. Connect the Circuit as shown in figure below.

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 2. Turn on the supply.
3. Now apply the 5 V to the SCR Gate (SCR Turns on)
4. When the gate signal is removed, due to commutation cicuiitrary the SCR Turns off.

2. CLASS B Commutation

AIM : To Study the Class A commutation of SCR

Procedure:
1. Connect the Circuit as Circuit below.

2. Turn on the supply.

3. Now apply the 5 V to the SCR Gate (SCR Turns on)
4. When the gate signal is removed, due to commutation cicuiitrary the SCR Turns off.
Exp 04 : Temperature Control Using Comparator and MOSFET
Aim: To control the speed of a fan using Thermistor.
Apparatus required
Power Electronics trainer kit
Patch cards
Power supply
100W Bulb

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Theory:
The LM741 series are general purpose operational amplifiers. It is intended for a wide range
of analog applications. The high gain and wide range of operating voltage provide superior
performance in integrator, summing amplifier, and general feedback applications.

Fig. 15 Pin diagram of LM741

The circuit shown in Fig.15 exploits the property of Thermistor to operate the DC Fan.
Thermistor is a kind of temperature dependent resistor and its resistance varies depending on the
temperature in its vicinity. There are two types of Thermistors- NTC and PTC.

Negative temperature coefficient (NTC) Thermistor decreases its resistance when the
temperature increases while Positive temperature coefficient (PTC) increases its resistance when
the temperature increases. Thermistors are bead like resistors available from 100 ohms to 10K or
more values. Here a 4.7K NTC Thermistor is used. IC uA 741 is used as a voltage comparator to
switch on the DC fan. Its INV input (pin2) gets an adjustable voltage through VR while its Non-
INV (pin3) input gets voltage through a potential divider comprising R1 and the Thermistor.
Thus the voltage at pin3 depends on the conductivity of the Thermistor.

When the temperature is normal, pin3 gets higher voltage than pin2 and makes the output of IC.
This high output keeps transistor off since its base is positive. DC fan remains off in this
condition. When the temperature increases above the value set by VR, resistance of Thermistor
decreases and the voltage at pin3 decreases. As a result, output of IC becomes low to switch on
transistor. A small brush less DC fan turns on by the transistor. When the temperature returns
normal, Fan automatically turns off. Diode 1N4007 is necessary to remove back EMF when
transistor turns off.

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 Fig. 16 Temperature controlled DC fan
Procedure:
1. Connect the circuit as shown in fig.16.

2. Turn on 12v dc supply.

3. Now increase the temperature of the Thermistor.
4. After a specified increase in the temperature the fan will turn on.
5. The temperature limit can be adjusted by potentiometer P1.
6. To heat up thermistor you can use your fingers or your mobile touch light.
Result: The DC fan is controlled by thermistor.
Exp 05: DC fan Speed Control Using PWM and MOSFET
Aim : To control the speed of DC fan using PWM and Mosfet.
Apparatus required
Power Electronics trainer kit
Patch cards

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 Power supply
100W Bulb
Theory:
Fig. 17 is showing a circuit by which we can control the speed of a DC fan using PWM and
Mosfet. PWM is generated by IC ne555 to on the Mosfet.

Fig. 17 Controlling of DC fan using PWM and Mosfet.

NE555 is wired as an astable multivibrator whose duty cycle can be adjusted by varying the
POT R1. The output of IC1 is coupled to the base of transistor Q1 which drives the motor
according to the PWM signal available at its base. Higher the duty cycle the average voltage
across motor will be high which results in higher motor speed and vice versa.

Fig. 18 Pin diagram of ne555

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PIN DESCRIPTION PURPOSE

1 Ground DC Ground

The trigger pin triggers the beginning of the timing sequence. When it goes
2 Trigger LOW, it causes the output pin to go HIGH. The trigger is activated when the
voltage falls below 1/3 of +V on pin 8.

The output pin is used to drive external circuitry. It has a "totem pole"
configuration, which means that it can source or sink current. The HIGH
output is usually about 1.7 volts lower than +V when sourcing current. The
3 Output
output pin can sink up to 200mA of current. The output pin is driven HIGH
when the trigger pin is taken LOW. The output pin is driven LOW when the
threshold pin is taken HIGH, or the reset pin is taken LOW.

The reset pin is used to drive the output LOW, regardless of the state of the
4 Reset
circuit. When not used, the reset pin should be tied to +V.

The control voltage pin allows the input of external voltages to affect the
5 Control Voltage timing of the 555 chip. When not used, it should be bypassed to ground
through an 0.01uF capacitor.

The threshold pin causes the output to be driven LOW when its voltage rises
6 Threshold
above 2/3 of +V.

The discharge pin shorts to ground when the output pin goes HIGH. This is
7 Discharge
normally used to discharge the timing capacitor during oscillation.

8 +V DC Power - Apply +3 to +18VDC here.

Procedure:
1. Connect the circuit as shown in fig.

2. Power on the 12v dc supply.

3. Adjust the potentiometer R1 value.
4. At a particular value the motor will start rotating.

Result: Speed Control of DC motor is done using 555 timer and Mosfet.

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 MOSFET and SCR AS A SWITCH
AIM : : To use MOSFET and SCR as a SWITCH
Theory:

Opto-Coupler:

Opto-isolators or Opto-couplers, are made up of a light emitting device, and a light sensitive
device, all wrapped up in one package, but with no electrical connection between the two, just a
beam of light. The light emitter is nearly always an LED. The light sensitive device may be a
photodiode, phototransistor, or more esoteric devices such as thyristors, TRIACs etc.

Working :

CASE 1 : When output is taken from

Collector (Pin 5).

(A). When a high logic is applied to

Optocoupler.

Observe given circuit, a High

logic on the opto-coupler.

Current from the source signal

passes through the input LED
which emits an infra-red light
whose intensity is proportional
to the electrical signal
This emitted light falls upon
the base of the photo-
transistor, causing it to switch-
ON and conduct in a similar
way to a normal bipolar transistor.

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B) When a Low Logic is applied to opto-coupler.
Observe the given circuit
carefully.
When the current flowing through
the LED is interrupted, i.e. a low
logic is applied ; the infra-red
emitted light is cut-off, causing the
photo-transistor to cease conducting.
In this case 12V appears at the
output side.
Which turns on the MOSFET.

CASE : 2 When Output is taken from Emitter (Pin 4)

(A) When a Low logic is applied to

Optocoupler.

In this case at the emitter 0V

appears.
i.e. no Gate signal appers.
MOSFET will be turn off.

(B) When a High logic is applied to Opto-coupler.

The photo-transistor can be used to switch

current in the output circuit.
12V appears at output side.
Which turns on the MOSFET.

(Note: Follow these cases for the SCR and see the
results
In case 1 if we use gate signal for the SCR, the SCR will remain in on state. But in case-2 when
first the SCR will be in off state then it will be in on state in condition (B). This shows that once
the SCR turn on it will be in on state until a reverse voltage is not applied to the SCR)

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