4_CMOS IC Fabrication

Process
 outlines
• Basic IC fabrication steps
• CMOS process steps
• Design rules
 Wafer, Die, and IC
• Yield
• Defect density
 目前技術的發展
300 mm
12-Inch
200 mm
8-Inch

150 mm
晶圓 6-Inch
Wafer

和 0.18µm 製程比較
0.13µm 製程的裸晶大小約縮小 60%以上
性能提昇約 70%
90-nm製程將製作在 300mm 的晶圓上

NEC 已設計出 65-nm製程所需要之

low-k薄膜技術
 晶片的大小
• 晶圓的照片（Wafer photo）
Single
die

Wafer

From http://www.amd.com 已提昇至 12” (30cm)

 晶片的大小
• 原子的大小: 幾Å左右
– 需要幾個原子形成一個元件
• 似乎會在100 Å 或 0.01 µm達到極限
– 約為30個矽原子的大小
– 重要的考量
• 效能與成本
 Cross section

SiO2 metal3

metal2

transistor metal1
via

poly
n+ n+
p+
substrate
substrate
 Material growth and deposition
• Oxidation
• Diffusion/ion implantation
• Polycrystal silicon
• Isolation
• Metal layers and contacts
 Silicon Dioxide (SiO2)
• Thin oxide, using dry oxidation
– Material under the gate terminal of MOS
• Thick oxide (field oxide), using wet oxidation
– Isolation between MOS
• CVD (chemical vapor deposition) oxide
– Isolation between layers
 Doped Silicon Layers
• Diffusion of n (or p) type impurity into Si
• Ion implantation of impurity
• Form the wells in substrate
• Form the drain/source terminal of MOS
 Polysilicon
• Form gate terminal of MOS
• Originally metal gate
– Metal Oxide Semiconductor (MOS)
• Polysilicon gate
• Silicide
– poly coated with a thin-layer of refractory
metal to reduce sheet resistance
• Can also be used in stacked capacitor for
RAM process (TSMC 0.35um 2P3M)
 Metal
• Aluminum (Al)
– Material or metal
layers
– Suffers
electromigration
• Copper
– Half resistance of Al
– Much harder
process
Chemical-mechanical polishing (CMP)
• Produce planar surface using a combination
of chemical etching and mechanical
“sanding”
• Metal deposition steps in multi-layer metal
process
Lithography (patterning)
 Well formation
• Twin-well process

First place tubs to provide properly-doped

substrate for n-type, p-type transistors:
p-tub n-tub

substrate
 Poly deposition
• Thin oxide (gate oxide) before poly

Pattern polysilicon before diffusion

regions:
poly gate oxide poly

p-tub n-tub
 Diffusion (ion implantation)
• Self-align process

Add diffusions, performing self-masking:

poly poly

n+ p-tub n+ p+ n-tub p+
 Metal layers and contact cuts
• Contact cuts for interconnections

Start adding metal layers:

metal 1 metal 1

poly vias poly

n+ p-tub n+ p+ n-tub p+
 nMOS Transistor layout
• Length (poly width) and width (diffusion
width) of MOSFET

n-type (tubs may vary):

w
CMOS Process I (active area)
CMOS process II (field oxide)
CMOS process III (MOS)
CMOS process IV (metal layer)
Bonding pad
P-well CMOS: well, TOX, Poly
p-well CMOS: diff, cut, metal
 Lightly doped drain (LDD)
• Reduce hot-electron effects in short-
channel devices
• Transparent to layout designers
 Silicide
• Even heavily doped polysilicon has large
sheet resistance (about 25 ohm)
• Add refactory metal to reduce the sheet
resistance to about 10m ohm
 Copper patterning
• Half resistance of Al
• Hard to etch
• Diffuse rapidly through Si
• Damascene process
 Dual-Damascene for Cu
• Create via using Cu
• Thin barrier layers are required to contain Cu
 Design rules
• Minimum dimension, line spacing,
overlapping, extension of different patterns
• Micron rules
– Unit of micron meters
– Technology dependent (non-scalable)
• Lambda rules
– Unit of lambda
– Technology independent (scalable)
Design rules
 MOSIS scalable lambda rules
• Designed to scale across a wide range of
technologies
• Designed for educational use
• fairly conservative
λ is the size of a minimum feature.
• Specifying λ particularizes the scalable
rules.
• Parasitics are generally not specified in
λ units.
 wires

6 metal 3

3 metal 2

3 metal 1

3 pdiff/ndiff

2 poly
transistors

2
2
3
3

1
5
 vias

• Types of via: metal1/diff, metal1/poly,

metal1/metal2.
4 4
1

2
 Metal 3 vias
• Type: metal3/metal2.
• Rules:
– cut: 3 x 3
– overlap by metal2: 1
– minimum spacing: 3
– minimum spacing to via1: 2
 Tub ties
• Also called Substract contact (or well
contact)
4
1
 spacings
• Diffusion/diffusion: 3
• Poly/poly: 2
• Poly/diffusion: 1
• Via/via: 2
• Metal1/metal1: 3
• Metal2/metal2: 4
• Metal3/metal3: 4
 overglass
• Cut in passivation layer.
• Minimum bonding pad: 100 　m.
• Pad overlap of glass opening: 6
• Minimum pad spacing to unrelated
metal2/3: 30
• Minimum pad spacing to unrelated metal1,
poly, active: 15
 SCMOS Design Rules
• Scalable CMOS (SCMOS) design rules
– Technology independent (unit of lambda)
– Standard (1.5um – 0.35um)
– SUBM (0.5um – 0.18um)
– DEEP (0.25um – 0.18um)
• Layers
– Well (n-well, p-well, twin-well)
– Active (thin oxide)
– Poly
– Contact to Poly and Active
– Via to Metal
Standard MOSIS SCMOS
(1.5um – 0.35um)
SUBM (Submicron)
0.5um – 0.18um
DEEP (deep submicron)
0.25um – 0.18um
Well
Active (MOS transistor area)
Poly (gate terminal of MOS)
Contact to Poly
Contact to Active
Metal 1
Via
Metal 2
Via 2
Metal 3
Via 3
Metal 4
Via 4 and Metal 5
Via 5 and Metal 6
 Summary of some important rules
Layer Rules No. Description Lambda (deep submicron)
active 2.1 Minimum width 3
2.2 Minimum spacing 3
poly 3.1 Minimum width 2
3.2.a Minimum spacing over active 4
3.3 Minimum gate extension of active 2.5
3.4 Minimum active extension of poly 4
contact 5.1 Exact size 2x2
5.2 (5.2b, 7.3) Minimum overlap 1.5 (1)
Metal 1 7.1 Minimum width 3
7.2 Minimum spacing 3
Via 1, 2, 3, 4 8.1, 14.1, 21.1, 25.1 Exact size 3x3
8.3, 14.3, 21.3, 25.3 Minimum overlap 1
Metal 2, 3, 4, 5 9.1, 15.1, 22.1, 26.1 Minimum width 3
9.2, 15.2, 22.2, 26.2 Minimum spacing 4
Via 5 29.1 Exact size 4x4
30.3 Minimum overlap 2
Metal 6 30.1 Minimum width 5
30.2 Minimum spacing 5