Chapter 1

Problem Statement and Solution

1.1 Problem Statement

Low-dropout regulators are mostly used to generate constant output voltage from a
noisy input power suppl. They are preferred because of their accuracy, small area. They offer
much more power efficiency over conventional voltage regulators. They consume very less
quiescent current.

In the VLSI design flow, Validation and testing of the Design has a critical part to
play. For validating LDOs, different analysis should be carried out .The prime focus of this
design is to choose architecture to have very good transient response and to provide very good
power supply ripple rejection.

1
1.2 Solution

In my thesis, I have chosen a proper architecture for the implementation of the LDO for
lower power supplies using lower power consumption. In this architecture, we have achieved
better transient response by choosing larger portion of the current to the second stage of the
OTA so the slewing condition can be eliminated completely.

In order to achieve better PSR characteristics we have chosen a ground referenced

differential pair followed by the common source with input pair is cascode configuration so that
the entire supply ripple will be at the gate of the driver transistor so that gate and source will be
in common mode with respect to supply ripple. Because of this supply ripple contribution from
the input OTA can reduced completely.

2
 Chapter 2

Low Drop Voltage Regulators

2.1 Introduction

A voltage regulator is normally a buffered reference: a bias voltage cascaded with a

non-inverting op-amp capable of driving large load currents in shunt-feedback configuration.
Linear regulators, also called series regulators, linearly modulate the conductance of a series
pass switch connected between an input dc supply and the regulated output to ensure the output
voltage is a predetermined ratio of its bias reference voltage, as illustrated in Fig. 1 . The term

and the load. Since the current flow and its control are continuous in time, the circuit is linear
and analog in nature, and because it can only supply power through a linearly controlled series
switch, its output voltage cannot exceed its unregulated input supply (i.e., VOUT <VIN).
3
 Figure 2.1 Basic Linear Regulators

2.2 Block Level Composition

A regulator is mainly comprised of a control loop whose function is to monitor and

control its output to remain within a small window of a target reference value, irrespective of
its environment and its operating conditions. A regulator circuit must therefore sense the output,
compare it against a reference, and use the difference to modulate the conductance between the
input supply and the regulated output. In the case of a voltage regulator, a feedback network
senses the output as shown in Fig. 3.3, and feeds it to an error amplifier, whose functi on
is to compare it against a reference voltage and generate an error signal that modulates the
conductance of a pass device. The circuit is essentially a non-inverting operational amplifier
with a dc reference voltage at its non-inverting input.

4
 Figure 2.2 General Block Level Composition of a linear regulator

There are two major blocks in a voltage regulator: a voltage reference and the control
loop. The latter is comprised of (1) an error amplifier to sense and generate a correcting signal,
(2) a feedback network to sense the output, and (3) a pass device to mediate and conduct
whatever load current is required from the unregulated input supply to the regulated output. The
control loop, in essence, reacts to offset and cancel the effects of load current, input voltage,
temperature, and an array of other variations on the output. The reference block provides a
stable dc-bias voltage that is impervious to noise, temperature, and input-supply-voltage
variations.

Housekeeping functions are essential to the overall health of the device. They ensure the system
operates safely and reliably, protecting the regulator from extreme adverse conditions. Plausible
destructive scenarios include exposure to over current, overvoltage, over temperature, short-
circuit, and electrostatic discharge (ESD) events. Housekeeping circuits can also have

5
application-specific features like enable-disabled soft- or slow-start functions for power-
modeling a system.

2.2.1 Dropout

The dropout voltage is defined as the value of the input/output differential voltage where
the control loop stops working. This voltage is important because it represents the minimum
power dissipated by the regulator, since the power lost is dependent on the product of the load
current and this dropout voltage. Low drop output (LDO) regulators consequently dissipate less
power than their higher dropout counterparts and have therefore enjoyed increasing popularity
in the marketplace, especially in battery-operated environments.

The three regions of operation of a linear regulator: linear, dropout, and off regions. When the
circuit is operating properly, that is to say, when it regulates the output with some finite and
nonzero loop gain, the regulator is in the linear region. As input voltage vIN decreases, past a
certain point, one of the transistors in the loop enters the triode region (or low-gain mode)
during which time the circuit still regulates the output, albeit at a lower loop gain and
consequently with some gain error. As vIN decreases further, the loop gain continues to fall
until it becomes, for all practical purposes, zero, when it reaches its driving limit.

Fig 2.3 Typical input-output voltage characteristics of a linear regulator

6
 At this point, the regulator enters the dropout region and the power switch, given its
limited drive, operates like a switch because it supplies all the current it can to maintain the
highest possible output voltage. The voltage difference between vIN and vOUT in this region
is dropout voltage VDO, and although VDO isat first approximately constant, as though it were
a resistive ohmic voltage drop, it tends to increase with decreasing values of vIN datasheets
often quote the equivalent resistance during the mostly linear portion of the dropout region. The
off region is where the circuit reaches its headroom limit, when the input supply voltage is too
low for the transistors to work properly, and more specifically, for the negative feedback control
loop to process that vOis below its target and keep some drive applied to the power switch.

7
 Chapter 3

Literature Survey

The most important aspects of the LDO can be divided into three categories quiescent
current, regulating performance, and operating voltages. Crucial metrics for characterization of
LDO are drop-out voltage, load regulation, tolerance over temperature, line regulation, droop,
output capacitor and ESR range, quiescent current, maximum load-current, and input/output
voltage range. All these performance characteristics need to trade of with each other. The
importance of particular parameter depends upon particular application.

8
3.1 DC Analysis

Drop out voltage is defined as the minimum voltage difference between input and output
voltage when the regulator stops to regulate. The drop out voltage is can be defined switch on
resistance [Ron]

Vdrop-out = ILoad Ron

3.1.1 Load Regulation

Load regulation of an LDO is defined as ratio of change in the output voltage to the
current voltage variations across the load range. It is typically the output impedance of the LDO
will define the load regulation

W Io change in the load current which the

difference between the minimum and maximum current. Ro_pass is the output impedance of
the driver transistor, Aol and are open loop gain and feedback factor of the LDO

3.1.2 Line Regulation

It is defined as change the output voltage to the change input power supply voltage, so
it is the low frequency gain from supply to the output node. The variations in the input power
supply can impact in two ways: directly through its own supply and indirectly via supply-
9
induced variations in reference vREF. The reference, as it turns out, is a sensitive node because
the regulator, being that it presents a non-inverting feedback amplifier to vREF , amplifies
variations in v -loop gain (ACL). The overall supply gain AIN is
therefore a function of both the supply gain of the regulator AIN.REG and the supply gain of
the reference AIN.REF:

3.1.3 Temperature Drift

It will basically define the variations of the output voltage with the variations in the
temperature. It can be quantified as using temperature coefficient

VTC is the output voltage variations across the temperature change

VTCVos are individual contributions of the Vref and offset voltages and Vo/Vref it is ratio of
the nominal output voltage to reference voltage.

10
3.2 AC Analysis

Fig. 3.1 System Model under Loading Conditions

Figure 3.1 gives the information about the things that will make an impact on the
stability of the LDO, they are OTA,driver element, feedback resistors, output capacitor used to
decrease variations in output voltage and associated ESR and a bypass capacitor.

In order to analyze we can broke the loop at "A" in Figure 3.1. the system should be
stable under unity feedback condition, If Vref and Vfb are the input and the output voltages
respectively. The loop gain can be defined as

Where gma and gmp are the trans conductance of OTA and driver, Roa output resistance
of the OTA, Cpar and Z are the parasitic capacitance of the driver and output impedance seen
from output voltage Vout

Where Cois the output capacitance and Resr is its associated resistance, Cb is the bypass
capacitance and Rx is the resistance seen from the output voltage Vout

11
Where Ropass is the resistance of the driver. Usually the output impedance due to the load
current is neglected because it is lot higher than output resistance Rx. If Co is far bigger than
Cb , then Z can approximated to

From the transfer function we can observe that system consists of three poles which
may possibly make the system unstable. Normally the output impedance of the system simply
equal to output impedance of the driver transistor since feedback resistors are too large. So the
poles and zeros can be derived from the transfer function are

Figure 3.2 demonstrates the frequency response of typical LDO when bypass capacitor
Cb is far lesser than the output capacitance. Even though in order to get better load regulation
we need to have larger loop gain this was limited by the unity gain band width of the LDO. The
minimum UGB of the LDO is decided by the transient response requirements. Specifically in
order to lower settling time we need larger UGB. So while there was trade off going always.
Even getting a stable system across the corners will become difficult with higher loop gains so
we need to make choose proper amount of loop gain depending upon application requirement.

12
 Fig 3.2 LDO frequency response under loading conditions

Along with that unity gain frequency also depend on the parasitic poles P2 and P3.
Typically dc gain of the LDO depends upon the relative positions of the P2 and Z1 and P3 in
order to make the system stable. As the driver transistor is having vary large size it will
contribute lot of capacitance at the gate of the driver making possible pole at the lower
frequencies. So we have to make either the input or output pole as dominant for stability.

Based upon which pole we are making dominant we will have two different kinds of
LDO internally compensated and externally compensated. For externally compensated worst-
case stability condition usually results when UGB extends into the parasitic-pole region, which
corresponds to low zESR frequencies (i.e., high RESR values), , high pO frequencies (i.e., low
CO and high IL values), and high gains which occur at the strongest process and temperature
corners of the pass device. The other worst-case stability scenario results when the ESR zero
resides one or more decades above f0dB, where it no longer saves phase, which occurs with
low RESR values, leaving a possibly unstable two-pole system, if output and error-amplifier
poles pO and pA reside at higher frequencies (with, for instance, high IL and low CO, CB, CP,
and CL values). The highest low-frequency loop gain possible corresponds to the first worst-
case stability condition because higher loop gains further extend UGB, which means loop gain
must remain below an upper bound to prevent UGB from creeping to higher frequencies.

Worst case stability conditions for the internally compensated configuration are when
P1 and P2 are at very low frequency and z1 and P3 are at very high frequency. The second one
is extending UGB to very high frequencies that is placing P1 and z1 at very low frequency and
p2 and p3 at very high frequency.

13
3.3 Transient Analysis

One of the important specifications for the LDO is its droop which defined as the
amount of the voltage decreased when the load is current is changed from minimum to
maximum within certain time which depends on the application. This specification is depends
upon the load which the LDO driving for the digital application this is not a stringent condition
but for analog applications it cannot go below certain vout min.

Fig.3.3 Typical LDO Transient response to a load current step

Figure 3.3 shows the output voltage transient characteristics when the load is changing
from minimum to maximum. Here is the time for the negative feedback loop to respond to
supply sufficient amount of load current which is basically equal to sum of time durations of
negative feedback loop to start acting and time required to charge the node to the required
potential. So the total time can be given by

tsr =

Here the BWcl is the closed loop band width of the LDO and Cpar is the capacitance at the gate
Isr is the slewing
rate limited current of the previous OTA. So droop of the system basically depends on the
output load capacitance and slew rate current and unity gain band width of the LDO. If the load
capacitance is large then amount of output voltage decreased is very less and if the slewing
limited current is large it can charge the driver gate node very fast so that droop can be
14
decreased. UGB is inversely related to the time required for the LDO to respond so it will
inversely related to the output voltage droop. Once the driver starts to supplying sufficient
amount current then LDO output voltage will starts to settle to the final output voltage. The

characteristics.

Fig.3.4 Simplified LDO Schematic for the purpose of transient analysis

3.4 Simulations

3.4.1. Functionality

The role of simulations in state-of-the-art designs is increasingly important. Their

general objectives are to (1) verify functionality and (2) ascertain parametric-compliance limits.
As in programming, however, they are as good as their inputs: "garbage in, garbage out.
should therefore simulate only when they think they know what to expect so that
they may properly evaluate the simulation. If the results do not conform to expectations, there
is either a problem with the simulation itself or the circuit, so the first thing to do is ensure the
operating conditions, models, and so on of the simulation are correct, and if so, a reevaluati on

15
of the circuit (without the computer) is in order. This process is iterated until the results match
expectations, at which point the designer is in a better position to make important design choices
and performance tradeoffs.

3.4.2. Parametric Limits

The second important objective of simulations is to ascertain the parametric limits of

the circuit when subjected to extreme process corner variations and operating conditions,
oftentimes referred as process-voltage-temperature (PVT) corners, even though extreme load
current, output capacitance, and other operating conditions are also considered. These
simulations ascertain systematic and process wide variations of all performance parameters by
repeating each circuit test and successively changing models and operating conditions to
include all possible combinations. For instance, weak NMOS, strong PMOS, and nominal NPN
transistors, along with high resistor and capacitor values, may constitute one model set of many
similar and distinct model combinations. Similarly, high temperature, low input voltage, low
output capacitance, high ESR, and so on also comprise a condition set to which the circuit will
be exposed while performing worst-case corner simulations

Process engineers often guarantee parameters that perform better than what they claim because
their intent is to increase die yield (i.e. profits for the company), which means process-corner
simulations is, on probabilistic terms, pessimistic: an exhaustive linear combination of six-
sigma variables is unrealistic. The caveat, however, from a
analog circuit has an infinite number of operating conditions (e.g., start-up conditions subject a
circuit to an infinite number of bias points large-signal behavior and therefore an infinite
set of ac conditions) and it is impossible to simulate them all, one at a time. This is why a linear
sum of six-sigma process variations, in combination with good engineering judgment, is
believed to mitigate the risk associated with analog IC design and help justify the cost of
fabrication. Fast product-development cycles also rely on these extreme corner scenarios to

16
increase the chances of building a sufficiently robust prototype to meet all parametric limits
after only one fabrication cycle, achieving the coveted first-pass success.

Along with AC, DC, Transient, Stability simulations some other simulations are also important
in terms of reliability of ip.

3.5 Other Reliability Analyses

A device reliability check helps us ensure that the Transis

before their operating lifetimes.

Instant dielectric failures

Progressive degradation

3.5.1 Aging

Tool : Relxpert Aging

During circuit operation, transistor performance (Id, Vtetc.) degrades with time
Relxpert-Aging allows the designer to simulate their circuit blocks for prediction of end-
of-life transistor/circuit degradation over a period of Time. Aging Analysis predicts
changes in device and circuit performance over arbitrary periods of time (e.g. 10 years)

RelXpert-aging in a nut-shell

Estimates this degradation based on the transient simulation of a circuit (stress

simulation).

17
 Evaluates the impact of this degradation on circuit performance (aged simulation).
Speed, timing & functionality
Calculates the current degradation
Relxpert uses APS as its underlying engine and is a circuit level reliability tool

Fig 3.5 Aging flow

3.5.2 Electric Overstress analysis

High Voltage EOS tool purpose is to check the internal nodes or junction of every device
for excessive Over-shoot and Under-shoot Voltages. Devices checked include all thin & thick
gate transistor types, decaps, and ESD diodes.

EOS tool will also identify high current events, such as latch-up or high current leakage
paths.
Tool will calculate defects per million (dpm) generated due to oxide voltage stress as a
quality metric. Check with Q&R for acceptable dpm success criteria.
18
Any circuits with Vds type violations will need to be checked with an Aging simulations
tool that models hot carriers, to determine if violation can be waived.
Simulations are performed at PVT corners.

19
 Chapter 4

Vampire Pro - Analog Regression Framework

4.1 Introduction

In this chapter, Introduction to vampirepro, features of tool and options available will
be discussed in brief. Vampirepro is an INTEL specific tool which is used for regression testing
of different IPs at a same time.

20
4.1.1 Challenges in Analog regression testing

There are lot of challenges in Analog regression testing. Few of them are listed below:

Multiple simulation test-benches (ADEXL) per block:

There are different types of simulations to be carried out on a single design. To carryout
different analysis, different setups have to be made for each analysis. For example for
DC analysis, equations for all the margin as well as output DC voltage etc has to be
added and for AC analysis, PSRR equation should be added. Not only in ADEXL view
but schematic also should be changed according to analysis. Hence there are more than
one ADEXL are there for a single IP. There was not an option to simulate them
simultaneously with a single fire.
Frequent UPF/Model updates: As the technology node decreases the need of newer
model libraries hikes as to overcome the leakage problems. Updated model libraries can
improve the performance in terms of saturation margins, PM, GM, UGB etc.
Resource intensive, manual and time consuming:

tasks at same time. Resources available are all manual and because of that they are very
time consuming.
Summarize and review results: There is no tool available which can give a summary
report so that comparison can be done easily. VampirePro generates summary report
and comparison can be done easily from that.

4.2 Features of Vampire Pro

VampirePro is an INTEL specific tool. It contains multiple features to reduce regression

testing efforts. Prime features are as listed below:

Users can import multiple ADEXL views: At the same time, multiple ADEXL can be
added for testing. Testing time and efforts can be decreased

21
 Override options in ADEXL views through interface: Another useful feature of the tool
is override. By using this feature you can override particular things, which are available
in ADEXL view, directly from the tool itself. You need not to switch to ADEXL and
make changes to some specific settings. The settings which can be modified from the
tool itself are as follows:
NB settings
UPF
Corners
Run directories
Variables etc.
Track job status: After submitting the job if we want to track the job that till where the
run has reached for that also option is available. Some Simulations take a long time to
finish and sometimes it fails. To track the jobs submitted is essential.
Review the results summary from interface: From the tool GUI itself you can see the
result after the simulation gets over. You need to open anything to see the equation
result you have added to your ADEXL view. To see the waveform you need to open
VIVA which can be opened from the toll itself.

4.3 Vampire Pro GUI

Edit global settings if needed for VampirePro Run directory and Job settings

NOTE: Fields in Red are mandatory to be filled.

Run directory: Used to give path where results need to be stored.

Run Name: Give a unique Run Name if you want to preserve the previous run.

22
 Fig 4.1 Global job setting

4.3.1. Add ADEXL views

Add regression block:

In VP we wanted to keep a group of ADEXL Views together so you can control the settings
for a group and also later review the results later in a group. For example you can call your
Regression Block TX or Transceiver or Whatever something meaningful and then add a
bunch of ADEXL Views related to TX under the Block.
Right Click to bring up the Pop-up Menu. The Pop-up menu Items change based on where
you right click

23
 Fig 4.2 Adding Regression block

4.3.2. Add ADEXL view for the regression block:

a. First we add the ADEXL Views with right click Menu.

b. Select The Block and Right Click to bring up Pop-Up Menu.
c. Click on Add ADEXL View.
d. Search for Library, Cell, View.
e. Click ADD ADEXL View.
f. Repeat step 4 and 5 for all ADEXLviews and click Cancel.

24
 Fig 4.3 Adding ADEXLS

4.4 Setup batch mode regression

4.4.1 Generate Ocean Scripts:

The VP System is totally based on Ocean Scripts, whenever you add a new ADEXL view or
make any changes to ADEXL View you need to click the Refresh Ocean Scripts Button

Fig.4.4 Generate the ocean scripts

25
4.4.2. Regression Block or Group of ADEXL Level Overrides:

Select The Regression Block You want to Override Settings.

Turn ON Override Settings for ALL ADEXL Views(s) Under Block.
Make Changes in Respective Tabs

Fig 4.5 Regression Block Override

Following Categories of Overrides are Possible for a group of ADEXL Views:

a. Simulation Settings like Run Directory

b. UPF/Model Files

c. PVT Corners

d. Net batch Job Settings

e. Dependent Simulation Settings

4.4.3 Launch the jobs

You can launch the jobs using the Launch Batch Sims Button. Then Monitor the status
in the GUI on the Job(s) Status and Logs tab. Once the run completes you will see the
PASS/FAIL/Terminated/Unknown status based on the Net batch and Simulation status.

26
 Fig 4.6 Launching jobs

4.4.4. Review the simulation results and reports:

You can look at the summary with PASS/FAIL per Block/Regression Group as shown below

Fig 4.7 Simulation results review

You can look at the results of individual ADEXL Simulations as shown below:

27
 Fig 4.8 Results

4.4.5 Input, output and log files

The Files that are very important for debug are presented in the GUI. The GUI is
dynamic, based on the Run you select the output File paths change. You can just double click
to open the files as shown in the image below:

Fig 4.9 Log files

28
 Chapter 5

Design of LDO

The LDO will be designed and simulated with a 14nm CMOS process. The environment for
the LDO consists 0,6 V reference voltage and 1.05 V supply voltage from switching regulator
with -7% and +5% variations on it. It is having load current which is varying from 0 to 60mA.
Basically in this section we will concentrate different trade off made during design of the LDO.

29
5.1 Specifications

Table 5.1 Specification table of the design

Specification Min Nom Max Comments

Input supply 1.05 Nominal Value

Vcc at bump 0.9765 1.05 1.115 VCC at silicon junction

Vout 790mv 800mv 810mv LDO Vout nom = 1.05V,

Iloadavg (min
-max) 0.1mA 60mA

Device 250pF Intrinsic cap

load
cap MIM 1nF MIM cap

Power noise
rejection -30dB At DC

Quiescent
power (.8mA + 3mA Quiescent power excludes the power
consumed )*1.05 consumed the driver due to the load current

Droop 60mV With iload changing from 0 to 60mA in 1ns

30
5.2 PVT conditions

One of the main challenges of the voltage regulators is to design it across the process corners,
temperature and voltage variations .process corners will define the variations in the device
characteristics during the fabrication. Even though not always the case generally process skews
definition will have four letters where the first two will define the silicon behavior and 3rd and
4th letters will define whether the nmos and pmos in the system are slow or fast. With the
operating conditions the temperature will also vary. Even the supply generated from the
switching regulator will vary around -7 % to +5%

Process skews: tttt rcss rcff rxsf rxfs rsss rssf rsfs rfsf rffs rfff

Table 5.2 Table PVT conditions for simulations

Specification Minimum Nominal Maximum

Vcc 0.9765 1.05 1.15

Iload 1u 60m

temperature -40 110

31
5.2 Architectural choice and design of individual blocks of the
LDO

5.2.1 Choice of Driver transistor

Area of the driver transistor will be decided by the load current. If the drop out voltage is very
less then pmos is preferred. It is easy to compensate NMOS driver transistor compared to pmos
because of its lower output impedance. NMOS will occupy lesser area compared to pmos
because of its higher current capability. For lower power supplies pmos is preferred compared
to the nmos because of its lower dropout voltage.

Because we are having dropout voltage of 175mv only we can have to pmos transistor as driver
pout voltage
because of its minimum vgs of the transistor will be effecting the drop out voltage.

5.2.2 Design of driver transistor

Size of the driver transistor will basically depend on the maximum value of the transistor. Here
we are using 60mA as maximum load current. Since the pmos device which we are using can
support 25uA for overdrive of 100mV we have to use around 3000 mult for pmos driver.

32
Stability will also become issue of concern at lighter loads. Because at lighter loads the output
impedance of the driver transistor is will be high so the output pole will move towards the
dominant pole so that stability will became an issue. So that a minimum current should flow
through the driver so that output pole will always placed above a certain frequency.

5.2.6 Feedback Resistor divider

Output voltage is fed back through Resistor dividers. This resistor divider network adjusts their
value and supplies the voltage to OTA second input which will be compared to Vref. Here I am
allotted 100uA for the resistor divider. We can even spend more current using this divider so
that this will decrease the amount of leaker we need to spend. Even choosing lower values for
the fee back resistors will also improve power supply ripple rejection.

5.2.7 Compensation

In an uncompensated LDO there are two significant poles. One is at the output of the
LDO because of large output capacitance which is used to decrease transient variations during
the load transients. The other is at input of the driver this due to large capacitance of the driver
due to large size and large output resistance of the OTA. The large output resistance is the
resultant of the large gain of the OTA.

Out of these two poles the pole at the driver input is called is as internal pole and the
pole at the output is called as output pole. Out of these two poles we have to make one of the
poles as dominant. If we want to make the output pole as dominant we need to increase the
capacitance at the output node. But increasing the output capacitance will occupy a lot of area.
So this is not an optimum solution unless we are having very high load currents. Since for large
load currents we need to use large capacitance to obtain better transient response. Otherwise
we need to decrease the size of the driver transistor to obtain higher output resistance but we

37
 ain the required phase margin.
Since this will degrade the UGB of LDO settling time of the LDO impacted badly. So we need

So we need to place this first pole according to the transient requirements.

In order to make the system stable we need to make compensate the second pole using a
zero. But across the load conditions the position of the second pole will move. At lighter loads
pole will move towards the lower frequencies so in the worst case we have to make the system
stable at lighter loads. In order provide almost same amount of phase margin across the load
conditions we need to track the output pole using pole tracking zero.

In order to obtain the pole tracking zero we can use a series combination of PMOS FET,
capacitance and resistor. Here the resistance of the pmos will be varied depending upon the
load current this due to vgs of the driver transistor will be varied proportionally so that zero will
also track the output pole.

5.3 AC and Stability Simulation Results:

5.3.1 Stability

All the stability parameters like PM, GM, LG and UGB is analyzing under this analysis for both
models. In the new updated model the performance is increased in-terms of stability parameter.

Figure 5.6 Stability and AC simulations of the LDO

39
 Chapter 6

Conclusion

I have successfully designed a low dropout regulator for lower power supplies. For
lower droop and better psr response. In order to achieve this I have taken new architecture for
the implementation of iref and operational conductance amplifier second stage. In order to
provide better transient performance I have used most current in the second stage of the op amp.
Even though the above architecture provides better power supply ripple rejection it provides
challenges while compensating the loop with three poles. So in order to make the system stable
we can track the output pole using pole tracking zero. We have to choose the location of first
pole depending up on the location of the remaining poles and zero so that w can get maximum
amount of unity gain frequency which will define the transient characteristics. I have presented
various simulation results for LDO for design verification.

43
 References

[1] Rincon-Mora, G.; Allen, P.E., "A low-voltage, low quiescent current, low drop-out
regulator," in IEEE Journal of Solid-State Circuits, vol.33, no.1, pp.36-44, Jan 1998 doi:
10.1109/4.654935

Compensation Technique for CMOS

Operational Amplifiers -STATE CIRCUITS, VOL. SC-18,NO.
6, DECEMBER 1983

[3] Tantawy, R.; Brauer, E.J., "Performance evaluation of CMOS low drop-out voltage
regulators," in Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest
Symposium, vol.1, no., pp.I-141-4 vol.1, 25-28 July 2004 doi:
10.1109/MWSCAS.2004.1353917

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 3,

JUNE 1982

[5] Abbasi, M.U.; Abbasi, T.A.; Abbasi, M.S., "A Fast Transient Response Low Drop -Out
Voltage Regulator," in Computer Science and Information Engineering, 2009 WRI World
Congress on , vol.3, no., pp.545-549, March 31 2009-April 2 2009 doi:
10.1109/CSIE.2009.91

-out voltage regulator in 90-nm CMOS

technology," in Complex Systems (ICCS), 2012 International Conference on , vol., no., pp.1-
4, 5-6 Nov. 2012 doi: 10.1109/ICoCS.2012.6458540

44
 Acknowledgement

I would like to extend my sincere thanks to my guide, Dr.T.V.K. Hanumantha Rao,

Associate professor, Department of Electronics and communication Engineering, National
Institute of Technology, Warangal. He has been extremely helpful with his knowledge and
enthusiasm. My project would have not been possible without the kind support he offered.

I would like to extend my sincere thanks to VLSI-SD faculty coordinator Sri. K.

Sarangam, Assistant Professor, Department of Electronics and communication Engineering,
National Institute of Technology, Warangal, for his support throughout the entire course.

I am grateful to all my team members for giving me this opportunity to be a part of

Intel as an Intern and helping me in successfully completing this project. I also want to thank
Mr. C V Ramana, Engineering manager, MIG group at Intel Corporation for his constant
guidance and motivation. I would also like to all other team members at Intel for their constant
help and support. Without their experience and insights, it would have been very difficult to do
quality work.

Besides my guide, I would like to thank Associate Professor Dr. T. Kishore Kumar,
Head of the Department for his excellent support directly and indirectly and also, I would like
to thank all staff members of ECE Department for their help and kind support in times of need.

I would like to express my gratitude to my parents for their kind co-operation and
encouragement which helped me in completion of this project.

At last I thank all my classmates for their help in the discussion of the problems about
this project.

Davalapalli Sateesh

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