A 5GHz CMOS Low Phase Noise Transformer Power Combining

VCO
Ping Wing Lai, Stephen I. Long

Dept. of Electrical and Computer Engineering, University of California Santa Barbara, CA93106
long@ece.ucsb.edu

Abstract A transformer based power combining parallel resistance of the resonator and gmbias is the gm of
technique is shown to be an efficient method for reducing the FET current source. In the current-limited regime,
VCO phase noise. Higher signal power and resonator Q can where the current source remains in saturation, the
be achieved while avoiding breakdown without penalty in oscillation amplitude V is proportional to IdRp.
tuning range. A CMOS process was used to fabricate the
Vdd
5GHz VCO. This VCO has a 4dB improvement in phase noise Vdd
and 2dB improvement in FOM over a simple LC VCO. The
Vgate Bias
phase noise at 1 MHz offset is 125 dBc/Hz. The VCO
dissipates 5.5mA with 17.6% tuning range at a 1.5V supply
voltage.

1. Introduction Vtune Vtune

As CMOS scaling continues, the device Bit0 Bit0
breakdown voltage will be reduced, and the Q factor of the Bit1 Bit1
passive element (inductor) will not improve. Therefore, Bit2 Bit2
Bit3 Bit3
improvement in oscillator phase noise will be limited since
the carrier/phase noise ratio of the oscillator is proportional
to the voltage swing. A smaller inductor, which has a Vdd VCO VCO
Vdd Vdd VCO VCO
Vdd
Core4 Core4 Core2
smaller equivalent parallel resistance (Rp), can be used to Core2

draw more current but keep the voltage swing below
breakdown voltage. Although more power in the tank can
increase the carrier, the smaller Q will increase the phase
noise. Phase noise can also be reduced with the same
resonator voltage swing by coupling several (N) identical
oscillators to each other, and the phase noise will be
reduced by a factor of 1/N [1]. But the chip area will be
increased in the same proportion. In Figure 1, a
transformer based area-saving coupled oscillator was
proposed [2-4]. Several individual oscillators were
combined by a transformer. In this paper, the transformer
based coupling and diode based bias level shifting
technique have been used to design a 5GHz VCO using a
0.18um CMOS process. Benefits in signal power and
resonator Q lead to a 4dB improvement in phase noise and
2dB improvement in FOM over a simple LC VCO. Tuning
range is retained while breakdown can be avoided.
2. Circuit Design
In recent research, it [5] states that Lessons
hypothesized equation
2 element and the parasitic capacitance from the gm cell are
4 FkTR p o
L ( m ) = (1)
V 2 2Q m
holds for the current-biased differential CMOS LC
oscillator by the first order approximation where V is the
oscillation single ended peak amplitude, Id is the bias
current, is the FET noise factor, Rp is the equivalent
Vswitch
VCO VCO
Core3
Core3 Vswitch Vswitch
Vdd Vdd
(a) (b)
Figure 1 Circuit Diagram of Transformer Power Combining VCO
(a) without (b) with diode based bias shift
In [6], it is shown that phase noise can still be
reduced by increasing current, Id, if Rp is reduced while
IdRp is kept constant. It is because the noise factor as
shown in equation (1) will not change if IdRp is kept
constant. One way to reduce the Rp while keeping IdRp
constant is to divide a simple inductor into several coupled
inductors, a transformer [2-4].
In this paper, 4 individual oscillators were
combined by a transformer. The physical layout of the
transformer is shown in Figure 2. The transformer is laid
out such that each coupled inductor will be geometrically
symmetric. Moreover, identical negative gm cell and
frequency tuning elements are used at each coupled
inductor, and the tuning capacitance from the tuning
equally distributed in each coupled inductor. Therefore, the
current distribution through each coupled inductor will be
the same, so the mutual inductance among the coupled
inductor is maximized to obtain the highest Q. The CMOS
process offers 6 layers of metal for interconnection with
the thick metal option. Metal6, the thick metal, is used for
the top level of the transformer, while metal 5, 4, 3 are in
parallel for the underpass of the transformer. An extra 25 SRF
SRF 8 turn
outer turn is used to couple the signal out from the
transformer to the buffer. The size of the transformer is
20 8 turn Transformer
inductor
585 x 585 um2.
15
The simulated Q of the 8 turn transformer, simple

Q
8 and 4 turn octagonal symmetric inductors are compared 10 SRF
in Figure 3. They are designed to have same inner 4 turn
diameter. The Q and inductance of the transformer has 5 inductor
been determined when it is parallel resonated with 4 ideal
capacitors. The resulting Q of this parallel resonant circuit 0
can be extracted from the phase slope. In order to calculate

0.00
1.0G
2.0G
3.0G
4.0G
5.0G
6.0G
7.0G
8.0G
9.0G
10.G
a Q versus frequency characteristic for the transformer, the
capacitors were swept in value to achieve a range of
resonant frequency. From Figure 3, the self resonant Frequency (Hz)
frequency (SRF) of the 8 turn transformer is higher than
Figure 3 Simulated Q of the Simple Inductors and Transformer
the 4 turn inductor, and the Q of the transformer is higher
and layout of the Inductors
at 5GHz. The Q of the transformer is close to the 8 turn
inductor, but the SRF of the 8 turn transformer is about 4
The schematic of the CMOS VCO is shown in
times higher than the 8 turn inductor. The increase in SRF
Figure 1. The negative Gm cell of the individual oscillator
is because the total inductance and parasitic capacitance of
is made by a pair of cross coupled PMOS transistors.
the whole transformer is shared among 4 coupled
PMOS is used because it may have less 1/f noise, and the
inductors. As a result, a larger transformer can be used to
N well parasitic substrate diode has a higher Q which
increase the Q of the tank.
would have smaller loading effect on the tank. The tail
current generator is eliminated since, in [7], it shows that
the tail current generator is a main contributor to both 1/f3
and 1/f noise. Without the voltage headroom of the current
generator, the oscillator can operate at higher voltage
swing but in a voltage-limited regime (triode region) which
will load the tank. The duration of the PMOS in triode
region can be reduced by reducing the width of the device,
however, the voltage swing will also be reduced. From
simulation, it shows that there will be an optimum width
for the best FOM for a particular tank network.

A bias-level shift technique [8], as shown in

Figure 1(b) and 4, is used to have one extra degree of
freedom to adjust the duration of PMOS in triode region by
shifting the dc gate voltage. 2 minimum p well p/n+ diodes
(a) are used to shift the gate voltage. A P well diode avoids
loading the tank with the parasitic substrate diode. A diode
instead of resistor is used because the diodes will self-bias
into reverse bias once the oscillation is started, so it can
provide an extremely high resistance, minimizing the
loading effect from the bias. As shown in Figure 4, the
Vgate bias is set to ground for avoiding the PMOS in
triode region. Large capacitors are used to cross-couple the
gate and drain. 2 n well accumulation mode MOS varactor
arrays are used for fine frequency tuning. A 4 bit NMOS-
switched capacitors frequency tuning array is used for
coarse tuning. Using this array also minimized the high
sensitivity to the tuning port by reducing the frequency to
voltage tuning ratio. A common source stage with resistive
(b) feedback is used as a buffer to minimize the loading on the
Figure 2: (a) Layout of the Transformer and (b) with Coupled VCO.
Inductors high lighted
 Vgate Bias = -0.8 Vgate Bias = 0
Vgate
-119
Transformer with bias shift
Transformer w/o bias shift
-120 Simple LC
GND
-121

Phase Noise @1MHz (dBc/Hz)

Vdrain
-122
Off Active Triode Active Off Off Active Off

-123

Idrain -124

-125

Figure 4: Vgate, Vdrain and Idrain of VCO at different gate bias -126
voltage level
-127
3. Measurement Results
-128
Both 4 turn simple inductor and 8 turn 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
transformer direct cross couple VCO without bias shift are Frequency (Hz) 9
x 10
also fabricated in a 0.18um CMOS for comparison. The Figure 5 Phase Noise versus the whole Frequency Range
-186
measured phase noise and FOM that is defined below Transformer with bias shift
Transformer w/o bias shift
Simple LC
f off
2
-187
FOM = 10 log P + L ( f off )dB

(4)
f o
-188
where P is the power dissipation of the oscillator in
milliwatts, fo is the center frequency, foff is the frequency
FOM

-189
offset from the center, and L(foff) is the phase noise
measured at foff offset frequency, plots of all VCOs at
1MHz offset are shown in Figure 5 and 6. The transformer
-190
coupled VCO with bias shift shows a phase noise and
FOM of 4dB and 2dB improvement over simple LC VCO
across the whole tuning range respectively. The diode bias -191
shifting technique improves the FOM of the transformer
coupled VCO by 2dB. It shows that the transformer
coupled technique can improve the phase noise. The -192
4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
transformer based VCOs show a similar tuning range of Frequency (Hz) 9
x 10
18% from 4.51Hz to 5.38GHz while the simple LC VCO
Figure 6 FOM versus Control voltage
show 14.5% tuning range from 4.21 to 4.87GHz, both 9
under 1.5V supply. The bias shifted transformer VCO has x 10
5.4
a phase noise of -124dBc/Hz to -127dBc/Hz at 1MHz. It
5.3
draws around 5.2mA to 5.5mA across the whole frequency
range. The plot of frequency versus control voltage is 5.2
shown in Figure 7. The die photo in figure 8 shows that the 5.1
Frequency (Hz)

VCO area is 0.81mm 2.

5

Table 1 compares the published VCO in 5GHz 4.9

range. It shows that our oscillator predicts the best phase
4.8
noise and FOM out of the current published VCO.
4.7

4.6

4.5
0 0.5 1 1.5
Control Voltage (V)
Figure 7 Frequency versus Control voltage
Ref. fosc (GHz) Vdd (V) Icore (mA) Tuning (%) Phase noise@1MHz FOM
[7] 4.6 to 5.7 2.5 2.9 21% -118.5 to -122.5 -183 to -189
[9] 5.13 to 5.33 1.5 11.5 3.8% -126 -188.2
[10] 4.57 to 5.21 2.5 8.75 13% -124 -185
[8] 5.18 to 5.88 1.5 5.1 12% -124.17 -190.7
[11] 5.12 to 5.52 1.8 7.5 8% -124 -187.2
[This Work1] 4.21 to 4.87 1.6 2.3 to 2.5 14.5% -119 to -122.5 -187 to -189.5
[This Work2] 4.51 to 5.38 1.5 7 to 7.7 17.6% -123 to 126 -187 to -189.5
[This Work3] 4.51 to 5.38 1.5 5.2 to 5.5 17.6% -124 to 127 -189 to -191.5
Table 1 FOM performance comparison
1
Simple LC oscillator, 2 Transformer coupled oscillator without bias shift, 3 Transformer coupled oscillator with bias shift

[3] P. Lai, S. Long, A 5GHz pHEMT Transformer-

Coupled VCO, IEEE RFIC symp., pp.135-138, Jun. 2005.

[4] P. Lai, S. Long, A Low Phase Noise InGaP-GaAs

HBT Transformer Power Combining VCO, IEEE CSIC
symp., pp.81-84, Oct. 2005.

[5] E. Hegazi, J. Rael and A. A. Abidi, The Designers

Guide to High-Purity Oscillators, Kluwer Academic
Publishers 2004.

[6] P. Lai, L. Dobos, S. Long, A 2.4GHz SiGe Low

Figure 8 Die photo
4. Conclusion
One of the most efficient methods of reducing
phase noise is to increase the signal amplitude in the
resonator. However, the maximum resonator signal
amplitude is limited by the breakdown mechanisms in the
devices and supply voltage. A transformer power
combining oscillator is introduced to allow a higher current
swing in the tank in order to reduce the phase noise.
5. Acknowledgment
The authors gratefully acknowledge the
fabrication support of MOSIS. The authors would also like
to thank Prof. Robert York and Chris Sanabria for their
support in testing and Vikas Manan for helping
discussions.
6. References
Phase-Noise VCO Using On Chip Tapped inductor, IEEE
ESSCIRC, pp. 505-508, Sept. 2003
[7] S. Levantino, et al., Frequency dependence on bias
current in 5 GHz CMOS VCOs: impact on tuning range
and flicker noise upconversion, IEEE J. Solid-State
Circuits, vol. 37, pp. 1003 1011, Aug. 2002.
[8] T. Song, et al., A 5GHz Transformer-Coupled CMOS
VCO Using Bias-Level Shifting Technique, IEEE RFIC
symp. 2004. pp. 127-130, Jun. 2004.
[9] T. Kim; A. Adams, N. Weste, High performance SOI and
bulk CMOS 5GHz VCOs, IEEE RFIC Symp., pp. 93-96, June
2003.
[10] S. Gierkink, et al., A low-phase-noise 5-GHz CMOS
quadrature VCO using superharmonic coupling, IEEE J. of
Solid-State Circuits, vol. 38, pp.1148-1154, July 2003.
[11] A. Jerng, C. Sodini, The impact of device type and sizing
on phase noise mechanisms, IEEE J. of Solid-State Circuits, vol.
40, pp. 360-369, Feb. 2005.

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