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3, MARCH 2013

Andrea Mazzanti, Member, IEEE, and Pietro Andreani, Senior Member, IEEE

pairs working in Class-C in pushpull configuration is presented.

The oscillator exhibits the same advantages enjoyed by comple-

mentary topologies on oscillators based on a single differential pair,

while yielding a substantial power consumption reduction thanks

to the Class-C operation. The phase-noise performance and the

fundamental conditions required to keep the transistors working in

Class-C are analyzed in detail. It is shown that, for an optimal per-

formance, both nMOS and pMOS transistors should not be pushed

into the deep triode region by the instantaneous resonator voltage,

and a simple circuit solution is proposed to accommodate a large

oscillation swing. A 0.18- m CMOS prototype of the (voltage-con-

trolled) oscillator displays an oscillation frequency from 6.09 to

7.50 GHz. The phase noise at 2-MHz offset is below 120 dBc/Hz

Fig. 1. (a) Original Class-C oscillator. (b) Pushpull Class-C oscillator.

with a power dissipation of 2.2 mW, for a state-of-the-art figure-of-

merit ranging from 189 to 191 dBc/Hz.

Index TermsClass-C, CMOS, phase noise, pushpull, voltage

controlled oscillator (VCO). the resonator (resulting from a small current conduction angle

of the transistors) leading to a high conversion efficiency of

the dc current into the fundamental harmonic current. For the

I. INTRODUCTION same dc current, the theoretical phase-noise improvement com-

pared with the standard differential-pair LC-tank oscillator is

3.9 dB; for the same power supply voltage, on the other hand,

T HE voltage-controlled oscillator (VCO) is a key building

block in high performance wireless and wireline commu-

nication systems. VCO research is steadily attracting a great in-

the Class-C oscillator ideally allows a 36% current saving for

the same (minimum) phase-noise level. Since its first introduc-

tion, the Class-C oscillator has gained an increasing popularity,

terest, leading to a proliferation of different topologies aimed

and several applications and improvements have been proposed

at improving frequency tuning range and phase noise [1][13].

in the recent literature [16][23]. All of the realizations pre-

The latter in particular deserves attention, since it determines the

sented so far are nevertheless based on a single differential pair

power consumption requirements. It has been rigorously proved

configuration, similar to the original topology in Fig. 1(a).

that the contribution of the thermal noise of the core transistors

This paper introduces a push-pull Class-C oscillator, shown

to phase noise in a generic harmonic oscillator does not, to the

in Fig. 1(b). While still preserving the superior dc-to-RF cur-

first order, depend on the transconductance of the core transis-

rent conversion efficiency of transistors working in Class-C and

tors [14], [15]; thus, although technology scaling does reduce

the same maximum theoretical phase noise figure of merit of

losses in switched-capacitor frequency tuning (which is partic-

the original Class-C VCO, the circuit displays the same advan-

ularly important for applications with a large tuning range), it

tages that, in some cases, make a complementary LC-tank os-

does not otherwise improve significantly the VCO spectral pu-

cillator (employing both nMOS and pMOS switching transis-

rity. The VCO power consumption is therefore becoming more

tors) preferable to a single differential pair oscillator [24][27].

and more dominant, compared with other system blocks directly

These advantages can be summarized as follows: 1) twice the

benefiting from technology scaling, and techniques to improve

tank voltage swing and 6-dB improvement of phase noise for

the VCO power budget without deteriorating its phase noise are

the same current consumption and resonator, provided the oscil-

of the greatest interest. Among different solutions, the Class-C

lator is working in the current-limited regime1; 2) a larger loop

oscillator of Fig. 1(a) has been proposed [14]. In this harmonic

gain due to the contribution of both nMOS and pMOS transcon-

oscillator, active devices deliver short and tall current pulses to

ductance; and 3) a voltage swing always within the supply rail,

avoiding reliability issues.

Manuscript received July 27, 2012; revised October 01, 2012; accepted

A 0.18- m CMOS test chip has been realized. Drawing

November 05, 2012. Date of publication December 20, 2012; date of current

version February 20, 2013. This paper was approved by Associate Editor 1.2 mA from a 1.8-V supply, the pushpull Class-C VCO is

Woogeun Rhee. tunable from 6.09 to 7.50 GHz, with a phase noise at 2-MHz

A. Mazzanti is with the Universit di Pavia, Dipartimento di Ingegneria

Industriale e dellInformazione, 27100 Pavia, Italy (e-mail: andrea.maz- 1Complementary oscillators do not improve the phase noise figure of merit,

zanti@unipv.it). compared to single-differential-pair oscillators. In fact, the maximum allowed

P. Andreani is with Department of Electrical and Information Technology, voltage swing in complementary oscillators to operate in the current-limited re-

Lund University, SE-221 00 Lund, Sweden (e-mail: piero@eit.lth.se). gion is one half that in single-differential-pair oscillators, leading to the same

Color versions of one or more of the figures in this paper are available online optimal phase noise normalized to power dissipation. This result has been de-

at http://ieeexplore.ieee.org. rived in [27] and exploited in [26] for the traditional differential pair oscillator

Digital Object Identifier 10.1109/JSSC.2012.2230542 topologies.

MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 725

the moderate overall tank quality factor of approximately

10, the oscillator displays a remarkable peak phase noise

figure-of-merit (FoM) of 191 dBc/Hz.

The paper is organized as follows. Section II reviews the prin-

ciple of operation of the Class-C oscillator and introduces the

theoretical framework for the push-pull configuration. A large

signal analysis of the circuit is carried out, deriving the condi-

tions under which short current pulses and high DC-to-RF con-

version efficiency is preserved in the complementary topology.

Section III analyzes the phase noise of the push-pull oscillator

and discusses non-ideal effects that should be considered to

Fig. 2. Current and voltage waveforms in the pushpull Class-C oscillator. (a)

avoid unwanted phase noise degradation. Section IV presents a First half and (b) second half of the oscillation period.

modification of the push-pull Class-C oscillator, able to accom-

modate a large voltage swing without phase noise penalty, as

well as a comparison with the standard complementary CMOS where is the tank common-mode dc voltage and

oscillator. The design and experimental results of a circuit pro- , where is the angular frequency of oscillation. Assuming

totype are presented in Section V, while Conclusions follow. a moderately large resonator quality factor, the differential tank

voltage can be approximated as a sinusoid with amplitude2

II. LARGE SIGNAL ANALYSIS

as

The large-signal operation of the pushpull Class-C oscillator

is presented in this section, deriving the conditions required to

preserve a highly efficient pulsed tank current. The fundamental (2)

difference between the standard differential-pair LC-tank oscil-

lator and the Class-C LC-tank oscillator in Fig. 1(a) is the rela- We assume that the transistors do not leave the saturation region,

tively large capacitance ( ) connected between the common i.e., a suitably low is selected for the nMOS transistors,

source node of the nMOS transistor pair and ground. keeps while the following condition holds for the pMOS transistors:

the voltage of the common source node (almost) constant.

As a result, the nMOS devices are active (i.e., they conduct cur- (3)

rent) only when (where are the gate

voltages of the two transistors of the differential pair and where is the pMOS threshold voltage. Looking at

is the nMOS threshold voltage), a condition occurring over a Fig. 2(a), in the first half of the oscillation cycle when and

small fraction of the oscillation period. The tank current is then are conducting, the drain currents are

made of short and tall current pulses with a fundamental com-

ponent roughly equal to , i.e., 3.9 dB larger than in the case

without , where transistors are active for half the oscilla-

tion period and the tank current resembles very closely a square (4a)

wave with a fundamental component of . As discussed

thoroughly in [14], to preserve the pulsed current shape, it is (4b)

very important that the nMOS transistors do not enter the triode

region. Therefore, to maximize the allowed tank voltage swing, where and (where

an RC network is introduced to provide a bias voltage to the is the electron/hole mobility, is the gate-oxide ca-

gates ( ) lower than the tank common-mode voltage. pacitance per unit area, and and are the transistor width

Turning to the complementary topology in Fig. 1(b), the and length, respectively), while and

nMOS transistors deliver current pulses to the differential tank, (where is the gatesource

and the same pulses flow through the cross-coupled pMOS pair. voltage of the n/pMOS transistor) are the average overdrive

Under steady-state conditions, the voltage waveform across the voltages in steady state for the nMOS and pMOS transistors,

tank settles so that opposite nMOS and pMOS transistors have respectively.

exactly the same conduction angle and current shape. The tank From (1) and (2), . Re-

voltages, transistor conduction angle, and current shape are placing the latter in (4b) and solving leads to

then determined by the aspect ratios of both nMOS and pMOS

transistors. To gain insight, Fig. 2 highlights the transistors

conducting current in the two half-cycles of one oscillation

(5)

period. The single-ended tank voltages can be written as

2The adopted notation here is different from [14]. The pushpull Class-C os-

(1a) cillator has a single differential tank while the resonator of the single-differential

pair Class-C oscillator in [14] is made of two single-ended tanks. The amplitude

(1b) calculated in [14] is for one of the two tanks.

726 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

enter the triode region, for different transistors gains.

the pMOS transistor. In the second half of the period, the situa-

Fig. 3. Voltage and current waveforms in the pushpull Class-C oscillator with tion is reversed.

transistors working always in saturation (solid curves) and with pMOS transis- The device conduction angle ( ) and the fundamental com-

tors entering deeply into the triode region (dotted curves). ponent of the drain current ( ) can be derived from (4)(6)

following the same approach presented in [28] for the analysis

of the CMOS Colpitts oscillator, leading to

(6a)

(8)

(6b)

(9)

Interestingly, if nMOS and pMOS transistors have different An analysis of the circuit if the pMOS transistors enter the triode

gains (i.e., ), the peak values of the tank voltages region is much more involved, and does not lead to simple

expressed by (6) are different. For symmetry, the analysis of closed-form equations. The intuitive view discussed above is

the circuit in the second half of the oscillation period, i.e., for nevertheless still useful to explain the behavior in this case. The

, when and are active, as depicted in results of a simulation with 0.25 V are shown with

Fig. 2(b), leads to tank voltages with opposite magnitude as the dotted lines in Fig. 3. The gain of the pMOS transistors is

now much lower, since they operate in triode for most of the

time, but the drain current shape must still match the drain cur-

rent of the opposite nMOS transistors. As a result, the ampli-

tude of the tank voltage driving the nMOS transistors (i.e.,

and in the first and second half of the period respectively)

(7)

drops significantly. As shown by the bottom plots in Fig. 3,

the conduction angle of the devices increases and the drain cur-

rent pulses are widened, losing the high dc-to-RF conversion

The above analysis has been checked by means of circuit sim-

efficiency of the narrow pulses. To gain further insight, Fig. 4

ulations reported in Fig. 3. The continuous lines represent the

plots the simulated magnitude of the fundamental component of

tank voltages (top plot) and the MOS currents (bottom plot) for a

the drain current normalized to the bias current (i.e., )

design where 0.9 V, 1.2 mA, and .

versus for different gain factors of the transistors. For

The supply voltage is adjusted for a steady-state common-mode

, the pMOS transistors do not leave the saturation

tank voltage 1 V, and the threshold of the pMOS tran-

region, while for they enter gradually into the

sistors has been artificially increased to 1 V by means of a dc

triode region; the lower , the larger the fraction of the

voltage source in series with the pMOS gates to avoid triode

oscillation period with pMOS transistors in triode. The current

operation. The simulated tank voltages are in very good agree-

conduction angle increases with decreasing , gradu-

ment with (6) and (7) and the difference between positive and

ally losing the high dc-to-RF conversion efficiency. In the limit

negative peaks, due to the different gains of pMOS and nMOS

case of , the conduction angle is approximately

transistors, is clearly evident. The origin of this asymmetry finds

and , which is the same as in the standard

also a very intuitive explanation. Since the circuit forces the

complementary CMOS oscillator.

same current in opposite nMOS and pMOS transistors, different

voltage amplitudes are required to compensate for the different

transistor gains. Focusing for example on the first half of the os- III. PHASE NOISE

cillation period, since the nMOS has more gain than the pMOS Following the linear time-variant (LTV) analysis approach

transistor ( ), the voltage driving the nMOS proposed by Hajimiry and Lee, the phase noise of a generic

MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 727

harmonic oscillator at an offset frequency from the carrier that is twice the amplitude that would be available with a single

can be expressed as [8], [29], [30] differential pair, yielding .

The effective noise contributed by each active pair is there-

fore

(10) (14)

where is the oscillation amplitude across the resonator, al-

negligible, since its white noise is almost totally filtered out by

ready introduced in (2), is the tank capacitance, and, for white

the large tail capacitance required for Class-C operation. This

noise sources, (simply referred to as effective noise here-

is a further significant advantage of the Class-C oscillator com-

after) is given by

pared to the traditional differential pair topology, where the con-

tribution of the biasing transistor to phase noise is in general

(11)

non-negligible [12], [28].

Finally, the oscillation amplitude is given by the product

where is the oscillation period, is the white current of the tank resistance and the fundamental current component,

noise power spectral density (either stationary or cyclo-sta- , which is the sum of the nMOS and pMOS currents, i.e.,

tionary) produced by the th device, and is the corre- twice the current given by (9),

sponding impulse sensitivity function (ISF), encoding the

time-dependent sensitivity of the phase of the oscillation to (15)

. It has been shown that the ISF of the noise current

Substituting (12), (14), and (15) into (10), the closed-form

source associated with the tank loss resistance is, with very

phase-noise expression for the pushpull Class-C oscillator is

good approximation, a sinusoid in quadrature with the tank

voltage and with a magnitude inversely proportional to the

number of resonators in the oscillator [31]. Since we have

assumed a sinusoidal tank voltage with zero initial phase [see (16)

(2)] and the oscillator in Fig. 1(b) comprises a single resonator, The results of the phase-noise analysis have been compared

the tank ISF is . The stationary current against Spectre-RF simulations for a design example where we

noise power spectral density of the tank loss resistance ( ) have assumed a tank inductance of 1 nH with a quality factor

is (where and are the Boltzmans , 600 fF, 1.2 mA. The oscillation fre-

constant and the absolute temperature, respectively) and the quency is 6.5 GHz. The bias voltage for the nMOS transis-

tank effective noise follows immediately by calculating tors has been selected to avoid their entering the triode region.

the integral of (11) to yield The simulated oscillation amplitude, effective noise contribu-

tions and phase noise at 2 MHz offset from the carrier are re-

(12) ported in Table I for different values of . The effective

noise contributions predicted by (12) and (14) are

10 A Hz and, assuming , we obtain

To calculate the effective noise produced by the thermal noise

of nMOS and pMOS pairs, we can exploit the powerful general

property of phase noise in harmonic oscillators presented in [14]

A

and [32]. In particular, it has been proved that, if the core tran-

Hz

sistors do not leave the active (saturation) region, their effective

noise is independent of transistor type, size, and shape of the The calculated phase noise by (16) is 125.3 dBc/Hz. These re-

drain current, but depends only on the oscillator topology and sults are in very good agreement with simulations, reported in

can be related to the tank effective noise by means of the fol- the first row of Table I, for , i.e., with pMOS tran-

lowing equation: sistors not leaving the saturation region. The small discrepancy

( 1 dB) between calculated and simulated phase noise is due

(13) to the approximation in (9), which leads to a slight

overestimation of the oscillation amplitude in (15). In particular,

where is the proportionality constant linking the transistors the calculated is 990 mV, which is 1 dB higher than the

thermal noise to their transconductance, is the ratio between simulated value of 890 mV.

the voltage swing at the output of the active pair to the oscilla- More interestingly, these simulations point out a gradual de-

tion amplitude across the tank, and is the ratio between the terioration of phase noise if the pMOS transistors are allowed

voltage swing driving each active pair to the tank voltage. In to enter the triode region, rising up to 7 dB in the limit case of

the pushpull oscillator of Fig. 1(b), there are two distinct dif- . The reason is twofold: 1) the reduction of the os-

ferential pairs driving the resonator. Obviously, because cillation amplitude, reported in Table I, which is due to the much

the differential output of each pair is directly connected to the lower DC-to-RF current conversion efficiency, as discussed in

tank. On the other hand, the use of two complementary active the previous section, and 2) a significant increase, of more than

pairs leads to a feedback oscillation amplitude across each pair four times, of the effective noise generated by the transistors. It

728 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

TABLE I

SIMULATED OSCILLATION AMPLITUDE, NOISE CONTRIBUTIONS, AND PHASE

NOISE OF THE PUSHPULL CLASS-C OSCILLATOR FOR DIFFERENT VALUES

OF

is worth noticing the proportional increase of both nMOS and Fig. 5. Pushpull Class-C oscillator modified to accommodate a large voltage

pMOS contributions, even if the former never leave the satura- swing.

tion region. The primary mechanism behind the increased con-

tribution of transistors effective noise is the larger current con-

duction angle, when pMOS transistors enter the triode region, as waveforms depicted in Fig. 5. During the first half of the os-

previously shown in Fig. 3. As a result, both nMOS and pMOS cillation cycle, transistors and are pushed toward the

transistors inject thermal noise into the tank over a wider frac- triode region. The boundary condition for saturation of ,

tion of the oscillation period, leading to a larger integral noise , can be written as

expressed by (11). , where and are the peak voltage

We have focused our attention on the transistors of the pMOS magnitudes at the two tank nodes in the first half of the oscilla-

pair, but the same discussion, with similar qualitative results, is tion cycle, as shown in Fig. 5. Given the differential oscillation

also valid for the transistors of the nMOS pair. For an optimal amplitude , the minimum required to

phase-noise performance, it is therefore very important to avoid keep in saturation is

any transistors entering the deep triode region.

(17)

IV. PUSHPULL CLASS-C OSCILLATOR FOR

Looking now at , the saturation condition

LARGE VOLTAGE SWING

requires . Assuming the

To avoid excessive phase noise penalty, the zero-peak differ- external bias voltage for the nMOS pair is selected at the min-

ential voltage swing across the resonator must be comparable imum possible value, i.e., ,

or lower than a pMOS threshold voltage. While this limitation where is the minimum voltage to keep the tail current

can be acceptable in ultrascaled technologies having a supply source in saturation), the upper bound for the tank voltage swing

voltage of 1 V with 0.50.6-V high- transistor options, it is:

represents a significant penalty for realizations in less scaled

technology nodes. A modified pushpull Class-C oscillator ac- (18)

commodating a larger voltage swing is presented in Fig. 5. An

additional RC network is introduced to provide a dc bias voltage The tank steady-state dc common-mode voltage is set by the

for the gates of the pMOS pair ( ) higher than the tank pMOS pair and the level shifter

common-mode voltage, allowing a larger resonator swing be-

(19)

fore the pMOS pair is pushed into the triode region. This is the

same technique adopted to bias the nMOS pair, with the differ- Assuming is selected at the optimal value given by (17),

ence that is not applied externally, but is generated by and replacing (19) in (18), the constraint on the maximum tank

offsetting upward the tank common-mode voltage, , by voltage swing to ensure transistors do not enter the triode region

, with transistor working as level shifter. This is nec- is

essary to preserve a low common-mode tank impedance and a

well-defined common-mode voltage. The power required to bias

the level shifter is negligible, compared with the overall dissi-

pation in the oscillator. (20)

By selecting a moderately high time constant for the RC bi-

asing networks, the noise impressed on and the noise The absolute value of and is introduced in the last

generated by the level shifter providing are low-pass fil- expression to highlight that the steady-state overdrive voltage of

tered and do not deteriorate the oscillator phase noise. nMOS (pMOS) transistors working in Class-C is negative (pos-

itive). For practical transistor sizes, the magnitude of the over-

A. Maximum Oscillation Amplitude drives is in the range of 50100 mV. The tail current source

To estimate the optimal design value for and the max- transistor in the Class-C oscillator can be sized very large, since

imum allowed oscillation amplitude, we refer to the voltage its drain parasitic capacitance is absorbed in . The required

MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 729

minimum drain voltage for saturation ( ) is therefore of the robustness against single-ended tank capacitance, lead to

the order of 100 mV or even less, leading to a maximum tank a significant improvement of the spectral purity for a given

voltage swing, from (20), which is roughly half of the supply power dissipation in favor of the Class-C oscillator. This will

voltage.3 This is nevertheless quite a pessimistic estimate. In be also evident from the comparison of experimental results

fact, in deep-submicron technologies, the velocity saturation of against the performances of recently reported complementary

the charge carriers prevails on the channel pinch-off to deter- LC-tank oscillators, presented in Section V.

mine saturation of the drain current, and a magnitude of

lower than what has been assumed in the above derivation is

therefore sufficient to keep the transistors in the active region. V. EXPERIMENTAL RESULTS

A VCO based on the large-swing Class-C topology of Fig. 5

B. Comparison With the Standard Complementary has been designed in 0.18- m CMOS. To keep a low VCO

Differential-Pairs CMOS Oscillator gain, the tank capacitance is made of a small varactor for fine

The maximum theoretical oscillation amplitude for the stan- tuning and a bank of four digitally switched and binary-sized

dard LC-tank oscillator with complementary differential pairs metal-fringe capacitors for coarse tuning. The 1-nH inductor is

is - [27]. Thus, this oscillator theoretically allows a two-turn coil, and the estimated tank is 10. From (20), the

a larger maximum amplitude than the pushpull Class-C os- optimal oscillation amplitude is approximately half of the

cillator of Fig. 5. However, it should be noticed that, unlike supply voltage. Given a nominal supply of 1.8 V, the biasing

in the Class-C oscillator, cannot be selected below current is set to 1.2 mA, leading to a simulated of

a few hundred millivolts, because the tail-current-source tran- 900 mV. The aspect ratio of the nMOS ( - ) and pMOS

sistor must be designed with a relatively small aspect ratio and a ( - ) core transistors is, respectively, 42 m/0.18 m and

correspondingly large overdrive voltage to yield a low transcon- 60 m/0.18 m. Transistor is 15 m/0.2 m and is biased

ductance, since its high-frequency thermal noise (proportional close to the threshold voltage with a 10- A current, providing

to its transconductance) is not filtered out, impacting the os- a voltage shift of 470 mV. The VCO drives directly a pair

cillator phase noise [28]. Furthermore, the noise from the of open-drain buffers, supplied off-chip with bias-tees, to drive

tail-current-source transistor is an issue as well [12]. the 50- impedance of the measurement setup.

The phase noise of the standard complementary oscillator is The tail current source is realized with a transistor

also severely impaired by capacitors connected single-ended having an aspect ratio of 500 m/0.8 m. A nonminimum

to the resonator, i.e., capacitors connected between the differ- channel length is selected to limit the generation of

ential outputs and ground [15], [27]. Assuming a tail-biased noise, which would be (at least partially) translated into

standard complementary oscillator topology, at large oscilla- phase noise. At the same time, the very large width leads

tion amplitude the on-resistance of the pMOS transistors, en- to a minimum drain voltage for saturation, of only

tering the triode region, appears in parallel to the single ended 80 mV. The total tail capacitance , comprising the parasitic

tank capacitors, thus degrading the loaded tank and there- drain junction capacitance of the tail transistor and an explicit

fore phase noise. In a typical design, this mechanism leads to a metal-fringe capacitance, is 1.1 pF. This value is sufficiently

significant phase noise penalty if the single-ended capacitance large to keep an almost constant steady-state tail voltage, the

is a non-negligible fraction of the total tank capacitance [27] fundamental condition for Class-C operation of the core tran-

(and up to 10-dB penalty in the case of 100% single-ended sistors. On the other hand, similar to the single-differential-pair

tank capacitance [15]). This issue leads to a severe tradeoff be- Class-C oscillator, too large a tail capacitance would lead to an

tween frequency tuning range and phase noise, since the com- instability of the oscillation amplitude, a phenomenon referred

ponents mostly responsible for introducing single-ended tank to as squegging [14]. Simulations indicate that squegging

capacitances are the varactors in the case of continuous fre- appears for 1.7 pF, indicating a sufficiently safe sta-

quency tuning, and, if a switched-capacitor bank is used for dis- bility margin with 1.1 pF. No squegging is observed

crete tuning, the parasitic capacitances of the switches [7]. How- in measurements.

ever, since the core transistors of a correctly designed pushpull Fig. 6 shows the chip photograph. The die area, including

Class-C oscillator never leave the saturation region, its pMOS pads, is 650 m 430 m. Fig. 7 shows the tuning curves. The

transistors cannot discharge the single-ended parasitic capaci- VCO is tunable from 6.09 to 7.50 GHz in 16 widely overlapping

tances, allowing a large frequency tuning range without a sig- bands. The maximum gain, at the center of the tuning curves,

nificant phase-noise penalty. ranges from 110 to 164 MHz/V.

In summary, even if the maximum oscillation amplitude Phase-noise measurements are carried out with 1.8 V

for the standard complementary differential-pair oscillator is and a current consumption of 1.2 mA, corresponding to a power

theoretically larger than for the Class-C oscillator, the higher dissipation of 2.16 mW. Fig. 8 shows a typical phase-noise plot.

dc-to-RF current conversion efficiency, the use of a large The bias voltage for the nMOS pair , provided off-chip,

explicit capacitance at the common-source node, allowing a is set to a nominal value of 0.65 V. This value, which is slightly

very low and filtering-out the bias current noise, and higher than the optimal minimum value calculated in the pre-

vious section, sets a small-signal device transconductance suffi-

3The maximum tank voltage swing of the pushpull Class-C oscillator is half

ciently large to ensure a robust oscillator start-up. On the other

that of the originally reported Class-C oscillator based on a single differential

pair [14]. Following the same analysis reported in [27], the two oscillators have hand, as it has been discussed in [14] for the single-differential-

the same maximum phase noise FoM. pair Class-C oscillator, the sensitivity of phase noise to

730 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

200-kHz, 2-MHz, and 20-MHz offset from the carrier in each subband of the

pushpull Class-C VCO.

culated at 2 MHz or 20 MHz, ranges from 189 to

191 dBc/Hz across the tuning range.

is very low and no appreciable phase noise variations are ob- Finally, measurement results are summarized and compared

served for ranging from 0.6 to 0.7 V. Eventually, a ded- with recently reported complementary oscillators (i.e., oscil-

icated start-up circuit, as proposed recently for the single-dif- lators employing both nMOS and pMOS transistor pairs) fea-

ferential-pair Class-C oscillator, may be adopted to further op- turing a tuning range of more than 10% in Table II. The designs

timize the design [19][23]. in [26] and [33] are standard complementary oscillators with a

The measured phase noise at different offset frequen- pMOS top biasing current source. In [34], a filtering technique

cies, in each subband of the VCO, is compared with sim- for the bias noise employing an additional inductor is used. In

ulations in Fig. 9. The measured phase noise at 200-kHz, [35] the tail transistor is removed, while in [36] it is replaced by

2-MHz, and 20-MHz offsets ranges, respectively, from 97.5 a pair of parallel LC resonators. The best peak phase-noise FoM,

to 101 dBc/Hz, 120 to 123 dBc/Hz, and 140.3 to among all realizations, is 187 dBc/Hz. On average, the FoM of

143.4 dBc/Hz. The phase noise corner is slightly the Class-C complementary topology is more than 3 dB higher,

larger than expected, as visible in Fig. 9 by the larger dis- meaning that, for the same oscillation frequency and phase noise

crepancy between measurements and simulations at 200-kHz target, the proposed solution saves more than half of the power.

offset, where noise is dominant. Possibly, this is caused Yet another popular (albeit somewhat arbitrary) figure-of-

by wanting device noise models. The smaller discrep- merit takes into account the tuning range TR as well, and is

ancy between measurements and simulations in the defined as , where is ex-

region, at 2-MHz and 20-MHz offsets, is likely due to a pressed in percent. Also in this case the push-pull Class-C VCO

slight overestimation of the tank quality factor. The FoM compares well with the state-of-the-art (see Table II again),

normalizing oscillation frequency ( ), power dissipa- especially if we consider the high frequency of operation and

tion ( ), and phase noise at the offset frequency , the rather old technology used.

MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 731

TABLE II

PERFORMANCE SUMMARY AND COMPARISON WITH RECENTLY REPORTED CMOS VCOS EMPLOYING COMPLEMENTARY DIFFERENTIAL PAIRS

CMOS VCOs using transformer feedback, IEEE J. Solid-State

Complementary VCOs are preferable, in some circum- Circuits, vol. 40, no. 3, pp. 652659, Mar. 2005.

stances, to topologies employing a single differential pair. A [14] A. Mazzanti and P. Andreani, Class-C harmonic CMOS VCOs, with

Class-C VCO adopting CMOS differential pairs in a pushpull a general result on phase noise, IEEE J. Solid-State Circuits, vol. 43,

no. 12, pp. 27162729, Dec. 2008.

configuration has been introduced and analyzed, providing [15] D. Murphy, J. J. Rael, and A. A. Abidi, Phase noise in LC oscillators:

insight on circuit operation and phase noise. It has been shown A phasor-based analysis of a general result and of loaded , IEEE

that, for an optimal phase noise performance, transistors must Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, pp. 11871203, Jun.

2010.

not leave the saturation region. A simple technique, requiring [16] P. Nuzzo, K. Vengattaramane, M. Ingels, V. Giannini, M. Steyaert, and

negligible additional dissipation, has been proposed to accom- J. Craninckx, 5 GHz dual-VCO software-defined frequency syn-

modate large voltage swing. As confirmed by experimental thesizer in 45 nm digital CMOS, in Proc. IEEE Radio Frequency In-

tegr. Circuits Symp., 2009, pp. 321324.

results, thanks to the high dc-to-RF current conversion effi- [17] V. Giannini, P. Nuzzo, C. Soens, K. Vengattaramane, J. Ryckaert, M.

ciency and the large tail capacitance, explicitly required for Goffioul, B. Debaillie, J. Borremans, J. Van Driessche, J. Craninckx,

Class-C operation, which filters out the bias noise, the proposed and M. Ingels, A 2-mm 0.15 GHz software-defined radio receiver

in 45-nm digital CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 12,

VCO displays an improved phase-noise performance compared pp. 34863498, Dec. 2009.

with the widely adopted standard topology of the complemen- [18] M. Tohidian, A. F.-Ahmadi, M. Kamarei, and F. Ndagijimana, High

tary differential-pair oscillator. swing class-C VCO, in Proc. Eur. Solid State Circuits Conf., 2011,

pp. 495498.

[19] J. Chen, F. Jonsson, M. Carlsson, C. Hedens, and L.-R. Zheng, A

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2002.

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[32] J. Bank, A Harmonic-Oscillator Design Methodology based on De- over 50 technical papers. His main research interests cover device modeling

scribing Functions, Ph.D. dissertation, Dept. Signals and Syst., Sch. and IC design for high-speed communications and millimeter-wave systems.

Electr. Eng., Chalmers Univ. Technol., Gteborg, Sweden, 2006. Dr. Mazzanti has been a member of the Technical Program Committee of the

[33] T. Tokairin, M. Okada, M. Kitsunezuka, T. Maedaand, and M. IEEE Custom Integrated Circuit Conference (CICC) and the IEEE International

Fukaishi, A 2.1-to-2.8-GHz low-phase-noise all-digital frequency Conference on IC Design and Technology (ICICDT) since 2008. He is currently

synthesizer with a time-windowed time-to-digital converter, IEEE J. serving as an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND

Solid State Circuits, vol. 45, no. 12, pp. 25822590, Dec. 2010. SYSTEMSI: REGULAR PAPERS.

[34] J. Shin and H. Shin, A 1.93.8 GHz fractional- PLL frequency syn-

thesizer with fast auto-calibration of loop bandwidth and VCO fre-

quency, IEEE J. Solid State Circuits, vol. 47, no. 3, pp. 665675, Mar.

2012. Pietro Andreani (SM07) received the M.S.E.E. de-

[35] S. Levantino, M. Zanuso, C. Samori, and A. Lacaita, Suppression of gree from the University of Pisa, Pisa, Italy, in 1988,

flicker noise upconversion in a 65 nm CMOS VCO in the 3.0-to-3.6 and the Ph.D. degree from Lund University, Lund,

GHz band, in IEEE Int. Solid State Circuits Conf. Dig. of Tech. Papers, Sweden, in 1999.

Feb. 2010, pp. 5051. Between 2001 and 2007, he was Chair Professor

[36] D. Ponton, G. Knoblinger, A. Roithmeierl, M. Tiebout, M. Fulde, and with the Center for Physical Electronics, Tech-

P. Palestri, Assessment of the impact of technology scaling on the nical University of Denmark. Since 2007, he has

performance of LC-VCOs, in Proc. Eur. Solid State Circuits Conf., been an Associate Professor with the Department

Sep. 2009, pp. 364367. of Electrical and Information Technology, Lund

University, Lund, Sweden, where he is involved

Andrea Mazzanti (M09) received the Laurea and with analog/mixed-mode/RF IC design. He is also a

Ph.D. degrees in electrical engineering from the Uni- part-time IC Designer with ST-Ericsson, Lund.

versit di Modena and Reggio Emilia, Modena, Italy, Prof. Andreani has been a TPC member of ISSCC (20072012) and is a TPC

in 2001 and 2005, respectively. member of ESSCIRC.

During the summer of 2003, he was with Agere

Systems, Allentown, PA as an Intern. From 2006

to 2009, he was an Assistant Professor with the

Universit di Modena and Reggio Emilia, Modena,

Italy, where he taught a course on advanced analog

IC design. In January 2010, he joined the Universit

di Pavia, Pavia, Italy. He has authored or coauthored

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