23rd International Conference on Electricity Distribution
Paper 0480
ADVANCED VECTOR SHIFT ALGORITHM FOR ISLANDING DETECTION
Murali KANDAKATLA Hannu LAAKSONEN
ABB GISL India ABB Oy Finland
murali.kandakatla@in.abb.com hannu.laaksonen@fi.abb.com
ABSTRACT
In order to improve the reliability of vector shift based
islanding detection an advanced vector shift algorithm has
been developed. This algorithm can use all three phase
voltages or a positive sequence voltage for vector shift
detection and will not cause nuisance tripping of DG units
due to other network disturbances. To validate the
developed algorithm, a medium-voltage (MV) distribution
network with DG units has been modelled in the PSCAD
simulation software. The algorithm is validated for its
dependability, stability and fast operation with simulated
real islanding and different non-islanding events like
faults, capacitor switching and connection of a parallel
transformer.
INTRODUCTION
One of the key protection functionalities in Smart Grids
will be reliable detection of islanding (or loss-of-mains,
LOM). Although the trend in new grid codes is to require
fault-ride-through (FRT) capability from distributed
generation (DG) units and possibly also to allow island
operation, there is still a need to reliably detect the
islanding situation to make the correct operations, such as,
change the setting group of a DG interconnection relay or
change the control principles and parameters of a DG unit.
Non-detection zone (NDZ) near power balance situations
and unwanted DG trips due to other network events
(nuisance tripping) have been the major challenges with
traditional passive local islanding detection methods. If the
number of DG units in the distribution networks increases,
as is expected in the future, the risk of power balance
situations will also increase. Therefore, the risk of possible
operation in the NDZ of the traditional passive islanding
detection methods also will increase. In addition, f, U and
rate-of-change-of-frequency (ROCOF) will be used more
often for defining the DG unit FRT requirements in the
new grid codes to enable utility grid stability supporting
functionalities from DG units [1], [2].
Due to the above-mentioned reasons in [1], a new, future-
proof, passive islanding detection algorithm without NDZ
has been proposed. On the other hand, in [2] it has been
proposed that centralized active network management
functionalities (CANM) at the MV level, like voltage
control or losses minimization, could in the future include
an algorithm which, in real time, confirms the operation of
reliable islanding detection, even based on passive
methods like voltage phase angle-based methods or
voltage vector shift. The algorithm proposed in [2]
continuously ensures that there is enough reactive power
unbalance that the operation point remains constantly
outside the NDZ of the used islanding detection method.
CIRED 2015
Lyon, 15-18 June 2015
Sudheer BONELA
ABB GISL - India
b.sudheer@in.abb.com
The focus of this paper is on development of traditional
passive islanding detection based on voltage vector shift.
Voltage vector shift is still used for islanding detection in
many countries, although in Europe some countries, such
as Germany and Denmark, have forbidden its use for LOM
detection due to its sensitivity to nuisance tripping.
However, in order to improve the reliability of vector shift
based islanding detection (no or less nuisance tripping of
DG units due to other network events), an advanced vector
shift algorithm has been developed and is presented in this
paper.
This algorithm uses all three phase voltages or positive
sequence voltage for vector shift detection and will not
cause nuisance tripping of DG units due to other network
disturbances.
To validate the developed algorithm, a MV distribution
network with DG units has been modelled in the PSCAD
simulation software. The algorithm is validated for its
dependability, stability and fast operation with simulated
real islanding and different non-islanding events like
faults, capacitor switching and connection of a parallel
transformer. The developed vector shift algorithm is also
implemented to the intelligent electronic device (IED) and
the behavior of the algorithm is validated by injecting the
simulated COMTRADE-files through an IED test setup.
In the following sections, the basic vector shift principle
and the developed advanced vector shift algorithm are
shown first. After that, the study network and example
simulation results are presented followed by conclusions.
PROPOSED ADVANCED VECTOR SHIFT
ALGORITHM
Basic vector shift principle
The principle of voltage vector shift after islanding is
explained with the help of the following system example.
Figure 1 shows a synchronous generator equipped with a
vector shift relay operating in parallel with a distribution
network.
_ _ _
V Is VS Relay CB IGr
Xd Grid
_
EI _
LOAD
VT
Figure 1. Equivalent circuit of a synchronous generator operating in
parallel with the grid
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Paper 0480

When the generator current Is is passing through the voltages (when all three phase voltage are used). The
generator reactance Xd, there is a voltage difference V vector shift algorithm is blocked, when any of the
between the terminal voltage VT and the generator internal measured voltages drop below or increase above the
voltage EI (Figure 1). Consequently, there is a threshold values.
displacement angle between the terminal voltage and START
generator internal voltage. The phasor diagram is shown in U_AB Signal
Figure 2(a). After the circuit breaker opens, the system U_BC Signal
AngDif_AB = ABS(FFT angle(U_AB)t=0 FFT angle(U_AB)t= 2cycles old)
AngDif_BC = ABS(FFT angle(U_BC)t=0 FFT angle(U_BC)t= 2cycles old)
consisting of the generator and load becomes islanded. At U_CA Signal AngDif_CA = ABS(FFT angle(U_CA)t=0 FFT angle(U_CA)t= 2cycles old)
U1 Signal AngDif_U1 = ABS(FFT angle(U1)t=0 FFT angle(U1)t= 2cycles old)
this same time instant, the synchronous generator begins Fm - Measured
to feed a larger (or smaller) load because the current IGr frequency
FN - Nominal IF {(Fm)t=0 (Fm)t=5 cycles old} < 0.001 FN, THEN FStable = (Fm)t=5 cycles old
frequency CorrectionAngle = (FN -FStable)x2x360.
provided by the grid is interrupted. Due to this, the angular
difference between VT and EI is suddenly increased (or
decreased) and the terminal voltage phasor changes its Fstable > FN + 2.5 Hz
YES
OR
position as shown in Figure 2(b). The sudden vector shift Fstable < FN 2.5 Hz
due to islanding can also be seen in the voltage waveform
NO
in Figure 2(c). VSAng_AB = AngDif_AB + CorrectionAngle
VSAng_BC = AngDif_BC + CorrectionAngle
VSAng_CA = AngDif_CA + CorrectionAngle
VSAng_U1 = AngDif_U1 + CorrectionAngle

YES VSAng_AB > NO

Vector shift angle

YES VSAng_BC > NO

OR AND
Vector shift angle

YES VSAng_CA > NO

Vector shift angle

U_AB Signal
U_CA Signal

U_BC Signal
U1 Signal

Out of three phases, if any one of the phase detects vector shift, the
Occurrence of LOM algorithm is initiated.
V(t)

Vector shift algorithm

blocking based on measured
voltages UV Block After detection of Vector shift
in first phase, with in 10 ms YES
OR
is any of the blocking conditions
t activated?
OV Block
U_AB or U_BC or
U_CA
< Under voltage value NO

(c) Change in angle

After detection of Vector shift
Figure 2. Internal and terminal voltage phasors: (a) before islanding (b) in first phase, with in 1 cycle time NO

are all the three phases detected

after islanding. (c) vector shift in voltage waveform U_AB or U_BC or the vector shift ?
U_CA
Generally, vector shift relays measure the duration of each > Over voltage value
As a blocking condition is detected, the algorithm
is blocked internally and the binary output
cycle of the voltage signal from each phase. The duration INT_BLKD is activated.
of the present cycle is compared with the previous cycle YES

(which is considered as reference). In an islanding This confirms the ISLANDING condition.

The algorithm Issues a binary pulse of fixed 100 ms Vector shift operate
situation, the cycle duration is either shorter or longer OPERATE

depending if there is excess or deficit of active power in

the islanded system. If the measured vector shift angle
STOP

in the terminal voltage exceeds a predetermined threshold

, a trip signal is immediately sent to the circuit breaker.
Some further analysis and comparisons related to different
vector shift algorithms etc. can be found from references
[3]-[5].
Advanced vector shift algorithm
The proposed advanced vector shift algorithm is presented
in the form of a flowchart in Figure 3. This new algorithm
uses all three phase voltages or a positive sequence voltage
for vector shift detection. The developed algorithm takes
simultaneously into account the behavior of voltage and
frequency, adapts to steady-state frequency variations and
has time-dependent correlation checks between phase
Figure 3. Flowchart of the developed advanced vector shift algorithm
VALIDATION OF DEVELOPED NEW
VECTOR SHIFT ALGORITHM
Study network
A typical MV distribution network with DG units has been
modelled in the PSCAD simulation software (Figure 4). In
the study network, the HV network is at 110 kV, the MV
network at 21 kV and the LV network at 0.4 kV voltage
levels. The load is mainly constant impedance-based
passive load (cos()=0.965 with larger MV island and
cos()=0.98 with smaller MV island and cos()=0.9725
with cable lines), and small part of the load is constant

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Paper 0480

power load. The system line types and line parameters are vector shift angle behaviour and binary output signals
also presented in Figure 4. Simulations were done with a (operate and internal blocking) for vector shift algorithm
directly connected synchronous generator (SG) based DG are presented.
unit at the MV feeder and other DG units as well as de- Voltage magnitude in three phases

Voltage(pu)
centralized compensation coils were disconnected (Figure 1
U AB
U BC
4). U CA
0.8
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s)
Vector shift angle detected in three phases

Angle(Degrees)
30
VSAng AB
20
VSAng BC
10
VSAng CA
0
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s)
Vector shift algorithm Operate and Blocked signals

Binary outputs
1
OPERATE
0.5 INT BLKD
0
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s)

Figure 5. Vector shift algorithm operation during islanding in small

power unbalance

From Figure 5, it can be seen that after islanding at 20.0 s,

Figure 4. Study network used in PSCAD simulations
The advanced vector shift algorithm is tested for its
dependability and stability in different simulation cases.
The simulated islanding cases consist of testing the
dependability of the algorithm in cases where the
algorithm is supposed to operate. All these islanding cases
the vector shift angles start to increase in all three phases.
After the detected vector shift angle has increased above
the pick-up setting, the algorithm issues an OPERATE
pulse output at around 20.25 s, because no blocking
conditions have been activated.
Islanding in Large Power Unbalance
This case is similar to the previous one, but the power
unbalance before islanding is now larger (Figure 6).
Voltage magnitude in three phases
1
Voltage(pu)

U AB
0.5 U BC
are simulated by opening the MV feeder CB (A in Figure U CA
4) or the recloser CB (B in Figure 4) at time 20.0 s and 0
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s)
by closing the CB 0.3 s later i.e. at 20.3 s. The faults and Vector shift angle detected in three phases
Angle(Degrees)

200
other network disturbances related simulation cases, i.e. VSAng AB
100 VSAng BC
cases where the algorithm should not operate, were done 0
VSAng CA
19.9 20 20.1 20.2 20.3 20.4 20.5
to test the stability of the algorithm. Time(s)
Vector shift algorithm Operate and Blocked signals
Binary outputs

During the PSCAD simulations from different cases, the 1

OPERATE
0.5 INT BLKD
phase-to-phase voltage measurements (UAB, UBC, UCA)
0
from the MV network and the LV network are recorded to 19.9 20 20.1 20.2
Time(s)
20.3 20.4 20.5

a COMTRADE-file format. The proposed algorithm is
tested with these voltage measurements from different
simulated cases and the results are presented in the
following sections. During the testing, the algorithm pick-
up value setting, i.e. vector shift angle, was 5 degrees and
the algorithm blocking settings for undervoltage was 0.80
pu and for overvoltage 1.2 pu.
Real Islanding Cases
Islanding in Small Power Unbalance
When islanding in small power unbalance, the local
generation is a bit larger (or smaller) than the local load in
the MV network. When the generation is larger than the
load, the power is exported to the utility grid. Respectively,
if the local generation is smaller than the local load, then
the deficit power is imported from the utility grid.
However, results for the vector shift algorithm are similar
in both cases if the size of the power unbalance is equal. In
Figure 5, phase-to-phase voltage magnitudes, voltage
Figure 6. Vector shift algorithm operation during islanding in large
power unbalance
From Figure 6, one can see that after islanding at 20.0 s,
the vector shift angles start to increase in all three phases.
When compared with the islanding in small power
unbalance, the vector shift can now be detected faster as
expected. In this case, the algorithm issues an OPERATE
pulse output at around 20.05 s.
Faults and Other Network Disturbances
Phase-to-Earth Fault
In this case, the phase-to-earth (A-G) fault for 150 ms, is
applied in the middle of the same MV feeder (viii in
Figure 4), i.e. 15 km from the recloser CB. Fault resistance
Rf = 1000 . In Figure 7, phase-to-phase voltage
magnitudes, voltage vector shift angle behavior and binary
output signals for vector shift Operate and blocking are
presented.
From Figure 7, it can be observed that during the A-G

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Paper 0480

Voltage magnitude in three phases

fault, the vector shift angles are only 0.3 degrees in two

Voltage(pu)
1 U AB
phase-to-phase voltages (UAB, UCA). Because the detected 0.5 U BC
vector shift angles are less than the pick-up setting and the U CA
0
19.9 20 20.1 20.2 20.3 20.4 20.5
vector shift is not detected in all three phases, the Time(s)
Vector shift angle detected in three phases

Angle(Degrees)
developed vector shift algorithm is not operated. 80
VSAng AB
40 VSAng BC
Voltage magnitude in three phases
0.97 VSAng CA
Voltage(pu)

U AB 0
19.9 20 20.1 20.2 20.3 20.4 20.5
0.96 U BC Time(s)
U CA Vector shift algorithm Operate and Blocked signals

Binary outputs
0.95
19.9 20 20.1 20.2 20.3 20.4 20.5 1
Time(s)
OPERATE
Vector shift angle detected in three phases 0.5 INT BLKD
Angle(Degrees)

0.4 0
VSAng AB 19.9 20 20.1 20.2 20.3 20.4 20.5
0.2 VSAng BC Time(s)
VSAng CA
0
19.9 20 20.1 20.2 20.3 20.4 20.5
Figure 9. Vector shift algorithm behavior during A-B-C fault at the
Time(s) beginning of the adjacent MV feeder
Vector shift algorithm Operate and Blocked signals
Binary outputs

1
OPERATE From Figure 9, one can see that during the A-B-C fault, all
0 INT BLKD
-1
three phase-to-phase voltages vector shift angles are
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s) significantly above the pick-up setting (5 degrees). But the
Figure 7. Vector shift algorithm behavior during A-G fault in the three phase-to-phase voltage magnitudes are below the set
middle of the same MV feeder undervoltage value (0.8 pu), which caused activation of the
Phase-to-Phase Fault algorithm internal block (INT_BLKD). Due to this internal
In this case, the phase-to-phase (A-B) fault for 150 ms is blocking the developed vector shift algorithm is not
applied in the middle of the adjacent MV feeder (ix in operated.
Figure 4). Fault resistance Rf = 5 . The results are 30% Voltage Dip in HV Network
presented in Figure 8. In this case, the 3-phase 30 % voltage dip is simulated in a
Voltage magnitude in three phases 110 kV HV network (xi in Figure 4). The results are
1
Voltage(pu)

U AB presented in Figure 10.

U BC
0.8
U CA Voltage magnitude in three phases
19.9 20 20.1 20.2 20.3 20.4 20.5 1
Voltage(pu)

Time(s) U AB
Vector shift angle detected in three phases 0.8 U BC
Angle(Degrees)

10 U CA
VSAng AB 0.6
19.9 20 20.1 20.2 20.3 20.4 20.5
5 VSAng BC Time(s)
VSAng CA Vector shift angle detected in three phases
0
Angle(Degrees)

19.9 20 20.1 20.2 20.3 20.4 20.5 4

Time(s) VSAng AB
Vector shift algorithm Operate and Blocked signals 2 VSAng BC
Binary outputs

1 VSAng CA
OPERATE 0
0.5 INT BLKD 19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s)
0 Vector shift algorithm Operate and Blocked signals
Binary outputs

19.9 20 20.1 20.2 20.3 20.4 20.5

Time(s) 1
OPERATE
0.5 INT BLKD
Figure 8. Vector shift algorithm behavior during A-B fault in the
0
middle of the adjacent MV feeder 19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s)
From Figure 8, it can be seen that during the A-B fault, the Figure 10. Vector shift algorithm behavior during a 3-phase 30%
UAB, UCA voltages vector shift angles are above the pick- voltage dip in HV network
up setting (5 degrees), but the vector shift angle of UBC is From Figure 10, it can be observed that during a 30 %
below the setting. The UAB voltage magnitude is just below voltage dip in the HV network, all three phase-to-phase
the set undervoltage value (0.8 pu), which caused voltage magnitudes are below the set undervoltage value
activation of the algorithm internal block (INT_BLKD). (0.8 pu), which caused activation of the algorithm internal
Due to these issues, the developed vector shift algorithm is block (INT_BLKD).
not operated.
Capacitor Switching at HV/MV Substation
Three-Phase Fault In this case, the capacitor switching at the HV/MV
In this case, the 3-phase (A-B-C) fault with fault resistance substation is simulated (iv in Figure 4).The results are
Rf = 1 for 150 ms is applied at the beginning of the presented in Figure 11.
adjacent MV feeder (x in Figure 4). The results are
shown in Figure 9.

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Voltage magnitude in three phases

1 reduce DG unit nuisance tripping because it is stable
Voltage(pu)

U AB
U BC during various network disturbances like faults, capacitor
U CA
0.95
19.9 20 20.1 20.2 20.3 20.4 20.5
switching and connection of parallel transformer.
Time(s)
Vector shift angle detected in three phases Although the proposed vector shift algorithm guarantees
Angle(Degrees)

1.5
VSAng AB
1
VSAng BC
fast and reliable islanding detection in nearly all
0.5
0
VSAng CA operational conditions when the DG unit is running in
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s) parallel with the utility grid supply, certain cases may still
Vector shift algorithm Operate and Blocked signals
cause mal-operations. If the power unbalance before
Binary outputs

1
OPERATE
0 INT BLKD islanding is very small and the detected vector shift angle
-1
19.9 20 20.1 20.2 20.3 20.4 20.5
is therefore also small, the function may not operate. This
Time(s)
means that the vector shift algorithm, like many traditional
Figure 11. Vector shift algorithm behavior during capacitor switching
event
passive islanding detection methods, still has NDZ near a
power balance situation. Therefore, other passive methods
From Figure 11, it can be seen that during capacitor for detecting the islanding without NDZ should be further
switching, the voltage magnitudes are stable around 1 pu developed. Potential methods to deal with this NDZ issue
and the vector shift angles around 1 degree. The detected could be, for example, the multi-criteria based passive
vector shift angles are less than the setting and vector shift islanding detection method [1] or use of active MV
is not detected in all three phases. Due to these issues the network management [2].
proposed vector shift algorithm is not operated.
Connection of Parallel Transformer at HV/MV REFERENCES
Substation [1] H. Laaksonen, 2012, "New Multi-Criteria Based
In this case, parallel transformer at the HV/MV substation Algorithm for Islanding Detection in Smart Grids",
is connected to the system (v in Figure 4). The results are IEEE PES ISGT Europe 2012, Berlin, Germany.
presented in Figure 12. [2] H. Laaksonen, 2014, "Reliable Islanding Detection
Voltage magnitude in three phases with Active MV Network Management", CIRED
0.97
Voltage(pu)

U AB Workshop, 11-12 June 2014, Rome.

0.965 U BC
U CA [3] A. Beddoes, P. Thomas, M. Gosden, 2005, "Loss of
0.96
19.9 20 20.1 20.2 20.3 20.4 20.5 Mains Protection Relay Performances when
Time(s)
Vector shift angle detected in three phases Subjected to Network Disturbances/Events", CIRED
Angle(Degrees)

1
VSAng AB
0.5 VSAng BC
18th International conference on electricity
VSAng CA distribution, 6-9 June 2005, Turin.
0
19.9 20 20.1 20.2 20.3 20.4 20.5
Time(s) [4] W. Freitas, Z. Huang, W. Xu, 2005, "A Practical
Vector shift algorithm Operate and Blocked signals
Binary outputs

1
OPERATE
Method for Assesing the Effectiveness of Vector
0 INT BLKD Surge Relays for Distributed Generation
-1
19.9 20 20.1 20.2 20.3 20.4 20.5 Applications", IEEE Transcations on Power
Time(s)
Delivery, vol. 20, no. 1
Figure 12. Vector shift algorithm behavior when connecting a parallel
transformer [5] W. Freitas, W. Xu, 2005, "Comparative Analysis
Between ROCOF and Vector Surge Relays for
From Figure 12, one can see that when connecting a Distributed Generation Applications", IEEE
parallel transformer, the voltage magnitudes are stable Transcations on Power Delivery, vol. 20, no. 2
around 1 pu and the vector shift angles around 0.5 degrees.
The detected vector shift angles are less than the setting
and therefore the proposed vector shift algorithm is not
operated.

CONCLUSIONS
In this paper a new advanced vector shift algorithm is
presented to improve the dependability and stability of the
voltage vector shift based islanding detection. The
developed algorithm can adaptively correct the measured
vector shift angle based on the steady-state frequency
variations, which makes the algorithm immune to steady-
state frequency variations. Based on the presented test
results, it can be concluded that the developed algorithm
successfully detects the islanding condition during small
and large power unbalances. In addition, the algorithm can

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