MCQ Computer Organization 2014-15

1.A 32-bit address bus allows access to a memory of capacity

(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb

2.Which processor structure is pipelined?

a)all x80 processors b) all x85 processors c) all x86 processors

3.In 8086 microprocessor one of the following statements is not true.

a)Coprocessor is interfaced in MAX mode b)Coprocessor is interfaced in MIN
modec)I/O can be interfaced in MAX / MIN mode d)Supports pipelining

4.The ________ ensures that only one IC is active at a time to avoid a bus conflict
caused by two ICs writing different data to the same bus.
A.control bus B.control instructions C.address decoder D.CPU

5.In an 8085 microprocessor, the instruction CMP B has been executed while the
contentsof accumulator is less than that of register B. As a result carry flag and zero flag
will berespectively
(A)set, reset (B) reset, set (C) reset, reset (D) set, set

6.To put the 8085 microprocessor in the wait state

(i) lower the-HOLD input
(ii) lower the READY input
(iii) raise the HOLD input
(iv) raise the READY input

7.Registers, which are partially visible to users and used to hold conditional, are known
as
a.PC
b.Memory address registers
c.General purpose register
d.Flags

8.What type of control pins are needed in a microprocessor to regulate traffic on the bus,
inorder to prevent two devices from trying to use it at the same time?
a.Bus control b.Interrupts c.Bus arbitration d.Status

9.Who invented the microprocessor?

a.Marcian E Huff b.Herman H Goldstein c.Joseph Jacquard d.All of above

10.Before a modem transmits, it send a:

a. CTS b.DTR c.DSR d.RTS

11.The number of memory cycles required to execute the following 8085 instructions
(i)LDA 3000H (ii)LXI D, FOF1H would be
(B)2 for (i) and 2 for (ii)
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(C)4 for (i) and 2 for (ii)
(D)3 for (i) and 3 for (ii)
(E)3 for (i) and 4 for (ii)

12.The 8255 Programmable Peripheral Interface isused as described below.

(i) An A/D converter is interfaced to a microprocessor through an 8255. The conversion is
initiated by a signalfrom the 8255 on Port C. A signal on Port C causes datato be stobed
into Port A.
(ii) Two computers exchange data using a pair of 8255s.Port A works as a bidirectional
data port supported byappropriate handshaking signals. The appropriatemodes of
operation of the 8255 for (i) and (ii) would be
(A)Mode 0 for (i) and Mode 1 for (ii)
(B)Mode 1 for (i) and Mode 2 for (ii)
(C)Mode 2 for (i) and Mode 0 for (ii)
(D)Mode 2 for (i) and Mode 1 for (ii)

13.The microprocessor 8085 has _____ basic instructions and _____ opcodes.
a) 80, 246
b) 70, 346
c) 80, 346
d) 70, 246

14.What does microprocessor speed depends on

a) Clock b) Data bus width c)Address bus width d)Size of register

15.The status that cannot be operated by direct instructions is

a) Cy b) Z c) P d)AC

16.The number of software interrupts in 8085 is ____ a) 5 b)8 c) 9 d) 10

17.Adress line for RST 3 is

a) 0020H b) 0028H c) 0018H d) 0038H

18.The necessary steps carried out to perform the operation of accessing either memory
or I/O Device, constitute a ___________________
a) fetch operation b) execute operation c)machine cycle d) instructioncycle
19.Which is a 8 bit Microprocessor __________ a) Intel 4040 b) Pentium I c) 8088 d)
Motorala MC-6801

20.Interfacing devices for DMA controller, programmable interval timer are

respectivelya)
8257, 8253 b) 8253, 8257 c) 8257,8251 d)8251,8257

21.Consider the following set of 8085 instruction.MVI A,82HORA AJP DSPLYXRA

ADSPLY:OUT PORT1HLT.The output at PORT1 is
a)00H
 MCQ Computer Organization 2014-15
b) FFH
c) 92H
d) 11H

22. The contents of accumulator before CMA instruction is A5H. Its content after
instructionexecution is
a) A5H b) 5AH c) AAH d) 55H

23.In an 8085 based system, the maximum number of input output devices can be
connectedusing I/0 mapped I/O method is
a) 64 b) 512 c) 256 d) 65536

24.How many transistors does the 8086 have?

a) 10,000 b) 29,000 c) 110,000 d) 129,000

25.What generation chip is the Pentium 4 for the Intel central processing units?
A. Seventh generation
B.Eighth generation
C.Ninth generation
D.Tenth Generation