ELS2103 - Digital System

Week 5
Transistor Level Logic CMOS vs. TTL
INSTITUT TEKNOLOGI DEL
Jl Sisingamangaraja, Tobasamosir (22381), Sumatera Utara
telp +62632331234, fax +626323311116, www.del.ac.id
 Topics

CMOS Logic Devices

Bipolar Logic Devices

Lect #4 ELS2103 Digital System SiagianP

 MOS Transistors
Voltage-controlled resistance

PMOS

NMOS

Lect #4 ELS2103 Digital

 Switch Model

Lect #4 ELS2103 Digital

 CMOS Inverter

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 Alternate transistor symbols

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 CMOS Gate Characteristics
No DC current flow into MOS gate terminal
However gate has capacitance ==> current required for
switching (CV2f power)
No current in output structure,
except during switching
Both transistors partially on
Power consumption related
to frequency
Slow input-signal rise times
==> more power
Symmetric output structure
==> equally strong drive in
LOW and HIGH states

Lect #4 ELS2103 Digital

 CMOS Gate Operation
Java applet showing CMOS gates
visit:
tech-www.informatik.uni-
hamburg.de/applets/cmos/
illustrates gate operation, including power drain
during switching
Link is on class website

Lect #4 ELS2103 Digital System SiagianP

 Pull-up / Pull-down Model
Typical CMOS gate can be viewed as
consisting of two parts
pull-up network and pull-down network

VDD

A
B Pull-up
C
output
A Pull-
B down
C

GND

Lect #4 ELS2103 Digital

 Pull-up / Pull-down Model
High level inputs to the PDN cause
switches to close
If there is a closed switch path thru
PDN, then output is low
Low level inputs to the PUN cause
switches to close
If there is a closed switch path thru
PUN, then output is high

Lect #4 ELS2103 Digital

 Pull-up / Pull-down Model

A Since hign level signals on

the inputs cause the PDN to
A and ( B or C) close switches, we get a
Boolean expression for the
B C
input which creates a closed
path thru PDN

If a closed path exists in PDN, then the output is pulled low.

Thus the logic function realized is the complement (inverted)
version of the Boolean expression.
output
A Pull- not (A and ( B or C))
B down
C

GND

Lect #4 ELS2103 Digital

 Pull-up / Pull-down Model
What happens when the Boolean expression is false?
V dd
Since there is no path thru PDN, the output could float.

In order to make the output high, the PUN must have a path which
connects VDD to the output. B

Observe: take the expression for PDN and use DeMorgans Law to write A
it in terms of complemented input variables. Complemented variables
are true when the input level is low. Thus, this gives exactly the form of C
the PUN

In this case: not A or ( not B and not C)

Lect #4 ELS2103 Digital

 CMOS NAND Gates
Use 2n transistors for n-input gate

Lect #4 ELS2103 Digital

 CMOS NAND -- switch model

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 CMOS NAND -- more inputs
(3)

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 CMOS non-inverting buffer

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 CMOS 2-input AND gate

Note the number of transistors compared to NAND (6

vs. 4)
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 In-Class Practice Problem

Design a CMOS NOR circuit

Hint: Like NAND shown earlier, NOR
circuits have 2n transistors for n-input
gate (this one has 4)

Lect #4 ELS2103 Digital

 CMOS NOR Gates
Like NAND -- 2n transistors for n-input
gate

Lect #4 ELS2103 Digital

 NAND vs. NOR
NMOS has lower on resistance than PMOS
(important when multiple transistors are in series)
NAND NOR

Result: NAND gates are preferred in CMOS due to

speed
Lect #4 ELS2103 Digital
 Cascade Structure
for Large Inputs
8-input CMOS NAND

Lect #4 ELS2103 Digital

 Complex Logic Functions
CMOS AND-OR-
INVERT gate

Lect #4 ELS2103 Digital

 Tri-State
We lied -
binary outputs have more than two values
Some gates are designed to have a
third value - a high impedance
Effectively disconnects the gate output
from the circuit

Lect #4 ELS2103 Digital

 Tri-State Application
En
En_ A
A F
A

If EN = 1, then F = A'
if En = 0, then F is open circuited,
denoted Hi-Z B

En_ A * A' + En_A' * B '

Lect #4 ELS2103 Digital

 Open Drain
Device without the internal active pull-
up network on the output
Why ?
Allows for two or more outputs to be
connected together
Produces a wired AND function
Requires a pull-up resistor

Lect #4 ELS2103 Digital

 Open Drain Application
+5v

A
B (AB)' (CD)' (EF)'
C
D =
E [AB + CD + EF] '
F

Lect #4 ELS2103 Digital

 CMOS Families
4000 series - mostly obsolete
HC
HCT (input levels compatible with TTL)
AC
ACT (input levels compatible with TTL)
FCT and FCT-T (both TTL compatible)

Lect #4 ELS2103 Digital

 Bipolar Logic Families

Lect #4 ELS2103 Digital

 TTL Digital Circuits
Designed using transistor-transistor
logic (remember EE341 ?)
npn bipolar junction transistors
Transistors operate in either
cut-off mode
no base current => no collector current
saturated mode
base current pulls VCE to ~ 0.2 v

Lect #4 ELS2103 Digital

 A Simplified TTL NAND Gate
+5V

A
B

Vout

Lect #4 ELS2103 Digital

 Schottky Transistors
Addition of Schottky diodes between
base and collector prevent saturation
Schottky diode has lower forward bias
voltage drop (0.25 v).
Resulting design is called a Schottky
transistor
Speeds switching time by reducing
charge storage in saturation

Lect #4 ELS2103 Digital

 TTL NAND Gate

Lect #4 ELS2103 Digital

 Special TTL outputs
Standard output stage is called totem
pole output
Tri-state outputs
Open collector (or CMOS open drain)
requires external pull-up resistor
allows wired-AND function

Lect #4 ELS2103 Digital

 TTL differences from CMOS
Asymmetric input and output characteristics.
Inputs source significant current in the LOW
state, leakage current in the HIGH state.
Output can handle much more current in the
LOW state (saturated transistor).
Output can source only limited current in the
HIGH state (resistor plus partially-on
transistor).
TTL has difficulty driving pure CMOS inputs
because VOH = 2.4 V (except T CMOS).

Lect #4 ELS2103 Digital

 TTL Families
7400 series (5400 mil spec)
74 S - Schottky
74 LS - low power Schottky
74 AS - advanced Schottky
74 ALS - advanced low power Schottky
74 F - Fast TTL

Lect #4 ELS2103 Digital

 TIs Logic Products

9/10/98
Lect #4 ELS2103 Digital
 Comparison of Signal Levels
CMOS CMOS TTL
(HC, AC) (HCT, ACT) (S, LS, AL, ALS, F)
5v 5v 5v
VOH 4.4 v

VIH 3.5 v
VOH 2.4 v VOH 2.4 v
VIH 2.0 v VIH 2.0 v
VIL 1.5 v

VIL 0.8 v VIL 0.8 v

VOL 0.5 v VOL 0.4 v VOL 0.4 v
0v 0v 0v

Lect #4 ELS2103 Digital

 Another Practice Problem
Attempt to draw a truth
table for the following A

circuit. Hint: List each B

transistor in the truth
table and show C
whether it is on of off D
for each input
combination

Lect #4 ELS2103 Digital

 Another Practice Problem
Z
H
H
H
H OR-AND-INVERT
H
L
L
L
H
L
L
L
H
L
L
L

Lect #4 ELS2103 Digital

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