Percobaan I

PENGENALAN DESAIN MENGGUNAKAN FPGA

Anju M. Silitonga (14S16037)

Tanggal Percobaan : 19/10/2017
ELS2104 PRAKTIKUM SISTEM DIGITAL
Laboratorium Dasar Teknik Elektro Teknik Elektro
Institut Teknologi Del

AbstrakTechniques of designing digital cicuits with fpga is

classical architecture cpld still use logic block from GAL/PAL
by using programmable interconection. In field programmable
logic array architecture (FPGA) use completely different
concept that is configurable logic block (CLB) and
programmable interconnection regulated according to rows
and columb. FPGA is volatile, because it is made of antifuse
technology and based on SPAM technology, therefore FPGA,
generally use ROM to store configuratin files used for their
digital circuits. In generally the ROM used depends on the
user or provided in the form of a ready made board the design
of digital circuit with target fpga using VHDL programming
language is VHDL usually used to write text models that
describe logic circuits. Such a models is prosessed by a
synthesis program, only if its part of the logic design.
Keyword : CPLD, SRAM, FPGA, VHDL, FULL ADDER.
I. THEORETICAL THEORY
1. FPGA
Field Programmable Gate Arrays (FPGAs) are
semiconductor devices that are based around a matrix
of configurable logic blocks (CLBs) connected via
programmable interconnects. FPGAs can be
reprogrammed to desired application or functionality
requirements after manufacturing. This feature
distinguishes FPGAs from Application Specific
Integrated Circuits (ASICs), which are custom
manufactured for specific design tasks. Although one-
time programmable (OTP) FPGAs are available, the
dominant types are SRAM based which can be
reprogrammed as the design evolves.

INTRODUCTION
In this experiment we will learn the technique of
designing digital circuit with target FPGA, experiment to
design full adder using XILLINX FPGA with schematic
approach and using VHDL language. there are several types of
FULL ADDER series, namely PALLEL ADDER, LOOK
AHEAD, CARRY ADDER, and CARRY SAVE ADDER
where each has its advantages and disadvantages. as for the
FPGA we use is XILLINX XC3S250E.
In this experiment the objectives and tools and materials are:

Purpose of experiment
1. Learn the technique of designing digital circuit with target
FPGA.
2. Can do digital circuit design with target FPGA using either
schematic approach or VHDL language.

Tools and materials : laptop installed xillinx ISE

Project Navigator 12.2 2. FULL ADDER
Full adder is a digital circuit that performs
addition. Full adders are implemented with logic gates in
hardware. A full adder adds three one-bit binary numbers,
 two operands and a carry bit. The adder outputs two
numbers, a sum and a carry bit. The term is contrasted
with a half adder, which adds two binary digits.

Full adder takes two binary numbers plus a carry

or overflow bit. The output is a sum and another carry bit.
Full adders are made from XOR, AND and OR gates in
hardware. Full adders are commonly connected to each
other to add bits to an arbitrary length of bits, such as 32
or 64 bits. A full adder is effectively two half adders, an
XOR and an AND gate, connected by an OR gate.

4. SRAM
SRAM (static RAM) is random access memory
K-map truth table from full adder (RAM) that retains data bits in its memory as long as
power is being supplied. Unlike dynamic RAM (DRAM),
which stores bits in cells consisting of a capacitor and a
transistor,SRAM does not have to be periodically
refreshed.
5. XILLINX
Xilink (Xilink Foundation Series) is a useful software
for designing and simulating a digital circuit. By using
Xilink the design process of a device or digital circuit
through a circuit simulation process that has been
designed to see if the design has been made is correct
or still contains errors.

3. VHDL II. Results and analysis

VHDL (VHSIC Hardware Description Language) is a
hardware description language used in electronic design 1. 2A: DESIGNING FULL ADDER WITH
automation to describe digital and mixed-signal systems SCEMATICS
such as field-programmable gate arrays and integrated
circuits. VHDL can also be used as a general purpose
parallel programming language. Step by Step Instructions to simulate a full-
adder.
I. Open up Schematics:

In Win 7, go to Start, Programs, , open up xillinx ISE

Project Navigator 12.2

A. Create a new project and name it.

B. Under Tools Menu, select Design Entry/Schematic
Editor.
II. Create a half-adder:
A. In the Schematic Editor window, open the Symbol

schematic that we draw on this experiment

Toolbox by pressing () button on the schematic
toolbar on the left.

B. Select AND2(The 2 represents two inputs),

click on the Schematic Workspace to place
the gate.
C. Select XOR2 and place it next to the AND2
gate.
D. Click on the draw wire button in the

schematic toolbar ( ).
E. Click once at a terminal of the XOR2 gate,
move mouse to an open space and right
click to bring up a menu. Select Add
Terminal, enter terminal name A1, select
terminal type INPUT, click OK.
F. Repeat the above procedure for the other
XOR2 terminal, but enter terminal name B1
instead. You should have the following:
Analysis : I may not be able to see the worst case delay in
your post-place & route waveforms, because the worst
case delay is input pattern dependant. Put another way, the
worst case delay happens only when certain transitions of
the inputs take place. As an exercise, think about what input
transitions will exhibit the worst case delay Ci->Co
(9.620ns) of our full adder. I modify test bench to have the
worst case delay shown in the waveforms.

G. Select the draw wire button (If its not

already selected). Click once at the
terminals of the AND2 gates and connect to
the two wires of the XOR2 gates by
clicking on them.
H. Create two output pins the same way you
create input pins in step D and E above. For
terminal type, select OUTPUT instead of
INPUT and name them SUM and CARRY.
You should have the following:
2B : DESIGNING FULL ADDER WITH VHDL LANGUAGE
APPROACH

In this experiment we will design full adder with different

approach that is by utilizing VHDL language. Previously
recommended to read back praktikan lecture materials
on VHDL language because in most labs this material
will not be repeated again.

Analysis : The Parallel Adder circuit consists of a Half

Analysis :
able to do hardware design until the system more complex,
Easy to find and detect errors more easily in simulation.
2C : DESIGNING 4-BIT RIPPLE CARRY ADDER WITH
VHDL.
We can build an n-bit adder by exploiting the previous
vhdl code through use of component keywords. Below you
will be given a 4-bit full sample adder with Ripple Carry
Adder architecture.
Parallel Adder circuit is a summing circuit of two numbers
(whether it is octal, decimal or hexadecimal) that has been
converted into binary form. Let's say there are two A and B
registers, each register is 4 bits.
Adder (HA) on the Least Significant Bit (LSB) of each input
and some Full Adder on the next bits. The working
principle of Parallel Adder is as follows: the summation is
done starting from the LSB. If the sum is a decimal number
"2" or more, then the excess bit is stored in Cout, while the
bit below will be issued in . It goes on to the Most
Significant Bit (MSB).
2D : DESIGNING 4-BIT ADDER WITH SCEMATICS
A 4-bit adder which adds two four bit binary numbers with a
Carry in line. The diagram above show the logic gate
schematic of a 4-bit adder. A full adder take in two number
and a carry in line, while a half adder does not allow a carry-in
bit. Although both a full adder and a full adder will output a
carry out bit. Note the Carry Out is not shown in the diagram
above. This schematic link shows the transistor view of a 4-bit
adder circuit.
 5. http://www.interfacebus.com/ic-adder-chips.html
6. web.eecs.utk.edu/~bvz/teaching/ece255fa08/labs/lab1.pdf
7. Modul M02_Prak.Sistem_Digital.
8.https://courses.cs.washington.edu/courses/cse370/DDOR/Tu
torials/Hierarchy/add4_ex.html

Analysis :
Building digital circuits using schematic is easier
because we can draw it in detail and thoroughly.

Conclusion :
1. Designing digital circuits using schematic is easier
than VHDL
2. vhdl is a very complex hardware-oriented
programming language, where we can make
digital circuits very well.
3. FPGA has a small error correction and is a
technology-independent technology to be
implemented in various algorithms
4. Having the ability to handle such a heavy
computing load, Eliminate the intensive tasks of
Digital Signal Processing Customize the
architecture to fit the ideal algorithm, Reduce
system costs, Cost efficiency.
5. VHDL is one type of HDL language used to
describe various functions of digital circuits such
as FPGA (Field-programmable Gate Arrays), Logic
gates, Flip-flops, etc.
6.

REFERENSI
1. https://cseweb.ucsd.edu/classes/fa01/cse140l/fulladder.html
2. http://www.circuitstoday.com/half-adder-and-full-adder
3.https://pdfs.semanticscholar.org/a64c/4d35faeac46a6a68f56
9893fb4e0ebf19ecd.pdf
4. http://teahlab.com/VHDL_Code_Full_Adder/
Lampiran :