Colour Television Chassis

Q552.4E
LA

Contents Page
1. Revision List 2
2. Technical Specs, Diversity, and Connections 2
3. Precautions, Notes, and Abbreviation List 7
4. Mechanical Instructions 11
5. Service Modes, Error Codes, and Fault Finding 20
6. Alignments 39
7. Circuit Descriptions 47
8. IC Data Sheets 53
9. Block Diagrams Drawing
Wiring diagram 4000 series 32" 69
Wiring diagram 4000 series 37" 70
Wiring diagram 4000 series 42" 71
Wiring diagram 4000 series 47" 72
Wiring diagram 5000 & 5500 series 32" 73
Wiring diagram 5000 & 5500 series 40" 74
Wiring diagram 5000 & 5500 series 46" 75
Wiring diagram 5000 series 55" 76
Block Diagram Video 77
Block Diagram Audio 78
Block Diagram Control & Clock Signals 79
Block Diagram I2C 80
Supply Lines Overview 81
10. Circuit Diagrams and PWB Layouts Drawing PWB
A 715G5194 PSU 32" & 37" 3500/4000 series 82 82-82
A01 715G5246 PSU 42" 3500/4000 series 88 91-92
B 313912365313 SSB 93 128-129
B 313912365333 - 313912365334 SSB 130 163-166
J 272217190529 Sensor board 167 168
J 272217190532 Sensor board 169 170
J 715G5255 Sensor board 171 172
E 2722171 90545, 90547, 90549, 90552, 90558
Keyboard control panel 173 174
E 715G5252 Keyboard control panel 3500/4000
series 175 175
11. Styling Sheets Drawing
4000 series 32" 177
4000 series 37" 178
4000 series 42" 179
4000 series 47" 180
5000 series 32" 181
5000 series 40" 182
5000 series 46" 183
5000 series 55" 184

Published by ER/TY 1266 Quality Printed in the Netherlands Subject to modification EN 3122 785 19222
2012-Jun-29

2012 TP Vision Netherlands B.V.
All rights reserved. Specifications are subject to change without notice. Trademarks are the
property of Koninklijke Philips Electronics N.V. or their respective owners.
TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjust
earlier supplies accordingly.
PHILIPS and the PHILIPS Shield Emblem are used under license from Koninklijke Philips Electronics N.V.
 EN 2 1. Q552.4E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0
First release.

Manual xxxx xxx xxxx.1

Chapter 2: Table 2-1 updated (added CTNs).

Manual xxxx xxx xxxx.2

Chapter 4: added additional LVDS cable handling info; see
section 4.4.2.

2. Technical Specs, Diversity, and Connections

Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections 2.1 Technical Specifications
2.4 Chassis Overview For on-line product support please use the CTN links
in Table 2-1. Here is product information available, as well as
Notes: getting started, user manuals, frequently asked questions and
Figures can deviate due to the different set executions. software & drivers.
Specifications are indicative (subject to change).

Table 2-1 Described Model Numbers and Diversity

2 4 9 10 11
Schemat
Mechanics Block Diagrams ics Styling

E (Keyboard/Leading Edge)
Connection Overview

Assembly Removal

J (Sensor Board)
Control & Clock
Wiring Diagram
Wire Dressing

Power Supply
Supply lines
Dressing

Audio

Name

Sheet
Video

SSB
I2C

CTN
32PFL4007H/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4007H/60 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4007K/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4007M/08 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4007T/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4007T/60 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4027H/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4027H/60 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4027K/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4027T/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4027T/60 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4037H/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4037H/60 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4037K/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4037T/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4037T/60 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL4047T/12 2.3 4-1 4.4 9.1 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.1
32PFL5007H/12 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.5
32PFL5007H/60 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.5
32PFL5007K/12 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.5
32PFL5007M/08 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.5
32PFL5007T/12 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.5
32PFL5007T/60 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.5
32PFL5507H/12 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.5
32PFL5507H/60 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.5
32PFL5507K/12 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.5
32PFL5507M/08 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.5
32PFL5507T/12 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.5
32PFL5507T/60 2.3 4-5 4.4 9.5 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.5
37PFL4007H/12 2.3 4-2 4.4 9.2 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.2
37PFL4007K/12 2.3 4-2 4.4 9.2 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.2
37PFL4007M/08 2.3 4-2 4.4 9.2 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.2
37PFL4007T/12 2.3 4-2 4.4 9.2 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.2
37PFL4007T/60 2.3 4-2 4.4 9.2 9.9 9.10 9.11 9.12 9.13 10.1 10.4 10.7 10.9 4000 11.2

2012-Jun-29 back to
div. table
 Technical Specs, Diversity, and Connections Q552.4E LA 2. EN 3

2 4 9 10 11
Schemat
Mechanics Block Diagrams ics Styling

E (Keyboard/Leading Edge)
Connection Overview

Assembly Removal

J (Sensor Board)
Control & Clock
Wiring Diagram
Wire Dressing

Power Supply
Supply lines
Dressing

Audio
Video

Name

Sheet
SSB
I2C
CTN
40PFL5007H/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.6
40PFL5007H/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.6
40PFL5007K/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.6
40PFL5007M/08 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.6
40PFL5007T/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.6
40PFL5007T/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.6
40PFL5507H/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5507H/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5507K/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5507M/08 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5507T/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5507T/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5527H/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5527H/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5527K/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5527M/08 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5527T/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5527T/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5537H/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5537H/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5537K/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5537M/08 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5537T/12 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
40PFL5537T/60 2.3 4-6 4.4 9.6 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.6
42PFL4007H/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4007K/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4007M/08 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4007T/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4007T/60 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4047T/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4307H/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4307K/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4307T/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
42PFL4317K/12 2.3 4-3 4.4 9.3 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.3
46PFL5007H/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.7
46PFL5007K/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.7
46PFL5007M/08 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.7
46PFL5007T/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.4 10.5 10.8 5000 11.7
46PFL5507H/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5507H/60 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5507K/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5507M/08 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5507T/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5507T/60 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5527H/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5527H/60 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5527K/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5527M/08 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5527T/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5527T/60 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5537T/60 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5537H/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5537H/60 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5537K/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5537M/08 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
46PFL5537T/12 2.3 4-7 4.4 9.7 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.7
47PFL4007H/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4007H/60 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4007K/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4007M/08 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4007T/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4007T/60 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4037T/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4047T/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4

back to 2012-Jun-29
div. table
 EN 4 2. Q552.4E LA Technical Specs, Diversity, and Connections

2 4 9 10 11
Schemat
Mechanics Block Diagrams ics Styling

E (Keyboard/Leading Edge)
Connection Overview

Assembly Removal

J (Sensor Board)
Control & Clock
Wiring Diagram
Wire Dressing

Power Supply
Supply lines
Dressing

Audio
Video

Name

Sheet
SSB
I2C
CTN
47PFL4307H/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4307K/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
47PFL4307T/12 2.3 4-4 4.4 9.4 9.9 9.10 9.11 9.12 9.13 10.2 10.4 10.7 10.9 4000 11.4
55PFL5507H/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5507H/60 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5507K/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5507M/08 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5507T/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5507T/60 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5527H/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5527K/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5527M/08 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5527T/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5537H/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5537K/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5537M/08 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8
55PFL5537T/12 2.3 4-8 4.4 9.8 9.9 9.10 9.11 9.12 9.13 - 10.3 10.6 10.8 5000 11.8

2.2 Directions for Use

You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

2012-Jun-29 back to
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 Technical Specs, Diversity, and Connections Q552.4E LA 2. EN 5

2.3 Connections

REAR CONNECTORS SIDE CONNECTORS

CI
AUDIO IN AUDIO IN
NETWORK DVI/VGA Y/Pb/Pr Y/Pb/Pr SERV.U

10
1 2 3 4

11
DIGITAL
AUDIO OUT
(OPTICAL)

12
BOTTOM REAR CONNECTORS
USB 3

5 6 7 8 9
USB 2 13

HDMI
SIDE

75
VGA SCART
(RGB/CVBS)
(3) (2) (1) ARC USB 1
14
HDMI TV ANTENNA

19220_007_120222.eps
120222

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used 3 - Cinch: Video YPbPr - In, Audio - In
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Gn - Video Y 1 VPP / 75 ohm jq
Grey, Rd= Red, Wh= White, Ye= Yellow. Bu - Video Pb 0.7 VPP / 75 ohm jq
Rd - Video Pr 0.7 VPP / 75 ohm jq
2.3.1 Rear Connections Rd - Audio - R 0.5 VRMS / 10 kohm jq
Wh - Audio - L 0.5 VRMS / 10 kohm jq
1 - RJ45: Ethernet
4 - Service Connector (UART)
1 - Ground Gnd H
2 - UART_TX Transmit k
3 - UART_RX Receive j
10000_025_090121.eps
120320 2.3.2 Rear Connections - Bottom

Figure 2-2 Ethernet connector

5 - VGA: Video RGB - In
1 5

1 - TD+ Transmit signal k 6

10

2 - TD- Transmit signal k 11 15

10000_002_090121.eps
3 - RD+ Receive signal j 090127
4 - CT Centre Tap: DC level fixation
5 - CT Centre Tap: DC level fixation Figure 2-3 VGA Connector
6 - RD- Receive signal j
7 - GND Gnd H 1 - Video Red 0.7 VPP / 75 ohm j
8 - GND Gnd H 2 - Video Green 0.7 VPP / 75 ohm j
3 - Video Blue 0.7 VPP / 75 ohm j
2 - Cinch: Audio - In (VGA/DVI) 4 - n.c.
Rd - Audio R 0.5 VRMS / 10 kohm jq 5 - Ground Gnd H
Wh - Audio L 0.5 VRMS / 10 kohm jq 6 - Ground Red Gnd H

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 EN 6 2. Q552.4E LA Technical Specs, Diversity, and Connections

7 - Ground Green Gnd H 8 - Aerial - In

8 - Ground Blue Gnd H - - IEC-type (EU) Coax, 75 ohm D
9 - +5VDC +5 V j
10 - Ground Sync Gnd H 9 - USB 1: USB2.0
11 - n.c.
12 - DDC_SDA DDC data j
13 - H-sync 0-5V j 1 2 3 4
14 - V-sync 0-5V j 10000_022_090121.eps
090121
15 - DDC_SCL DDC clock j
Figure 2-6 USB (type A)
6 - SCART: Video RGB - In, CVBS - In, Audio - In
20 2 1 - +5V k
2 - Data (-) jk
3 - Data (+) jk
21 1
10000_001_090121.eps
4 - Ground Gnd H
090121

Figure 2-4 SCART connector 2.3.3 Side Connections

1 - n.c. 10 - Common Interface

2 - Audio R 0.5 VRMS / 10 kohm j 68p - See diagram B05G 10-3-15 jk
3 - n.c.
4 - Ground Audio Gnd H 11 - Head phone (Output)
5 - Ground Blue Gnd H Bk - Head phone 32 - 600 ohm / 10 mW ot
6 - Audio L 0.5 VRMS / 10 kohm j
7 - Video Blue 0.7 VPP / 75 ohm jk 12 - Optical: S/PDIF - Out
8 - Function Select 0 - 2 V: INT Bk - Coaxial Optical signal k
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3 j 13 - USB 2, 3: USB2.0
9 - Ground Green Gnd H
10 - n.c.
11 - Video Green 0.7 VPP / 75 ohm j 1 2 3 4
12 - n.c. 10000_022_090121.eps
13 - Ground Red Gnd H 090121

14 - Ground P50 Gnd H

Figure 2-7 USB (type A)
15 - Video Red 0.7 VPP / 75 ohm j
16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm j 1 - +5V k
17 - Ground Video Gnd H 2 - Data (-) jk
18 - Ground FBL Gnd H 3 - Data (+) jk
19 - n.c. 4 - Ground Gnd H
20 - Video CVBS 1 VPP / 75 ohm j
21 - Shield Gnd H 14 - HDMI SIDE: Digital Video, Digital Audio - In
19 1
7 - HDMI: Digital Video - In, Digital Audio with ARC - In/Out 18 2

(optional) 10000_017_090121.eps
090428
19 1
18 2
Figure 2-8 HDMI (type A) connector
10000_017_090121.eps
090428
1 - D2+ Data channel j
Figure 2-5 HDMI (type A) connector 2 - Shield Gnd H
3 - D2- Data channel j
1 - D2+ Data channel j 4 - D1+ Data channel j
2 - Shield Gnd H 5 - Shield Gnd H
3 - D2- Data channel j 6 - D1- Data channel j
4 - D1+ Data channel j 7 - D0+ Data channel j
5 - Shield Gnd H 8 - Shield Gnd H
6 - D1- Data channel j 9 - D0- Data channel j
7 - D0+ Data channel j 10 - CLK+ Data channel j
8 - Shield Gnd H 11 - Shield Gnd H
9 - D0- Data channel j 12 - CLK- Data channel j
10 - CLK+ Data channel j 13 - Easylink/CEC Control channel jk
11 - Shield Gnd H 14 - n.c.
12 - CLK- Data channel j 15 - DDC_SCL DDC clock j
13 - Easylink/CEC Control channel jk 16 - DDC_SDA DDC data jk
14 - ARC (optional) Audio Return Channel 17 - Ground Gnd H
(optional) k 18 - +5V j
15 - DDC_SCL DDC clock j 19 - HPD Hot Plug Detect j
16 - DDC_SDA DDC data jk 20 - Ground Gnd H
17 - Ground Gnd H
18 - +5V j 2.4 Chassis Overview
19 - HPD Hot Plug Detect j Refer to chapter Block Diagrams for PWB/CBA locations.
20 - Ground Gnd H

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 Precautions, Notes, and Abbreviation List
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2 Warnings
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched on.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
3.3 Notes
3.3.1 General
Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
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Q552.4E LA 3. EN 7
3.3.2 Schematic Notes
All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( 10-6),
nano-farads (n 10-9), or pico-farads (p 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
To reach a solder-tip temperature of at least 400C.
To stabilize the adjusted temperature at the solder-tip.
To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around
360C - 380C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch off unused equipment or
reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
3.3.6 Alternative BOM identification
It should be noted that on the European Service website,
Alternative BOM is referred to as Design variant.
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
2012-Jun-29
 EN 8 3. Q552.4E LA Precautions, Notes, and Abbreviation List

result in sets which have the same CTN (Commercial Type 6 = play 16 : 9 format, 12 = play 4 : 3
Number; e.g. 28PW9515/12) but which have a different B.O.M. format
number. AARA Automatic Aspect Ratio Adaptation:
By looking at the third digit of the serial number, one can algorithm that adapts aspect ratio to
identify which B.O.M. is used for the TV set he is working with. remove horizontal black bars; keeps
If the third digit of the serial number contains the number 1 the original aspect ratio
(example: AG1B033500001), then the TV set has been ACI Automatic Channel Installation:
manufactured according to B.O.M. number 1. If the third digit is algorithm that installs TV channels
a 2 (example: AG2B0335000001), then the set has been directly from a cable network by
produced according to B.O.M. no. 2. This is important for means of a predefined TXT page
ordering the correct spare parts! ADC Analogue to Digital Converter
For the third digit, the numbers 1...9 and the characters A...Z AFC Automatic Frequency Control: control
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be signal used to tune to the correct
indicated by the third digit of the serial number. frequency
AGC Automatic Gain Control: algorithm that
Identification: The bottom line of a type plate gives a 14-digit controls the video input of the feature
serial number. Digits 1 and 2 refer to the production centre (e.g. box
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. AM Amplitude Modulation
code, digit 4 refers to the Service version change code, digits 5 AP Asia Pacific
and 6 refer to the production year, and digits 7 and 8 refer to AR Aspect Ratio: 4 by 3 or 16 by 9
production week (in example below it is 2010 week 10 / 2010 ASF Auto Screen Fit: algorithm that adapts
week 17). The 6 last digits contain the serial number. aspect ratio to remove horizontal black
bars without discarding video
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
10000_053_110228.eps countries
110228 B-TXT Blue TeleteXT
C Centre channel (audio)
Figure 3-1 Serial number (example) CEC Consumer Electronics Control bus:
remote control bus on HDMI
3.3.7 Board Level Repair (BLR) or Component Level Repair connections
(CLR) CL Constant Level: audio output to
connect with an external amplifier
If a board is defective, consult your repair procedure to decide CLR Component Level Repair
if the board has to be exchanged or if it should be repaired on ComPair Computer aided rePair
component level. CP Connected Planet / Copy Protection
If your repair procedure says the board should be exchanged CSM Customer Service Mode
completely, do not solder on the defective board. Otherwise, it CTI Color Transient Improvement:
cannot be returned to the O.E.M. supplier for back charging! manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
3.3.8 Practical Service Precautions
Synchronization
DAC Digital to Analogue Converter
It makes sense to avoid exposure to electrical shock. DBE Dynamic Bass Enhancement: extra
While some sources are expected to have a possible low frequency amplification
dangerous impact, others of quite high potential are of DCM Data Communication Module. Also
limited current and are sometimes held in less regard. referred to as System Card or
Always respect voltages. While some may not be Smartcard (for iTV).
dangerous in themselves, they can cause unexpected DDC See E-DDC
reactions that are best avoided. Before reaching into a D/K Monochrome TV system. Sound
powered TV set, it is best to test the high voltage insulation. carrier distance is 6.5 MHz
It is easy to do, and is a good service precaution. DFI Dynamic Frame Insertion
DFU Directions For Use: owner's manual
3.4 Abbreviation List DMR Digital Media Reader: card reader
0/6/12 SCART switch control signal on A/V DMSD Digital Multi Standard Decoding
board. 0 = loop through (AUX to TV), DNM Digital Natural Motion

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 Precautions, Notes, and Abbreviation List Q552.4E LA 3. EN 9

DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,

reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote iTV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A key encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a snow vision mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP software key VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I 2C Inter IC bus software upgrade via RF transmission.
I2D Inter IC Data bus Upgrade software is broadcasted in
I2S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (colour
Telecommunication Union relating to carrier = 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (colour carrier
SDI), is a digitized video format used PAL M = 3.575612 MHz and
for broadcast grade video. PAL N = 3.582056 MHz)
Uncompressed digital component or PCB Printed Circuit Board (same as PWB)
digital composite signals can be used. PCM Pulse Code Modulation

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 EN 10 3. Q552.4E LA Precautions, Notes, and Abbreviation List

PDP Plasma Display Panel SWAN Spatial temporal Weighted Averaging

PFC Power Factor Corrector (or Pre- Noise reduction
conditioner) SXGA 1280 1024
PIP Picture In Picture TFT Thin Film Transistor
PLL Phase Locked Loop. Used for e.g. THD Total Harmonic Distortion
FST tuning systems. The customer TMDS Transmission Minimized Differential
can give directly the desired frequency Signalling
POD Point Of Deployment: a removable TS Transport Stream
CAM module, implementing the CA TXT TeleteXT
system for a host (e.g. a TV-set) TXT-DW Dual Window with TeleteXT
POR Power On Reset, signal to reset the uP UI User Interface
PSDL Power Supply for Direct view LED uP Microprocessor
backlight with 2D-dimming UXGA 1600 1200 (4:3)
PSL Power Supply with integrated LED V V-sync to the module
drivers VESA Video Electronics Standards
PSLS Power Supply with integrated LED Association
drivers with added Scanning VGA 640 480 (4:3)
functionality VL Variable Level out: processed audio
PTC Positive Temperature Coefficient, output toward external amplifier
non-linear resistor VSB Vestigial Side Band; modulation
PWB Printed Wiring Board (same as PCB) method
PWM Pulse Width Modulation WYSIWYR What You See Is What You Record:
QRC Quasi Resonant Converter record selection that follows main
QTNR Quality Temporal Noise Reduction picture and sound
QVCP Quality Video Composition Processor WXGA 1280 768 (15:9)
RAM Random Access Memory XTAL Quartz crystal
RGB Red, Green, and Blue. The primary XGA 1024 768 (4:3)
color signals for TV. By mixing levels Y Luminance signal
of R, G, and B, all colors (Y/C) are Y/C Luminance (Y) and Chrominance (C)
reproduced. signal
RC Remote Control YPbPr Component video. Luminance and
RC5 / RC6 Signal protocol from the remote scaled color difference signals (B-Y
control receiver and R-Y)
RESET RESET signal YUV Component video
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see ITU-656
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mmoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 600 (4:3)
SVHS Super Video Home System
SW Software

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 Mechanical Instructions Q552.4E LA 4. EN 11

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing 4000 Styling (xxPFL4xx7x/xx series) Notes:
4.2 Cable Dressing 5000 styling (xxPFL5xx7x/xx series)
4.3 Service Positions Figures below can deviate slightly from the actual situation,
4.4 Assy/Panel Removal due to the different set executions.
4.5 Set Re-assembly

4.1 Cable Dressing 4000 Styling (xxPFL4xx7x/xx series)

19220_009_120223.eps
120223

Figure 4-1 Cable dressing 32PFL4xx7x/xx

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 EN 12 4. Q552.4E LA Mechanical Instructions

19220_010_120223.eps
120223

Figure 4-2 Cable dressing 37PFL4xx7x/xx

19220_011_120223.eps
120223

Figure 4-3 Cable dressing 42PFL4xx7x/xx

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 Mechanical Instructions Q552.4E LA 4. EN 13

19220_012_120223.eps
120223

Figure 4-4 Cable dressing 47PFL4xx7x/xx

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 EN 14 4. Q552.4E LA Mechanical Instructions

4.2 Cable Dressing 5000 styling (xxPFL5xx7x/xx series)

3 tape (150 m.m.)

11 tape (100 m.m.)
3 clamp
1 adhesive saddle
19220_014_120223.eps
120223

Figure 4-5 Cable dressing 32PFL5xx7x/xx

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 Mechanical Instructions Q552.4E LA 4. EN 15

4 tape (150 m.m.)

11 tape (100 m.m.)
1 adhesive clamp
19220_015_120223.eps
120223

Figure 4-6 Cable dressing 40PFL5xx7x/xx

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 EN 16 4. Q552.4E LA Mechanical Instructions

2 tape (200 m.m.)

2 tape (150 m.m.)
10 tape (100 m.m.)
6 tape (80 m.m.)
3 tape (50 m.m.)
2 clamp
19220_016_120223.eps
120223

Figure 4-7 Cable dressing 46PFL5xx7x/xx

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 Mechanical Instructions Q552.4E LA 4. EN 17

19220_083_120229.eps
120229

Figure 4-8 Cable dressing 55PFL5xx7x/xx

4.3 Service Positions

For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.

4.4 Assy/Panel Removal

Instructions below apply to the 32PFL5507K/12, but will be
similar for other models.
1
4.4.1 Rear Cover

Warning: Disconnect the mains power cord before removing

19220_066_120229.eps
the rear cover. 120229
Attention: Before lifting the rear cover, unplug the Keyboard
Control connector [1], as indicated in Figure 4-9. Figure 4-9 Rear cover removal

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 EN 18 4. Q552.4E LA Mechanical Instructions

4.4.2 Small Signal Board (SSB)

Caution: it is mandatory to remount all different screws at their 3

original position during re-assembly. Failure to do so may result
in damaging the SSB.

ATTENTION!
The LVDS connector(s) require(s) a special procedure for
disconnecting. LVDS CABLE
Refer to Figure 4-10 to Figure 4-13 for clarification.
1. Press the catches [1] simultaneously.
2. Slide the LVDS cable sidewards carefully [2].
Failure to pressing the catches leads to a damaged LVDS
cable [3]!
Any LVDS cable that is damaged at the notch area must be
replaced with a new one to avoid future unnecessary
repair actions.
19220_068_120229.eps
120229

Figure 4-12 LVDS cable - damaged notch area [3]

1
Upon re-connecting the LVDS cable, ensure the catches are
locked after having inserted the LVDS cable.

LVDS CABLE

2
Click!

1
19220_067_120229.eps
120229

Figure 4-10 LVDS connector - correct handling

LVDS flat foil

Click!

19222_001_120626.eps
120626

Figure 4-13 SSB LVDS - catch locking

19054_001_111010.eps 4.4.3 IR/LED panel

111010

1. Unlock the catches at both sides.

Figure 4-11 Unlocking LVDS connector
2. Flip the board upside-down.
3. Unlock the cable from the connector.
When defective, replace the whole unit.

4.4.4 Keyboard Control Panel

The keyboard control panel is located in the rear cover.

When defective, replace the whole unit.

4.4.5 LCD Panel

Refer to Figure 4-14 for details.

1. Remove the SSB as described earlier.
2. Remove the PSU.
3. Remove the stand.
4. Remove the stand bracket.
5. Remove the mains plug together with its subframe.
6. Remove the woofer.
7. Remove the IR/LED panel as earlier described.
8. Remove the WiFi module.

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 Mechanical Instructions Q552.4E LA 4. EN 19

9. Remove the speakers together with their subframes.
10. Remove all remaining boards and cables that do not
belong to the LCD panel.
11. Remove the rims [1] and [2] at both sides of the set.
12. Lift the LCD panel from the bezel.
When defective, replace the whole unit.
4.5 Set Re-assembly
To re-assemble the whole set, execute all processes in reverse
order.
Notes:
While re-assembling, make sure that all cables are placed
and connected in their original position.
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

1
19220_069_120229.eps
120229

Figure 4-14 LCD panel removal

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 EN 20 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter: Automatic volume levelling (AVL).
5.1 Test Points Skip/blank of non-favourite pre-sets.
5.2 Service Modes
5.3 Stepwise Start-up How to Activate SDM
5.4 Service Tools For this chassis there are two kinds of SDM: an analogue SDM
5.5 Error Codes and a digital SDM. Tuning will happen according Table 5-1.
5.6 The Blinking LED Procedure Analogue SDM: use the standard RC-transmitter and key
5.7 Protections in the code 062596, directly followed by the MENU (or
5.8 Fault Finding and Repair Tips HOME) button.
5.9 Software Upgrading Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU (or
5.1 Test Points "HOME") button again.
As most signals are digital, it will be difficult to measure Analogue SDM can also be activated by grounding for a
waveforms with a standard oscilloscope. However, several key moment the solder path on the SSB, with the indication
ICs are capable of generating test patterns, which can be SDM (see Service mode pad).
controlled via ComPair. In this way it is possible to determine Digital SDM: use the standard RC-transmitter and key in
which part is defective. the code 062593, directly followed by the MENU (or
"HOME") button.
Perform measurements under the following conditions: Note: It is possible that, together with the SDM, the main
Service Default Mode. menu will appear. To switch it off, push the MENU (or
Video: Colour bar signal. "HOME") button again.
Audio: 3 kHz left, 1 kHz right.

5.2 Service Modes

Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
SDM
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section 5.4.1 ComPair).
19220_070_120229.eps
120229
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the Figure 5-1 Service mode pad
activation of the Service modes. For instance the old MENU
button is now called HOME (or is indicated by a house icon). After activating this mode, SDM will appear in the upper right
corner of the screen (when a picture is available).
5.2.1 Service Default Mode (SDM)
How to Navigate
Purpose When the MENU (or HOME) button is pressed on the RC
To create a pre-defined setting, to get the same transmitter, the TV set will toggle between the SDM and the
measurement results as given in this manual. normal user menu.
To override software protections detected by stand-by
processor and make the TV start up to the step just before How to Exit SDM
protection (a sort of automatic stepwise start-up). See Use one of the following methods:
section 5.3 Stepwise Start-up.
Switch the set to STAND-BY via the RC-transmitter.
To start the blinking LED procedure where only LAYER 2 Via a standard customer RC-transmitter: key in 00-
errors are displayed. (see also section 5.5 Error Codes). sequence.

Specifications
5.2.2 Service Alignment Mode (SAM)

Table 5-1 SDM default settings Purpose

To perform (software) alignments.
Region Freq. (MHz) Default system To change option settings.
Europe, AP(PAL/Multi) 475.25 PAL B/G To easily identify the used software version.
Europe, AP DVB-T 546.00 PID Video: 0B DVB-T To view operation hours.
06 PID PCR: 0B 06 PID
Audio: 0B 07
To display (or clear) the error code buffer.

How to Activate SAM

Via a standard RC transmitter: Key in the code 062596
directly followed by the INFO or OK button. After activating
SAM with this method a service warning will appear on the
All picture settings at 50% (brightness, colour, contrast).
screen, continue by pressing the OK button on the RC.
Sound volume at 25%.
All service-unfriendly modes (if present) are disabled, like:
Contents of SAM
(Sleep) timer.
Child/parental lock. Hardware Info.
Picture mute (blue mute or black mute).

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 Service Modes, Error Codes, and Fault Finding
A. SW Version. Displays the software version of the
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z).
AAAA= the chassis name.
B= the software branch version. This is a
sequential number (this is no longer the region
indication, as the software is now multi-region).
X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
B. STBY PROC Version. Displays the software
version of the stand-by processor.
C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched on/off, 0.5 hours is added to this number.
Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
Reset Error Buffer. When cursor right (or OK button)
pressed here, followed by the OK button, the error buffer
is reset.
Alignments. This will activate the ALIGNMENTS sub-
menu. See Chapter 6. Alignments.
Dealer Options. Extra features for the dealers.
Options. Extra features for Service. For more info
regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the OK button before
the options are stored, otherwise changes will be lost.
Initialize NVM. The moment the processor recognizes a
corrupted NVM, the initialize NVM line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
Initialize the NVM.
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, its advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code 062598 directly followed by the MENU (or "HOME")
button and XXX (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zeros. If the above action is
successful, the front LED will go out as an indication that the
RC sequence was correct. After the display option is changed
in the NVM, the TV will go to the Stand-by mode. If the NVM
was corrupted or empty before this action, it will be initialized
first (loaded with default values). This initializing can take up to
20 seconds.
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Q552.4E LA 5. EN 21
Display option code
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Figure 5-2 Location of Display Option Code sticker
Store - go right. All options and alignments are stored
when pressing cursor right (or the OK button) and then
the OK-button.
Operation hours display. Displays the accumulated total
of operation hours of the screen itself. In case of a display
replacement, reset to 0 or to the consumed operation
hours of the spare display.
SW Maintenance.
SW Events. In case of specific software problems, the
development department can ask for this info.
HW Events. In case of specific software problems, the
development department can ask for this info :
- Event 26: refers to a power dip, this is logged after
the TV set reboots due to a power dip.
- Event 17: refers to the power OK status, sensed even
before the 3 x retry to generate the error code.
Test settings. For development purposes only.
Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
Channel list, Personal settings, Option codes,
Alignments, Identification data (includes the set type
and prod code + all 12NC like SSB, display, boards),
History list. The All item supports to upload all several
items at once.
First a directory repair\ has to be created in the root
of the USB stick.
To upload the settings, select each item separately, press
cursor right (or the OK button), confirm with OK and
wait until the message Done appears. In case the
download to the USB stick was not successful, Failure will
be displayed. In this case, check if the USB stick is
connected properly and if the directory repair is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customers
TV settings and to store them into another SSB.
Download from USB. To download several settings from
the USB stick to the TV, same way of working needs to be
followed as described in Upload to USB. To make sure
that the download of the channel list from USB to the TV is
executed properly, it is necessary to restart the TV and
tune to a valid preset if necessary. The All item supports
to download all several items at once.
NVM editor. For NET TV the set type number must be
entered correctly.
Also the production code (AG code) can be entered here
via the RC-transmitter.
Correct data can be found on the side/rear sticker.
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 EN 22 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding
How to Navigate
In SAM, the menu items can be selected with the
CURSOR UP/DOWN key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the CURSOR UP/DOWN key to
display the next/previous menu items.
With the CURSOR LEFT/RIGHT keys, it is possible to:
(De) activate the selected menu item.
(De) activate the selected sub menu.
With the OK key, it is possible to activate the selected
action.
How to Exit SAM
Use one of the following methods:
Switch the TV set to STAND-BY via the RC-transmitter.
Via a standard RC-transmitter, key in 00 sequence, or
select the BACK key.
5.2.3 Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
When in this chassis CSM is activated, a test pattern will be
displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second
Green). This test pattern is generated by the PNX51X0
(located on the 200Hz board as part of the display). So if this
test pattern is shown, it could be determined that the back end
video chain (PNX51X0 and display) is working.For TV sets
without the PNX51X0 inside, every menu from CSM will be
used as check for the back end chain video.
When CSM is activated and there is a USB stick connected to
the TV set, the software will dump the CSM content to the USB
stick. The file (CSM_model number_serial number.txt) will be
saved in the root of the USB stick. This info can be handy if no
information is displayed.
When in CSM mode (and a USB stick connected), pressing
OK will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.txt)
contains:
The normal CSM dump information,
All items (from SAM load to USB, but in readable format),
Operating hours,
Error codes,
Software/Hardware event logs.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the red
button and key in serial digits 2679 (same keys to form the
word COPY with a cellphone). A file Dump_model
number_serial number.bin will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped.
Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED. Only the latest error is displayed (see also
section 5.5 Error Codes).
How to Activate CSM
Key in the code 123654 via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
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How to Navigate
By means of the CURSOR-DOWN/UP knob on the RC-
transmitter, can be navigated through the menus.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
General
Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this. The update
can also be done via the NVM editor available in SAM.
Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee in a possibility to
do this. The update can also be done via the NVM editor
available in SAM.
Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
12NC display. Shows the 12NC of the display.
12NC supply. Shows the 12NC of the power supply.
12NC 200Hz board. Shows the 12NC of the 200Hz Panel
(when present).
12NC AV PIP. Shows the 12NC of the AV PIP board
(when present).
Software versions
Current main SW. Displays the build-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
Stand-by SW. Displays the build-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
Upgrading).
Example: STDBY_83.84.0.0.
e-UM version. Displays the electronic user manual
software-version (12NC version number). Most significant
number here is the last digit.
FPGA software.
Quality items
Signal quality. Bad / average /good (not for DVB-S).
Ethernet MAC address. Displays the MAC address
present in the SSB.
Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
BDS key. Indicates if the set is in the BDS status.
CI module. Displays status if the common interface
module is detected.
CI + protected service. Yes/No.
Event counter :
S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)
S : 0000 000X (number of software events : SW EVENT-
LOG #(events)
H : 000X 0000(number of hardware errors)
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 Service Modes, Error Codes, and Fault Finding Q552.4E LA 5. EN 23

H : 0000 000X (number of hardware events : SW EVENT-
LOG #(events).
How to Exit CSM
Press MENU (or "HOME") / Back key on the RC-transmitter.
5.3 Stepwise Start-up
When the TV is in a protection state due to an error detected by
stand-by software (error blinking is displayed) and SDM is
activated via shortcutting the SDM solder path on the SSB, the
TV starts up until it reaches the situation just before protection.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up
in this mode with a faulty FET 7U0X (diagram B02A) is done,
you can destroy all ICs supplied by the +1V8 and +1V1, due to
overvoltage (12V on XVX-line). It is recommended to measure
first the FET 7U0X or others FETs on shortcircuit before
activating SDM via the service pads.
The abbreviations SP and MP in the figures stand for:
SP: protection or error detected by the Stand-by
Processor.
MP: protection or error detected by the MIPS Main
Processor.

Mains
off Mains
on

- WakeUp requested
WakeUp
- Acquisition needed
requested
- Tact switch pushed

St by Semi Active
- stby requested and
no data Acquisition St by - St by requested
required - tact SW pushed

Tact switch
pushed
WakeUp
requested
- Tact switch pushed
(SDM)
- last status is hibernate
GoToProtection
after mains ON
Hibernate
GoToProtection

Protection

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Figure 5-3 Transition diagram

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 EN 24 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

Off
Mains is applied
Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.

st-by P resets

Initialise I/O pins of the st-by P:

- Switch reset-AVC LOW (reset state)
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-USB LOW (reset state) If the protection state was left by short circuiting the
- Switch reset-DVBs LOW (reset state) SDM pins, detection of a protection condition during
- keep Audio-reset and Audio-Mute-Up HIGH startup will stall the startup. Protection conditions in a
- Switch CTRL-DISP3 LOW(2D mode) playing set will be ignored. The protection mode will
- Switch BL-DIM LOW not be entered.
- Switch BL-I-CTRL LOW

- Switch Audio-Reset high.

start keyboard scanning, RC detection. Wake up reasons are It is low in the standby mode if the standby
off. mode lasted longer than 10s.

Switch ON Platform and display supply by switching

LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power

is switched on, followed by the +1V2 DCDC converter

Detect2 is moved to an interrupt. The detection is on

interrupt base now
12V error:
Detect2 high received No
Layer1: 3
within 2 seconds?
Layer2: 16

Yes
Enter protection
Enable the DCDC converters
(ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set IC slave address

of Standby P to (A0h)

Detect EJTAG debug probe

(pulling pin of the probe interface to An EJTAG probe (e.g. WindPower ICE probe) can be
ground by inserting EJTAG probe) connected for Linux Kernel debugging purposes.

EJTAG probe Yes

connected ?

No

No No
Cold boot?

Yes

Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism

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Figure 5-4 Off to Semi Stand-by flowchart (part 1)

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 Service Modes, Error Codes, and Fault Finding Q552.4E LA 5. EN 25

Reset-system is switched HIGH by the Reset-system is switched HIGH by the

AVC releases Reset-Ethernet, Reset-USB and
This cannot be done through the bootscript,
the I/O is on the standby P
Timing need to be updated if
more mature info is available.
No
AVC at the end of the bootscript AVC at the end of the bootscript
No
AVC releases Reset-Ethernet, Reset-USB and
Reset-DVBs when the end of the AVC boot- Reset-DVBs when the end of the AVC boot-
script is detected script is detected
No
Reset-Audio and Audio-Mute-Up are Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the switched by MIPS code later on in the
startup process startup process
Bootscript ready
in 1250 ms?
Wake up reason
coldboot & not semi- Startup screen shall only be visible when
standby? there is a coldboot to an active state end
situation. The startup screen shall not be
visible when waking up for reboot
yes reasons or waking up to semi-standby
conditions or waking up to enter
Hibernate mode.
Startup screen cfg file
present?
The first time after the option turn on of
the startup screen or when the set is
virgin, the config file is not present and
hence the startup screen will not be
shown.
Yes

Yes
85500 sends out startup screen

Set IC slave address

of Standby P to (60h)
85500 & FPGA start up the display.

RPC start (comm. protocol)

Startup screen visible

Flash to Ram
No
image transfer succeeded
within 30s?
Code =
Layer1: 2 See the Semi-standby to On
Layer2: 15 Yes description for the detailed display startup
sequence.
During the complete display time of the
Code = Startup screen, the preheat condition of
Switch AVC PNX85500 in No SW initialization
Layer1: 2 100% PWM is valid.
reset (active low) succeeded
Layer2: 53
within 20s?

Wait 10ms Yes

Enable Alive check mechanism

Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.

MIPS reads the wake up reason Wait until AVC starts to

from standby P. communicate
Wait 5ms

switch off the remaining DC/DC Initialize audio

converters

Switch Standby I/O line high Initialize tuner and channel decoders
3-th try?
and wait 4 seconds

Yes Initialize source selection

Blink Code as
error code Initialize video processing IC's
- local contrast FPGA
- 5120's, 21/9 scaler and MPC if present

Enter protection initialize AutoTV by triggering CHS AutoTV Init interface

Initialize Ambilight with Lights off.

Semi-Standby

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Figure 5-5 Off to Semi Stand-by flowchart (part 2)

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 EN 26 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

The assumption here is that a fast toggle (<2s) can

Semi Standby
only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be Wait until previous on-state is left more than 2
made in less than 2s, because the standby state will seconds ago. (to prevent LCD display problems)
be maintained for at least 4s.
CPipe already generates a valid output
clock in the semi-standby state: display Assert RGB video blanking and audio mute
startup can start immediately when leaving
the semi-standby state.

Display already on? Yes

(splash screen)

No

Send display startup and shutdown

targets to FPGA

Switch on the display power by

switching LCD-PWR-ONn low

Wait x ms

Switch on LVDS output in the 85500 Switch Off LCD

The exact timings to
switch on the Backlight
Initialize audio and video
display (LVDS
Switch on the display By sending I2C processing IC's and functions
delay, lamp delay)
Display_On command to FPGA according needed use case.
are defined in the Wait 10ms(tbc)
display file.
Set BL-DIM & BL-I-CTRL according to Display file
(For Splash Screen, fix BL-DIM at high[100%], BL-I-CTRL at low[0%])

Delay BL-ON with the sum of LVDS Wait 10ms(tbc)

delay and the Lamp delay indicated in
the display file

Switch on LCD backlight (BL-ON)

Start POK line detection Wait until valid and stable audio and video, corresponding to the
algorithm requested output is delivered by the AVC

Switch Audio-Reset low and wait 5ms

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
return

unblank the video.

Switch on the Ambilight functionality according the last status

settings.

Startup screen Option

and Installation setting
Photoscreen ON?

Yes

Display cfg file present

and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
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Figure 5-6 Semi Stand-by to Active flowchart

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Service Modes, Error Codes, and Fault Finding Q552.4E LA 5. EN 27

Active

Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground

(I/O: audio reset)
And wait 5ms

Switch off POK line detection

algorithm

switch off LCD backlight

switch off Ambilight

Mute all video outputs

Wait until Ambilight has faded out:
Output power Observer should be zero

CTRL-DISP3=high? Yes
(3D mode?)

Switch CTRL-DISP3 to
LOW
No

Wait x ms (display file)

Switch off the display by sending I2C

The exact timings to Display_Off command to FPGA
switch off the
display (LVDS
delay, BL-ON Switch off LVDS output in 85500
delay) are defined
in the display file.
Wait x ms

Switch off the display power by

switching LCD-PWR-ONn high

Semi Standby
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Figure 5-7 Active to Semi Stand-by flowchart

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 EN 28 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

Semi Stand by

If ambientlight functionality was used in semi-standby

(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

Switch Memories to self-refresh (this creates a more

stable condition when switching off the power).

Switch AVC system in reset state (reset-system and

reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Wait 10ms

Disable all supply related protections and switch off

the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the

Standby I/O line

Important remarks:

release reset audio 10 sec after entering

standby to save power

Also here, the standby state has to be

maintained for at least 4s before starting
another state transition.
Stand by

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Figure 5-8 Semi Stand-by to Stand-by flowchart

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 Service Modes, Error Codes, and Fault Finding Q552.4E LA 5. EN 29

5.4 Service Tools 5.5 Error Codes

5.4.1 ComPair 5.5.1 Introduction

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the P
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.
How to Connect
This is described in the chassis fault finding database in
ComPair.
TO TV
TO
UART SERVICE
TO
I2C SERVICE
CONNECTOR CONNECTOR
ComPair II
Multi
RC in function
RC out
Optional Power Link/ Mode
Switch Activity I2C
PC
ComPair II Developed by Philips Brugge
Optional power
HDMI
I2C only
Figure 5-9 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be
blown!
How to Order
ComPair II order codes:
ComPair II interface: 3122 785 91020.
Software is available via the Philips Service web portal.
ComPair UART interface cable for Q55x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: When you encounter problems, contact your local
support desk.
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.
New in this chassis is the way errors can be displayed:
If no errors are there, the LED should not blink at all in
CSM or SDM. No spacer must be displayed as well.
There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2).
LAYER 1 errors are one digit errors.
LAYER 2 errors are 2 digit errors.
In protection mode.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
TO
UART SERVICE In CSM mode.
CONNECTOR
When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
In SDM mode.
When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
RS232 /UART
Error display on screen.
In CSM no error codes are displayed on screen.
In SAM the complete error list is shown.
Basically there are three kinds of errors:
Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section 5.6 The Blinking LED Procedure).
Errors detected by the Stand-by software which not
5V DC lead to protection. In this case the front LED should blink
the involved error. See also section 5.5 Error Codes, 5.5.4
Error Buffer. Note that it can take up several minutes
10000_036_090121.eps
091118 before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.
5.5.2 How to Read the Error Buffer
Use one of the following methods:
On screen via the SAM (only when a picture is visible).
E.g.:
00 00 00 00 00: No errors detected
23 00 00 00 00: Error code 23 is the last and only
detected error.
37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note that no protection errors can be logged in the
error buffer.

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 EN 30 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

Via the blinking LED procedure. See section 5.5.3 How to content, as this history can give significant information). This to
Clear the Error Buffer. ensure that old error codes are no longer present.
Via ComPair. If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
5.5.3 How to Clear the Error Buffer code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Use one of the following methods:
Via error bits in the status registers of ICs.
By activation of the RESET ERROR BUFFER command
in the SAM menu. Via polling on I/O pins going to the stand-by processor.
Via sensing of analog values on the stand-by processor or
If the content of the error buffer has not changed for 50+
the PNX8550.
hours, it resets automatically.
Via a not acknowledge of an I2C communication.
5.5.4 Error Buffer
Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
In case of non-intermittent faults, clear the error buffer before
problems wait 2 minutes from start-up onwards, and then
starting to repair (before clearing the buffer, write down the check if the front LED is blinking or if an error is logged.

Table 5-2 Error code overview

Monitored Error/ Error Buffer/

Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board
I2C3 2 13 MIPS E BL / EB SSB SSB
I2C2 2 14 MIPS E BL / EB SSB SSB
I2C4 2 18 MIPS E BL / EB SSB SSB
PNX doesnt boot (HW cause) 2 15 Stby P P BL SSB SSB
12V 3 16 Stby P P BL / Supply
Inverter or display supply 3 17 MIPS E EB / Supply
HDMI mux 2 23 MIPS E EB Sil9x87A SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
AV-PIP board 8 25 MIPS E EB AV PIP board
Channel dec DVB-C 2 27 MIPS E EB TDA10024 SSB
Channel dec 2 27 MIPS E EB TC90157 SSB
Channel dec DVBT2 2 27 MIPS E EB CXD2820 SSB
Channel DVB-S 2 28 MIPS E EB STV0903 SSB
14v/18v OLP LNB controller 2 32 MIPS E EB SSB
LNB controller R3 2 31 MIPS E EB LNBH 23 SSB
LNB controller R4 2 31 MIPS E EB LNBH 25 SSB
Tuner1 2 34 Stby P P EB DTT71300 SSB
main NVM 2 35 MIPS E x STM24C64 SSB
Tuner DVB-S 2 36 MIPS E EB STV6110 SSB
Class-D 2 37 MIPS E EB TAS5711PHP SSB
FPGA backlight 2 38 MIPS E EB LX 4 SSB
Temperature sensor LED driver/TCON 7 42 MIPS E EB LM 75 Temperature sensor
Temperature sensor SSB/set 2 42 MIPS E EB LM 75 Temperature sensor
FAN 7 43 MIPS E EB FAN
FPGA PQ 2 45 MIPS E EB LX 25 SSB
MIPS doesnt boot (SW cause) 2 53 Stby P P BL PNX8550 SSB

Extra Info
Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8 Fault Finding and Repair Tips, 5.8.6
Logging). Its shown that the loggings which are generated
by the main software keep continuing. In this case
diagnose has to be done via ComPair.
Error 13 (I2C bus 3, SSB bus blocked). Current situation:
when this error occurs, the TV will constantly reboot due to
the blocked bus. The best way for further diagnosis here, is
to use ComPair.
Error 14 (I2C bus 2, TV set bus blocked). Current
situation: when this error occurs, the TV will constantly
reboot due to the blocked bus. The best way for further
diagnosis here, is to use ComPair.
Error 18 (I2C bus 4, Tuner bus blocked). In case this bus
is blocked, short the SDM solder paths on the SSB during
startup, LAYER error 2 = 18 will be blinked.
Error 15 (PNX8550 doesnt boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8550
(supplies not OK, PNX 8550 completely dead, I2C link
between PNX and Stand-by Processor broken, etc...).
When error 15 occurs it is also possible that I2C1 bus is
blocked (NVM). I2C1 can be indicated in the schematics as
follows: SCL-UP-MIPS, SDA-UP-MIPS.
Other root causes for this error can be due to hardware
problems regarding the DDRs and the bootscript reading
from the PNX8550.
Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
LAYER 2 error = 16.
Error 17 (Invertor or Display Supply). Here the status of
the Power OK is checked by software, no protection will
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
Error 23 (HDMI). When there is no I2C communication
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark: this only
works for TV sets with an I2C controlled screen included.

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 Service Modes, Error Codes, and Fault Finding
Error 28 (Channel dec DVB-S). When there is no I2C
communication towards the DVB-S channel decoder,
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 31 (Lnb controller). When there is no I2C
communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
procedure when SDM is switched on. All service modes
(CSM, SAM and SDM) are accessible during this failure,
observed in the Uart logging as follows: "<< ERRO >>>
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Error 36 (Tuner DVB-S). When there is no I2C
communication towards the DVB-S tuner during start-up,
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched on.
Error 37 (Class-D amplifier). When there is no I2C
communication towards the TAS5731PHP Class-D
Amplifier during start-up, LAYER 2 error = 37 will be logged
and displayed via the blinking LED procedure when SDM
is switched on.
Note: TV in normal working condition, but without Audio out
from speaker.
Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
Error 53. This error will indicate that the PNX8550 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
5.6 The Blinking LED Procedure
5.6.1 Introduction
The blinking LED procedure can be split up into two situations:
Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-2 Error code
overview) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
Blinking LED procedure LAYER 2 error. Via this
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
2 digits (see table 5-2 Error code overview) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
regarding the failure of the defective board.
Important remark:
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.
When one of the blinking LED procedures is activated, the front
LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. n long blinks (where n = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. n short blinks (where n= 1 to 9)
4. A pause of approximately 3 s,
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Q552.4E LA 5. EN 31
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).
6. The sequence starts again.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
5.6.2 How to Activate
Use one of the following methods:
Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in normal operation
mode or automatically when the error/protection is
monitored by the Stand-by processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether error devices are
mentioned. (see section 5.8 Fault Finding and Repair
Tips, 5.8.6 Logging).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
normal operation mode or when SDM (via hardware pins)
is activated when the tv set is in protection.
5.7 Protections
5.7.1 Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.
Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section 5.3 Stepwise Start-up).
5.7.2 Hardware Protections
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D audio amplifier (item
7D60; see diagram B06A) and puts the amplifier in a
continuous burst mode (cyclus approximately 2 seconds).
2012-Jun-29
 EN 32 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding
Repair Tip
There still will be a picture available but no sound. While
the Class D amplifier tries to start-up again, the cone of the
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again. The headphone amplifier will
also behaves similar.
5.8 Fault Finding and Repair Tips
Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info.
5.8.1 Audio Amplifier
The Class D-IC 7D60 has a powerpad for cooling. When the IC
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class D-
IC could break down in short time.
5.8.2 AV PIP
To check the AV PIP board (if present) functionality, a
dedicated tespattern can be invoke as follows: select the
multiview icon in the User Interface and press the OK
button. Apply for the main picture an extended source, e.g.
HDMI input. Proceed by entering CSM (push 123654 on the
remote control) and press the yellow button. A coloured
testpattern should appear now, generated by the AV PIP board
(this can take a few seconds).
5.8.3 CSM
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)
5.8.4 DC/DC Converter
Description basic board
The basic board power supply consists of 4 DC/DC converters
and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver:
+1V1 supply voltage (1.15V nominal), for the core voltage
of PNX855xx, stabilized close to the point of load;
SENSE+1V1 signal provides the DC-DC converter the
needed feedback to achieve this.
+1V8 supply voltage, for the DDR2 memories and DDR2
interface of PNX855xx.
+3V3 supply voltage (3.30V nominal), overall 3.3 V for
onboard ICs, for non-5000 series SSB diversities only.
+5V (5.15V nominal) for USB, WIFI and Conditional
Access Module and +5V5-TUN for +5V-TUN tuner
stabilizer.
The linear stabilizers are providing:
+1V2 supply voltage (1.2V nominal), stabilized close to
PNX855xx device, for various other internal blocks of
PNX855xx; SENSE+1V2 signal provides the needed
feedback to achieve this.
+2V5 supply voltage (2.5V nominal), for LVDS interface
and various other internal blocks of PNX855xx. Stabilizer
7UC0 is used (diagram B02B).
+3V3 supply voltage (3V3 nominal), is provided by 7UD1
(diagram B02C); the 12 V to 3V3 DC-DC converter delivers
the supply voltage to the PNX855xx.
+5V-TUN supply voltage (5V nominal) for tuner and IF
amplifier.
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+3V3-STANDY (3V3 nominal) is the permanent voltage,
supplying the Stand-by microprocessor inside PNX855xx.
Supply voltage +1V1 is started immediately when +12V voltage
becomes available (+12V is enabled by STANDBY signal when
"low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
are switched "on" by signal ENABLE-3V3 when "low", provided
that +12V (detected via 7U40 and 7U41) is present.
+12V is considered OK (=> DETECT2 signal becomes "high",
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
can be started up) if it rises above 10V and doesnt drop below
9V5. A small delay of a few milliseconds is introduced between
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.
Description DVB-S2:
LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7TP2 (diagram B03B) LNB supply control IC. It provides
supply voltage that feeds the outdoor satellite reception
equipment.
+3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
via a 5V to 1V DC-DC converter and is stabilized at the
point of load (channel decoder) by means of feedback
signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
are generated via linear stabilizers from +5V-DVBS that by
itself is generated via the first conversion channel of 7TP2.
At start-up, +24V becomes available when STANDBY signal is
"low" (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
inside 7TP2 are activated. Initially only the 24V to 5V converter
(channel 1 of 7TP2 generating +5V-DVBS) will effectively work,
while +V-LNB is held at a level around 11V7 via diode 6TP5.
If +24V drops below +15V level then the DVB-S2 supply will
stop, even if +3V3 is still present.
Note: +24V audio is used in 4000 series, 4300 & 5000 series
use +12V audio.
Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power on via the mains cord,
presuming that the stand-by microprocessor and the external
supply are operational. Take STANDBY signal "high"-to-"low"
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes "low") then +1V1 is started immediately.
After ENABLE-3V3 goes "low", all the other supply voltages
should rise within a few milliseconds.
Tips
Behaviour comparison with a reference TV550 platform
can be a fast way to locate failures.
If +12V stays "low", check the integrity of fuse 1U40.
Check the integrity (at least no short circuit between drain
and source) of the power MOS-FETs before starting up the
platform in SDM, otherwise many components might be
damaged. Using a ohmmeter can detect short circuits
between any power rail and ground or between +12V and
any other power rail.
Short circuit at the output of an integrated linear stabilizer
(7UC0) will heat up this device strongly.
Switching frequencies should be 500 kHz ...600 kHz for
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
to 1.1 V DC-DC converter 900 kHz is used.
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 Service Modes, Error Codes, and Fault Finding Q552.4E LA 5. EN 33

5.8.5 Exit Factory Mode
When an F is displayed in the screens right corner, this
means the set is in Factory mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the VOLUME minus button on the TVs local keyboard for 10
seconds (this disables the continuous mode).
Then push the SOURCE button for 10 seconds until the F
disappears from the screen.
5.8.6 Logging
When something is wrong with the TV set (f.i. the set is
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a ComPair UART-
cable (3138 188 75051) from the service connector in the TV to
the multi function jack at the front of ComPair II box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.
- Select the correct database (open file Q55X.X, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. logging)
in the Connection Description box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the Display Option Code (useful when there is no picture),
look for item DisplayRawNumber in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for error devices in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.7 Guidelines Uart logging
Description possible cases:
Uart loggings are displayed:
When Uart loggings are coming out, the first conclusion we
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The PNX855xx is able to read and write in the DRAMs.
We can not yet conclude : Flash RAM and DRAMs are fully
operational/reliable.There still can be errors in the data
transfers, DRAM erros, read/write speed and timing
control.
Some failures are indicated by error codes in the logging,
check with error codes table (see Table 5-2 Error code
overview).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).
I2C bus error mentioned as e.g.: I2C bus 4 blocked.
Not all failures or error messages should be interpreted as
fault.For instance root cause can be due to wrong option
codes settings => e.g. DVBS2Suppoprted : False/True.
In the Uart log startup script we can observe and check the
enabled loaded option codes.
Defective sectors (bad blocks) in the Nand Flash can also be
reported in the logging.
Startup in the software upgrade application and observe the
Uart logging:
Starting up the TV set in the Manual Software Upgrade mode
will show access to USB, meant to copy software content from
USB to the DRAM.Progress is shown in the logging as follows:
cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
40505344 of 40607744 bytes programmed.
Startup in Jett Mode:
Check Uart logging in Jet mode mentioned as : JETT UART
READY.
Uart logging changing preset:
=> COMMAND: calling DFB source = RC6, system=0, key = 4.
5.8.8 Loudspeakers
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!
5.8.9 PSL
In case of no picture when CSM (test pattern) is activated and
backlight doesnt light up, its recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).
5.8.10 Tuner
Attention: In case the tuner is replaced, always check the tuner
options!
5.8.11 Display option code
Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.

No Uart logging at all: While in the download application (start up in TV mode + OK

In case there is no Uart logging coming out, check if the button pressed), the display option code can be changed via
startup script can be send over the I2C bus (3 trials to 062598 HOME XXX special SAM command (XXX=display
startup) + power supplies are switched on and stable. option in 3 digits).
No startup will end up in a blinking LED status : error
LAYER 1 = 2, error LAYER 2 = 53 (startup with SDM
solder paths short).
Error LAYER 2 = 15 (hardware cause) is more related to
a supply issue while error LAYER 2 = 53 (software cause)
refers more to boot issues.

Uart loggings reporting fault conditions, error messages, error

codes, fatal errors:
Failure messages should be checked and investigated.For
instance fatal error on the PNX51x0: check startup of the
back-end processor, supplies..reset, I2C bus. => error
mentioned in the logging as: *51x0 failed to start by itself*.

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 EN 34 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

5.8.12 SSB Replacement For a more general overview of steps to follow, refer to figure
5-12 SSB replacement flowchart.
Follow the instructions in the flowchart in case a SSB has to be
exchanged. See table 5-3 SSB replacement instructions. Table 5-3 SSB replacement instructions

Step # Action to do Advise / Attention points / Remarks

1 Ensure ESD protection by using a wristband -
2 If SSB is still functional: Go via SAM to upload to USB and copy Personal Upload to USB: A directory repair will be created on the USB, and all data will be copied in this
settings - Option codes - Alignments (Presets) - Set Identification. directory. On sets with software before Q552-xx-140-x-x, there was an issue by copying the
Advice: because of differences in memory allocation, it is advised to upgrade program map table, so it is advised to reinstall the programs from Virgin mode instead of using
main SW before copying data from existing SSB. Copy of Preset list is copy via USB.
possible from normal user interface.
3 Disconnect set from mains and from antenna. Safety and ESD!
4 Open the set and disconnect LVDS flat cable. Disconnect other cables / Always take care for ESD! Be extra careful when removing connectors!
connections.
5 Dismount the (defective) SSB from the set. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-10 and Figure 5-11.
6 Place new SSB in the set, and fixate/mount carefully. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-10 and Figure 5-11.
7 Connect PSU and other connectors. Insert the optional WiFi module. Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the
optional WiFi module: a defective WiFi module can give reboots or no start-up of the SSB. In this
case do a trial without WiFi module.
8 Connect LVDS connector(s). Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage
the LCD display. Check if flat cables are fitted correctly before closing the connector lock.
9 Connect set to mains and switch TV On. Check start-up of the set, backlight switch On
10 If the set does not start (or reboots) check: Power supply connector must snap into the socket.
- The connectors from the power supply,
- The power supply cable and connection pins,
- LVDS cable connection.
11 Before programming the new SSB, upgrade to latest software. If set is starting Some SSBs will start-up in software upgrade mode, and software needs to be installed before you
up in software upgrade mode, then first install new software via software can program the Display Option codes. Its adviced to use an autorun.upg file for software
Upgrade Menu or via the autorun.upg file. upgrade, this in case you have no OSD on the screen.
12 If set is starting up without picture or menu (OSD), first program the correct Use blind service mode 062598 + Home button, directly followed by the
Display Option codes. Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.
13 Go to SAM and program Set type and Serial number. This is possible via Programming Set type and Serial number is mandatory to have all functionality of the set, like
the NVM editor and virtual keyboard. In case personal settings were DLNA, Net TV For certain sets you may need to use ComPair for this.
recovered from the defective SSB, you can use an Upload from USB.
14 Check if option codes are correct, and keys are present. SSBs with integrated Attention, check if Tuner on defect board and new board is the same. If not, the same Tuner option
TCON needs TCON alignment in SAM. Adjust White point colour temperature code nbr 1 needs to be adapted (add or substract 512). refer to General Service Info GSC_89308.
alignment for normal, warm and cool according to values in section 6.3.1. Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair.
15 Update to latest software (Standby and main software). This step is necessary Even when the SSB already has the latest software, it is mandatory to upgrade again the software
to make sure that the (optional) 200 Hz T-CON board has the latest software. to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated
Display drive, and White point colour temperature needs to be aligned! See software is loaded, from the main processor via the LVDS connection, to upgrade the
section 6.3.1. 200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is
available. See General Service info GSC_85590.
16 Once the set is playing, check cable connection between PSU and SSB, by Check the two power connectors 1M95 and 1M99. Bad contact or bad connection here can give
moving the cable if there are no bad connections. reboots.
17 Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type It is mandatory to fill in the E-DDF form (see the At Your Service web portal).
and TV serial number.
18 Install presets or check if all presets are OK. Check in CSM if Type number, Special attention for Standby software: check if Standby software ID is matching with the D-RAMs
Serial number, Main and Standby software are correct. mounted on the SSB (2 Elpida = 73, 4 Elpida = 64, 2 Hynix = 72, 4 Hynix = 63).
19 Check connectivity to Net TV and DLNA. Check AmbiLight functionality. Only for sets having these functionalities.
20 Inform customer about Memory Card, USB, or Hard drive PVR (Personal Inform customer that previous recordings made on Memory Card (movie download), USB, or Hard
Video Recording) recordings. drive will be lost. USB or Hard drive needs to be re-formatted and matched with new SSB (WDRM
Keys!).

SSB fixation points

Significant risk of damaging the board

by the fixation point

Blue arrows: traces of friction

Red arrows: damaged components

19070_201_110728.eps 19070_202_110728.eps
110804 110804

Figure 5-10 Mounting attention points [1/2] Figure 5-11 Mounting attention points [2/2]

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 Service Modes, Error Codes, and Fault Finding Q552.4E LA 5. EN 35

In st ru ct io n n o t e SSB rep lacem en t Q55x.x

Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder upgrades in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No

Yes

C onnect the U SB stick to the set,

go to SAM and save the current TV settings via Upload to USB

1. D ismount the defective SSB.

2. Replace the SSB by a Service SSB.

Start-up the set

Due to a possible wrong display option code in the received Service
SSB (NVM), its possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback). Set behaviour?
No pictur e displayed Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB,

and enable the UART logging on the PC. Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.

1) Plug the USB stick into the TV set and select

3) Plug the prepared USB stick into the TV set. Follow the the autorun .upg file in the displayed browser.
instructions in the UART log file, press Right cursor key to enter
the list. Navigate to the autorun.upg file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press Ok.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and Ok to start flashing the main
TV software. Printouts like: L: 1-100%, V: 1-100% and
P: 1-100% should be visible now in the UART logging.

3) Wait until the message Operation successful ! is displayed

5) Wait until the message Operation successful ! is logged in and remove all inserted media. Restart the TV set.
the UART log and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where
xxx is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the Display Option code, the set is going to

Standby
(= validation of code)

Restart the set

No

Connect PC via the ComPair interface to Service connector.

Saved settings
on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Yes

Open ComPair browser Q54x
In case of settings reloaded from USB, the set type,
Go to SAM and reload settings serial number, display 12 NC, are automatically stored
via Download from USB function. when entering display options.
Program set type number, serial number, and display 12 NC
Program E - DFU if needed.

If not already done:

Check latest software on Service website. - Check if correct display option code is programmed.
Update main and Stand-by software via USB. - Verify option codes according to sticker inside the set.
- Default settings for white drive > see Service Manual.
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.

Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End Q55x.E SSB Board swap ER on behalf of VDS

Updated 28-07-2011

19070_200_110728.eps
111103

Figure 5-12 SSB replacement flowchart

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 EN 36 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the An F is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10
seconds

- Press the SOURCE button for 10 seconds until the F disappears

from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced

with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct

disabling of the Factory mode.

Program display option code

via 062598 MENU, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering display option code, the set is

going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-13 SSB replacement flowchart - Factory mode

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 Service Modes, Error Codes, and Fault Finding
Figure 5-14 SSB start-up
5.9 Software Upgrading
5.9.1 Introduction
The set software and security keys are stored in a NAND-
Flash, which is connected to the PNX855xx.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the electronic User Manual.
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if the CI + key, MAC address.. are valid.
For the correct order number of a new SSB, always refer to the
Spare Parts list!
5.9.2 Main Software Upgrade
The UpgradeAll.upg file is only used in the factory.
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Q552.4E LA 5. EN 37
18753_211_100811.eps
110810
Automatic Software Upgrade
In normal conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the AUTORUN.UPG
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_prod.zip). This can also be done by the
consumers themselves, but they will have to get their software
from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The autorun.upg file
must be placed in the root of the USB stick.
How to upgrade:
1. Copy AUTORUN.UPG to the root of the USB stick.
2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.
Manual Software Upgrade
In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the OK button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use
a TV remote in DVD mode). Keep the OK button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.
Attention!
In case the download application has been started manually,
the autorun.upg will maybe not be recognized.
What to do in this case:
1. Create a directory UPGRADES on the USB stick.
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 EN 38 5. Q552.4E LA Service Modes, Error Codes, and Fault Finding

2. Rename the autorun.upg to something else, e.g. to

software.upg. Do not use long or complicated names,
keep it simple. Make sure that AUTORUN.UPG is no
longer present in the root of the USB stick.
3. Copy the renamed upg file into this directory.
4. Insert USB stick into the TV.
5. The renamed upg file will be visible and selectable in the
upgrade application.

Back-up Software Upgrade Application

If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the back-up software upgrade
application.
How to start the back-up software upgrade application
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the CURSOR DOWN-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.
3. The back-up software upgrade application will start.

5.9.3 Stand-by Software Upgrade via USB

In this chassis it is possible to upgrade the Stand-by software

via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory UPGRADES on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbyFactory_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section
Manual Software Upgrade.
5. Select the appropriate file and press the OK button to
upgrade.

5.9.4 Content and Usage of the One-Zip Software File

Below the content of the One-Zip file is explained, and

instructions on how and when to use it.
AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the
program instruction and software content, needed to
upgrade the ambilight CPLD on the TV550 platform.
BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the
BalanceFPGA software in upg format.
FUS_Q555X_x.x.x.x_prod.zip. Contains the
autorun.upg which is needed to upgrade the TV main
software and the software download application.
PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the
PNX5130 software in upg format.
StandbySW_Q555X_x.x.x.x_prod.zip. Contains the
StandbyFactory software in upg format.
ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM
content. Must be programmed via ComPair or can be
loaded via USB, be aware that all alignments stored in
NVM are overwritten here.

5.9.5 UART logging 2K10 (see section 5.8 Fault Finding and
Repair Tips, 5.8.6 Logging)

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 Alignments Q552.4E LA 6. EN 39

6. Alignments
Index of this chapter: LATAM models: an NTSC M TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 61.25 MHz
6.2 Hardware Alignments (channel 3).
6.3 Software Alignments
6.4 Option Settings 6.3.1 White Point
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes
Choose TV menu, Setup, More TV Settings and then
Picture and set picture settings as follows:
6.1 General Alignment Conditions Picture Setting
Perform all electrical adjustments under the following
Contrast 100
conditions:
Brightness 50
Power supply voltage (depends on region):
Colour 0
AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
Light Sensor Off
AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
Picture format Unscaled
EU: 230 VAC / 50 Hz ( 10%).
LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
In menu Picture, choose Pixel Plus HD and set picture
US: 120 VAC / 60 Hz ( 10%).
settings as follows:
Connect the set to the mains via an isolation transformer
with low internal resistance. Picture Setting

Allow the set to warm up for approximately 15 minutes. Dynamic Contrast Off

Measure voltages and waveforms in relation to correct Dynamic Backlight Off

ground (e.g. measure audio signals in relation to Colour Enhancement Off

AUDIO_GND). Gamma 0

Caution: It is not allowed to use heat sinks as ground.

Test probe: Ri > 10 M, Ci < 20 pF. Go to the SAM and select Alignments-> White point.
Use an isolated trimmer/screwdriver to perform
alignments. White point alignment LCD screens:
Use a 100% white screen (format: 720p50) to the HDMI
6.1.1 Alignment Sequence input and set the following values:
Colour temperature: Cool.
All White point values to: 127.
First, set the correct options:
In SAM, select Option numbers.
In case you have a colour analyser:
Fill in the option settings for Group 1 and Group 2
Measure, in a dark environment, with a calibrated
according to the set sticker (see also paragraph 6.4
contactless colour analyser (Minolta CA-210 or Minolta
Option Settings).
CS-200) in the centre of the screen and note the x, y value.
Press OK on the remote control before the cursor is
Change the pattern to 90% white screen. If a Quantum
moved to the left.
Data generator is used, select the GreyAll test pattern at
In submenu Option numbers select Store and press
level = 230.
OK on the RC.
Adjust the correct x, y coordinates (while holding one of the
OR:
White point registers R, G or B on 127) by means of
In main menu, select Store again and press OK on
decreasing the value of one or two other white points to the
the RC.
correct x, y coordinates (see Table 6-1 White D alignment
Switch the set to Stand-by.
values - LED - Minolta CA-210, or 6-2 White D alignment
Warming up (>15 minutes).
values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy:
0.002.
6.2 Hardware Alignments Repeat this step for the other colour temperatures that
Not applicable. need to be aligned.
When finished press OK on the RC and then press STORE
6.3 Software Alignments (in the SAM root menu) to store the aligned values to the
Put the set in SAM mode (see Chapter 5. Service Modes, Error NVM.
Codes, and Fault Finding). The SAM menu will now appear on Restore the initial picture settings after the alignments.
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below. Table 6-1 White D alignment values - LED - Minolta CA-210
The following items can be aligned:
White point Value Cool (9420K) Normal (8120K) Warm (6080K)
Ambilight. x 0.282 0.292 0.320
y 0.298 0.311 0.345
To store the data:
Press OK on the RC before the cursor is moved to the
left Table 6-2 White D alignment values - LED - Minolta CS-200
In main menu select Store and press OK on the RC
Switch the set to stand-by mode. Value Cool (11000K) Normal (9000K) Warm (6500K)
x 0.276 0.287 0.313
For the next alignments, supply the following test signals via a y 0.282 0.296 0.329
video generator to the RF input:
EU/AP-PAL models: a PAL B/G TV-signal with a signal
If you do not have a colour analyser, you can use the default
strength of at least 1 mV and a frequency of 475.25 MHz
values. This is the next best solution. The default values are
US/AP-NTSC models: an NTSC M/N TV-signal with a average values coming from production.
signal strength of at least 1 mV and a frequency of 61.25
Select a COLOUR TEMPERATURE (e.g. COOL,
MHz (channel 3).
NORMAL, or WARM).
Set the RED, GREEN and BLUE default values according
to the values in Table 6-3 to Table 6-10.
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 EN 40 6. Q552.4E LA Alignments

When finished press OK on the RC, then press STORE (in 6.4 Option Settings
the SAM root menu) to store the aligned values to the NVM.
Restore the initial picture settings after the alignments. 6.4.1 Introduction

Table 6-3 White tone default setting 32" (4000 series) The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
White Tone e.g. 32PFL4xx7x/xx digital diagnosis possible, the microprocessor has to know
Colour Temperature R G B which ICs to address. The presence / absence of these
Normal 126 115 122 PNX51XX ICs (back-end advanced video picture improvement
Cool 112 110 127 IC which offers motion estimation and compensation features
Warm 127 104 81 (commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes.
Table 6-4 White tone default setting 37" (4000 series)
Notes:
After changing the option(s), save them by pressing the OK
White Tone e.g. 37PFL4xx7x/xx
button on the RC before the cursor is moved to the left,
Colour Temperature R G B
select STORE in the SAM root menu and press OK on the
Normal 126 105 127
RC.
Cool 105 94 127
The new option setting is only active after the TV is
Warm 127 94 85
switched off / stand-by and on again with the mains
switch (the NVM is then read again).
Table 6-5 White tone default setting 42" (4000 series)
6.4.2 Dealer Options
White Tone e.g. 42PFL4xx7/xx
Colour Temperature R G B For dealer options, in SAM select Dealer options.
Normal 127 111 114 See Table 6-12 SAM mode overview.
Cool 124 115 127
Warm 127 99 76
6.4.3 (Service) Options

Table 6-6 White tone default setting 47" (4000 series) From 2011 onwards, it is not longer possible to change
individual option settings in SAM. Options can only be changed
White Tone e.g. 47PFL4xx7/xx all at once by using the option codes as described in section
Colour Temperature R G B 6.4.4.
Normal 127 112 118
Cool 115 119 127 6.4.4 Opt. No. (Option numbers)
Warm 127 100 76

Select this sub menu to set all options at once (expressed in

Table 6-7 White tone default setting 32" (5000 series) two long strings of numbers).
An option number (or option byte) represents a number of
White Tone e.g. 32PFL5xx7/xx different options. When you change these numbers directly,
Colour Temperature R G B you can set all options very quickly. All options are controlled
Normal 127 96 84 via eight option numbers.
Cool 127 99 102 When the NVM is replaced, all options will require resetting. To
Warm 127 83 44 be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
Table 6-8 White tone default setting 40" (5000 series)
Example: The options sticker gives the following option
numbers:
White Tone e.g. 40PFL5xx7/xx 32776 00001 15421 02235
Colour Temperature R G B 43847 36615 33024 00012
Normal 115 121 127 The first line (group 1) indicates hardware options 1 to 4, the
Cool 97 108 127 second line (group 2) indicate software options 5 to 8.
Warm 127 117 92 Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
Table 6-9 White tone default setting 46" (5000 series) When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
White Tone e.g. 46PFL5xx7.xx
Colour Temperature R G B Diversity
Normal 127 97 92 Not all sets with the same Commercial Type Number (CTN)
Cool 127 101 109 necessarily have the same option code!
Warm 127 84 53 Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Table 6-10 White tone default setting 55" (5000 series)
Refer to Chapter 2. Technical Specs, Diversity, and
Connections.
White Tone e.g. 55PFL5xx7/xx
Colour Temperature R G B
6.4.5 Option Code Overview
Normal 127 98 85
Cool 127 104 105
Warm 127 83 45
Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!

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 Alignments Q552.4E LA 6. EN 41

6.4.6 Option Bit Overview Caution

When manipulating option codes, know what youre doing.
For test purposes, please find below an overview of the Option Wrong option codes could damage the set.
Codes on bit level. With a bin/dec converter, you can calculate Prescribed option codes below are an example, not valid for all
the Option Code. sets and are subject to modification.
The correct option codes are always present on a sticker inside
the set!

Table 6-11 Option codes at bit level (Option 1 - Option 8)

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Option 1 (prescribed value 327761))
Bit 15 (MSB) 32768 Video Store Streaming 11) 0 = OFF
1 = ON
Bit 14 16384 Multi App 001) 00 = none
Bit 13 8192 01 = multi app
10 = AVPIP + multi app
11 = future use
Bit 12 4096 Perfect Pixel 001) 00 = Pixel Plus HD
Bit 11 2048 01 = Pixel Precise HD
10 = Perfect Pixel HD
11 = future use
Bit 10 1024 Tuner Type 0001) 000 = TH2603 (Europe/CH)
Bit 9 512 001 = FA2307 (Brazil)
010 = VA1E1ED2411
Bit 8 256
011 = SUT-RE2144
100 = future use
101 = future use
110 = future use
111 = future use
Bit 7 128 PQ Profiles 0001) 000 = OFF
Bit 6 64 001 = ON
010 = future use
Bit 5 32
011 = future use
100 = future use
101 = future use
110 = future use
111 = future use
Bit 4 16 DNM 011) 00 = Perfect Natural Motion
Bit 3 8 01 = HD Natural Motion
10 = future use
11 = future use
Bit 2 4 MOP AL 01) 0 = OFF
1 = ON
Bit 1 2 AL Optical Syst 001) 00 = 140 nit
Bit 0 (LSB) 1 01 = 200 nit
10 = 110 nit
11 = future use
Option 2 (prescribed value 000011))
Bit 15 (MSB) 32768 AL Shop Mode 01) 0 = boost mode in shop is OFF
1 = boost mode in shop is ON
Bit 14 16384 AL settings storage location 01) 0 = stored in AL modules
1 = stored in SSB
Bit 13 8192 Wall Adaptive AL 01) 0 = OFF
1 = ON
Bit 12 4096 Sunset 01) 0 = OFF
1 = ON
Bit 11 2048 Ambient Light 00001) 0000 = none
Bit 10 1024 0001 = 2-sided (3/3)
0010 = 2-sided (4/4)
Bit 9 512
0011 = 2-sided (5/5)
Bit 8 256 0100 = 2-sided (6/6)
0101 = 2-sided (7/7)
0110 = 3-sided (4/7/4)
0111 = 3-sided (5/5)(9/9)(5/5)
1000 = 3-sided (3/6/3)
1001 = 3-sided (5/5)(10/10)(5/5)
1010 = 2-sided (8/8)
1011 = 3-sided (5/12/15)
1100 = 2-sided (1/1)
1101 = 2-sided (2/2)
1110 = 3-side (4/10/4)
1111 = 3-side (6/6)(11/11)(6/6)
Bit 7 128 FPGA3Dact/1Ddimm 01) 0 = OFF
1 = ON
Bit 6 64 AL Select 01) 0 = AL2k10
1 = AL2k11
Bit 5 32 3D Passive 01) 0 = 2D
1 = 3D passive
Bit 4 16 Smart Bit Enhancement (SBE) 01) 0 = off
1 = on (200 Hz board present)
Bit 3 8 Super Resolution 01) 0 = Super Resolution SD
1 = Super Resolution HD

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 EN 42 6. Q552.4E LA Alignments

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Bit 2 4 Light Sensor Type 001) 00 = future use
Bit 1 2 01 = future use
10 = future use
11 = future use
Bit 0 (LSB) 1 Light Sensor 11) 0 = OFF
1 = ON
Option 3 (prescribed value 154211))
Bit 15 (MSB) 32768 Side IO 01) 0 = not present
1 = present
Bit 14 16384 AV3 0111) 000 = none
Bit 13 8192 001 = CVBS
010 = YPbPr
Bit 12 4096
011 = YPbPr/LR:Europe
100 = YPbPr/HV/LR
101 = CVBS/LR:Brazil
110 = CVBS/Yc/LR
111 = YPbPr/CVBS/LR
Bit 11 2048 AV2 111) 00 = Scart/CVBS/RGB/LR
Bit 10 1024 01 = CVBS
10 = YPbPr/LR
11 = none:Europe and Brazil
Bit 9 512 AV1 001) 00 = Scart/CVBS/RGB/LR:Europe
Bit 8 256 01 = CVBS/YC/YPbPr/HV/LR
10 = CVBS/YC/YPbPr/LR
11 = YPbPr/LR:Brazil
Bit 7 128 3D Prepared 01) 0 = not prepared
1 = prepared
Bit 6 64 Sound in Stand 01) 0 = OFF
1 = ON
1)
Bit 5 32 Headphone 1 0 = OFF
1 = ON
Bit 4 16 Seamless System 11) 0 = OFF
1 = ON
Bit 3 8 ViewPort 21_9/PQL 11) 0 = OFF
1 = ON
Bit 2 4 HDMI Side 11) 0 = OFF
1 = ON (HDMI 4)
Bit 1 2 HDMI 3 01) 0 = OFF
1 = ON
Bit 0 (LSB) 1 HDMI 2 11) 0 = OFF
1 = ON
Option 4 (prescribed value 022351))
Bit 15 (MSB) 32768 Cabinet 000011) Cabinet type
Bit 14 16384 (no detailed info available)

Bit 13 8192
Bit 12 4096
Bit 11 2048
Bit 10 1024 Region 0001) 000 = Europe (/02, /05 & /12)
Bit 9 512 001 = AP PAL multi
010 = AP NTSC
Bit 8 256
011 = future use
100 = Latam (/78 & /77)
101 = Australia
110 = China (/93)
111 = future use
Bit 7 128 Display MSB 11) 0 = display option =< 255
1 = display option > 255
Bit 6 64 S Video 01) 0 = OFF
1 = ON
Bit 5 32 Video Store USB 11) 0 = OFF
1 = ON
Bit 4 16 Internet software Upgrade 11) 0 = OFF
1 = ON (automatic software upgradable via internet)
Bit 3 8 Online Service 11) 0 = OFF
1 = ON (connection to internet provider Philips)
Bit 2 4 WiFi 01) 0 = OFF
1 = ON (wireless connection to ethernet; no link with Ethernet option bit 0)
Bit 1 2 DLNA 11) 0 = OFF
1 = PC link
Bit 0 (LSB) 1 Ethernet 11) 0 = OFF
1 = Ethernet vonnector and HW present
Option 5 (prescribed value 438471))
Bit 15 (MSB) 32768 8 Days EPG 11) 0 = OFF
1 = ON (country dependent)
Bit 14 16384 DVBC Installation 011) 00 = OFF
Bit 13 8192 01 = Country dependent
10 = ON
11 = future use
Bit 12 4096 DVBT Installation 011) 00 = OFF
Bit 11 2048 01 = Country dependent
10 = ON
11 = future use

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 Alignments Q552.4E LA 6. EN 43

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Bit 10 1024 DVB-S 01) 0 = OFF
1 = ON (ATSC/DVB should be ON)
Bit 9 512 DVB-C 11) 0 = OFF
1 = ON (ATSC/DVB should be ON)
Bit 8 256 DVB 11) 0 = analogue only
1 = DVBT (and C/S depending DVBC/S option)
Bit 7 128 Display Type 010001111) Display Type (ex.: 327)
Bit 6 64
Bit 5 32
Bit 4 16
Bit 3 8
Bit 2 4
Bit 1 2
Bit 0 (LSB) 1
Option 6 (prescribed value 366151))
Bit 15 (MSB) 32768 E-sticker 11) 0 = OFF
1 = ON
Bit 14 16384 Hotel Mode 001) 00 = OFF
Bit 13 8192 01 = 1V1
10 = 1V2
11 = future use
Bit 12 4096 Virgin 01) 0 = ON
1 = OFF
Bit 11 2048 empty - -
Bit 10 1024 Auto Store Mode 111) 00 = none
Bit 9 512 01 = PDC_VPS
10 = TXT page
11 = PDC_VPS_TXT
Bit 8 256 Temp sensor on SSB 11) 0 = OFF
1 = ON
Bit 7 128 Ginga 001) 00 = OFF
Bit 6 64 01 = Country dependent
10 = ON
11 = future use
Bit 5 32 MHP 001) 00 = OFF
Bit 4 16 01 = Country dependent
10 = ON
11 = future use
Bit 3 8 Over the Air Download 011) 00 = OFF
Bit 2 4 01 = Country dependent
10 = ON
11 = future use
Bit 1 2 DVBC light 11) 0 = OFF
1 = ON (when DVBC Installation is OFF or when ON but selected country is OFF, this option is used)
Bit 0 (LSB) 1 DVBT light 11) 0 = OFF
1 = ON (when DVBT Installation is OFF or when ON but selected country is OFF, this option is used)
Option 7 (prescribed value 330241))
Bit 15 (MSB) 32768 Visual Identity 11) 0 = User Interface 2k10
1 = User Interface 2k11 (always ON)
Bit 14 16384 Red LED Config LUT 0001) 000 = LUT 0
Bit 13 8192 001 = LUT 1
010 = future use
Bit 12 4096
011 = future use
100 = future use
101 = future use
110 = future use
111 = future use
Bit 11 2048 Board Identifier 001) not used, should always be 00
Bit 10 1024
Bit 9 512 Manet 01) 0 = all sets except Manet
1= Manet
Bit 8 256 Auto Power Down 11) 0 = OFF
1 = ON
Bit 7 128 Light Guide 01) 0 = OFF
1 = ON
Bit 6 64 E-box 01) 0 = integrated set
1 = e-box/monitor
Bit 5 32 Temp LUT 0001) 000 = future use
Bit 4 16 001 = future use
010 = future use
Bit 3 8
011 = future use
100 = future use
101 = future use
110 = future use
111 = future use
Bit 2 4 Temp Sensor 001) 00 = no temp sensor
Bit 1 2 01 = temp sensor in display
10 = temp sensor on additional board
11 = temp sensor in AL module
Bit 0 (LSB) 1 FAN 01) 0 = no fan
1 = fan(s) present)
Option 8 (prescribed value 000121))
Bit 15 (MSB) 32768 MSB Cabinet 01) Cabinet

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 EN 44 6. Q552.4E LA Alignments

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Bit 14 16384 3D goggles 01) 0 = 2K10 Xpand
1 = 2k11 Real D
Bit 13 8192 empty - -
Bit 12 4096 3D Overdrive LUT 0001) 000 = no overdrive LUT
Bit 11 2048 001 = LUT1
010 = LUT2
Bit 10 1024
011 = LUT3
100 = LUT4
101 = LUT5
110 = LUT6
111 = LUT7
Bit 9 512 ISF 01) 0 = OFF
1 = ON
Bit 8 256 DVB-S channel decoder + new LNB 01) 0 = OFF
1 = channel decoder STV 0903BAC + LNBH25
Bit 7 128 MSB Light Sensor type 01) -
Bit 6 64 DVB-T2 Sony channel decoder 11) 0 = OFF
1 = channel decoder T2: CXD2834ER
Bit 5 32 FPGA PQ 01) 0 = not present
1 = present
Bit 4 16 2player gaming 11) 0 = OFF
1 = ON
Bit 3 8 WM DRM10 11) 0 = OFF
1 = ON
Bit 2 4 HBBTV 11) 0 = OFF
1 = ON
Bit 1 2 DVB-T2 Installation 01) 0 = no installation
1 = country depending
Bit 0 (LSB) 1 DVB-T2 11) 0 = OFF
1 = channel decoder 2

Note 6.5.1 SSB identification

1). Example
Whenever ordering a new SSB, it should be noted that the
6.5 Reset of Repaired SSB correct ordering number (12nc) of a SSB is located on a sticker
A very important issue towards a repaired SSB from a Service on the SSB. The format is <12nc SSB><serial number>. The
repair shop (SSB repair on component level) implies the reset ordering number of a Service SSB is the same as the ordering
of the NVM on the SSB. number of an initial factory SSB.
A repaired SSB in Service should get the service Set type
00PF0000000000 and Production code 00000000000000.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool or use the NVM editor and Dealer options
items in SAM (do not forget to store).

After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this, you can use the NVM editor in SAM. This action also
ensures the correct functioning of the Net TV feature and
access to the Net TV portals. The loading of the CTN and
production code can also be done via ComPair (Model number
programming).

After a SSB repair, the original channel map can be restored,

provided that the original channel map was stored on a USB
stick before repair was commenced and that basic functionality 18310_221_090318.eps
of the TV, needed for this procedure, was not hampered as a 090319
result of the defect. The procedure of channel map cloning is
clearly described in the (electronic) user manual. Figure 6-1 SSB identification

In case of a display replacement, reset the Operation hours

display to 0, or to the operation hours of the replacement
display.

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 Alignments Q552.4E LA 6. EN 45

6.6 Total Overview SAM modes

Table 6-12 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Hardware Info A. software version e.g. Q5551_0.9.1.0 Display TV & Stand-by software version and CTN serial
B. Stand-by processor version e.g. STDBY_83.84.0.0 number

C. Production code e.g. see type plate

Operation hours Displays the accumulated total of operation hours.TV
switched on/off & every 0.5 hours is increase one
Errors Displayed the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be selected
Warn
Cool
White point red LCD White Point Alignment. For values,
White point green see Table 6-3 White tone default setting 32" (4000 series) to
6-10 White tone default setting 55" (5000 series)
White point blue
Ambilight Select module
Brightness
Select matrix
Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not start up
(once) with a language selection menu after the mains switch
is turned on for the first time (virgin mode)
E-sticker Off/On Select E-sticker On/Off (USPs on-screen)
Auto store mode None
PDC/VPS
TXT page
PDC/VPS/TXT
Miscellaneous Hotel mode Off Hotel mode is Off
Option numbers Group 1 e.g. The first line (group 1) indicates hardware options 1 to 4
00008.00001.15421.02239
Group 2 e.g. The second line (group 2) indicates software options 5 to 8
44816.34311.33024.00000
Store Store after changing
Initialise NVM N.A.
Store Select Store in the SAM root menu after making any changes
Operation hours display 0003 In case the display must be swapped for repair, you can reset
the Display operation hours to 0. So, this one does keeps
up the lifetime of the display itself (mainly to compensate the
degeneration behaviour)
Software maintenance Software events Display Display information is for development purposes
Clear
Test reboot
Test cold reboot
Test application crash
Hardware events Display Display information is for development purposes
Clear
Test setting Digital info Current frequency: 538
QAM modulation: 64-qam Display information is for development purposes
Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency 000 Install start frequency from 0 MHz
Install end frequency 999 Install end frequency as 999 MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before installation
Digital + Analogue

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 EN 46 6. Q552.4E LA Alignments

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Development file versions Development 1 file version Display parameters Display information is for development purposes
DISPT5.0.9.29
Acoustics parameters ACSTS
5.0.6.20
PQ - TV550 1.0.27.22
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM
5.0.5.2
Development 2 file version 12NC one zip software Display information is for development purposes
Initial main software
NVM version Q55x1_0.4.5.0
Flash units software
Temp com file version none
Upload to USB Channel list To upload several settings from the TV to an USB stick
Personal settings
Option codes
Alignments
Identification data
History list
All (options included)
Download from USB Channel list To download several settings from the USB stick to the TV
Personal settings
Option codes
Alignments
Identification data
All (options included)
NVM editor Type number see type plate NVM editor; re key-in type number and production code after
AG code see type plate SSB replacement

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 Circuit Descriptions Q552.4E LA 7. EN 47

7. Circuit Descriptions
Index of this chapter: For Service, the platform is supporting Remote Diagnostics (IP
7.1 Introduction Remote Diagnostics and Repair). Detailed information will
7.2 Power Supply follow via the regular communication channels.
7.3 Video and Audio Processing - PNX855xx
The Q552.4E LA chassis comes with the following stylings:
Notes: 4000 (series xxPFL4xxx),
Only new circuits (circuits that are not published recently) 5000 (series xxPFL5xxx).
are described.
Figures can deviate slightly from the actual situation, due 7.1.1 Implementation
to different set executions.
For a good understanding of the following circuit
Key components of this chassis are:
descriptions, please use the wiring-, block- (see chapter PNX855xx System-On-Chip (SOC) TV Processor
9. Block Diagrams) and circuit diagrams (see chapter
SUT-RE214Z Hybrid Tuner (DVB-T/C, analogue)
10. Circuit Diagrams and PWB Layouts).Where necessary,
STV6110A DVB-S Satellite Tuner
you will find a separate drawing for clarification. SII9x87 HDMI Switch
TAS5731 Class D Power Amplifier
7.1 Introduction LAN8710 Dual Port Gigabit Ethernet media access
The Q552.4E LA is part of the TV550 R4 2012 platform. It controller.
uses the (same) PNX855xx chipset as its predecessor
Q552.2E LA, part of the TV550 2011 platform.
7.1.2 TV550 Architecture Overview
The major deltas versus the Q552.2 are:
integrated Wifi in 5000 & 5500 series
implementation of active 3D for 5500 series For details about the chassis block diagrams refer to chapter 9.
Block Diagrams. An overview of the TV550 R4 2012
2 to 3D conversion
architecture can be found in Figure 7-1 and Figure 7-2.
TV video call feature.

2 LVDS for 4000s

4 LVDS for 5000 s/5500s Cell
FHD@120
FLASH
512 MB

DDR 512 MB
32

4 1 Gb ( 8) PWM
BL Backlight
PNX85500 BOOST 3D goggle drive
Ambilight CPLD
NR 8x PWM
Hybrid DEI Not Applicable FPGA
Tuner PQ Enhancement Spartan 6
for 5000 series
DVB FRC LX4
T2 3D: Active 3D-IR
PWM: temp. ctrl Glass
DVB-S2 DVB
Tuner S2 SPI
AL Ambilight CPLD AL mods.
2
IS
CLASS-D
HDMI
Audio
9287

ETH USB
Temp
Series
Class D Amplifier
supply voltage
PHY HUB I2C/Analog
Sensor 40x7 24 V
Shop 43x7 12 V
50x7 12 V
CI+ Temp
Sensor
3D active

19220_017_120224.eps
120224

Figure 7-1 Architecture of TV550 R4 platform (4000-5000 range)

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 EN 48 7. Q552.4E LA Circuit Descriptions

4 LVDS 4 LVDS Cell

Entry 2D3D FHD@120
FLASH
512MB Backlight
3D goggle drive

DDR 512MB FPGA

32

4 1Gb ( 8) PWM Spartan 6

BL BOOST LX25T
PNX85500
Only required for
NR Active 3D 8x PWM
Hybrid DEI
Tuner PQ Enhancement
DVB FRC
T2 3D: Active 3D-IR
PWM: temp. ctrl Glass
DVB-S2 DVB
Tuner S2 SPI Ambilight CPLD
AL mods.

HDMI
9287
Audio
I2S
CLASS-D
ETH
PHY
USB
HUB I2C/Analog
Temp Series
Class D Amplifier
supply voltage
Sensor
55x7 12v
Shop
CI+ Temp
Sensor
3D active

19220_022_120227.eps
120227

Figure 7-2 Architecture of TV550 R4 platform (5500 range; supporting active 3D)

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 Circuit Descriptions Q552.4E LA 7. EN 49

7.1.3 SSB Cell Layout

19220_023_120227.eps
120227

Figure 7-3 SSB layout cells (top view; 4000-5000 range)

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 EN 50 7. Q552.4E LA Circuit Descriptions

LX25 2D-3D
Processing
LX25

19220_024_120227.eps
120227

Figure 7-4 SSB layout cells (5500 range; supporting active 3D)

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 Circuit Descriptions Q552.4E LA 7. EN 51

7.2 Power Supply

7.2.1 Power Supply Unit 4xx7 series

No pinning table is available.

Refer to section 10.1 and 10.2 for schematics.

7.2.2 Power Supply Unit 5xx7 series

Table 7-1 Connector overview 5xx7 series, all screen sizes

Connector
no. 1308 1316 1M95 1M99
Description Mains to display to SSB to SSB
Pin CN1 CN2 CN4 CN5
1 N A1 +3V3SB GND_AL
2 L n.c. Standby 12V3
3 n.a. n.c. GND1 GND_AL
4 n.a. C1 GND1 12V3
5 n.a. C2 +12V3 GND1
6 n.a. C3 +12V3 +12V3
7 n.a. C4 +Vsnd GND1
8 n.a. n.a. +Vsnd +12V3
9 n.a. n.a. GND_SND n.a.
10 n.a. n.a. GND_SND n.a.
11 n.a. n.a. BL_ON n.a.
12 n.a. n.a. BL_DIM n.a.
13 n.a. n.a. BL_I_CTRL n.a.
14 n.a. n.a. POK n.a.

No schematics are available.

7.3 Video and Audio Processing - PNX855xx

The PNX855xx is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:

Multi-standard digital video decoder (MPEG-2, H.264,

MPEG-4)
Integrated DVB-T/DVB-C channel decoder
Integrated CI+
Integrated motion accurate picture processing (MAPP2)
High definition ME/MC
2D LED backlight dimming option
Embedded HDMI HDCP keys
Extended colour gamut and colour booster
Integrated USB2.0 host controller
Improved MPEG artefact reduction compared with
PNX8543
Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions,

such as DVB-T channel decoding, MPEG-2/H.264 decode,
analog video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
and vivid colour management. High flat panel screen
resolutions and refresh rates are supported with formats
including 1366 768 @ 100Hz/120Hz and 1920 1080 @
100Hz/120Hz. The combination of Ethernet, CI+ and H.264
supports new TV experiences with IPTV and VOD. On top of
that, optional support is available for 2D dimming in
combination with LED backlights for optimum contrast and
power savings up to 50%.

For a functional diagram of the PNX855xx, refer

to Figure 7-5.

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 EN 52 7. Q552.4E LA Circuit Descriptions

PNX85500x
MEMORY
CONTROLLER

TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)

DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT

Low-IF DIGITAL IF MPEG/H.264

VIDEO Motion-accurate
DECODER pixel processing

SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION

AUDIO DACS analog audio

SPDIF AUDIO IN
AUDIO DSP
I 2S
AUDIO OUT
HDMI SPDIF
HDMI 450 MHz
RECEIVER AV-DSP

SYSTEM 560 MHz DRAWING

CONTROLLER MIPS32 ENGINE
(8051) 24KEf CPU

DMA BLOCK

I2C PWM GPIO IR ADC SPI UART I 2C GPIO Flash USB 2.0 SD Ethernet
x8 Memory MAC
Card

18770_241_100201.eps
111103

Figure 7-5 PNX855xx functional diagram

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 IC Data Sheets Q552.4E LA 8. EN 53

8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as black boxes in the
electrical diagrams (with the exception of memory and logic
ICs).

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 EN 54 8. Q552.4E LA IC Data Sheets

8.1 Diagram 10-3-3 DC/DC B02A, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1 1 28 DRVH1
NC 2 27 LL1
EN1 3 26 DRVL1
VO1 4 25 PGND1
VFB1 5 24 TRIP1
NC
TPS53124

6 23 VIN
GND 7 22 VREG5
TEST1 8 21 V5FILT
NC 9 20 TEST2
VFB2 10 19 TRIP2
VO2 11 18 PGND2
EN2 12 17 DRVL2
NC 13 16 LL2
VBST2 14 15 DRVH2

18310_300_090319.eps
100416

Figure 8-1 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 55

8.2 Diagram 10-3-4 DC/DC, 1.8 V to 1.2 V conversion B02B, RT9025 (IC 7UA4-1)

Block diagram

VIN VOUT

SD
OCP

Error
EN OTP Amplifier

+
VDD POR 0.8V - Mode ADJ
PGOOD
RT9025 -
0.72V +
GND

Pinning information

PGOOD RT9025 8 GND

EN 2 7 ADJ
GND
VIN 3 9 6 VOUT
VDD 4 5 NC

SOP-8 (Exposed Pad)

19220_028_120227.eps
120227

Figure 8-2 Internal block diagram and pin configuration

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 EN 56 8. Q552.4E LA IC Data Sheets

8.3 Diagram 10-3-5 DC/DC, 12 V to 5 V/3.3 V conversion B02C, RT8293AHGSP (IC 7UD0)

Block diagram

VIN

Internal
Regulator Oscillator
Current Sense
Shutdown Slope Comp Amplifier
Comparator VA VCC + VA
Foldback
1.2V + Control -
-
0.4V + BOOT
Lockout -
Comparator UV S Q 85m
5k Comparator SW
EN - +
R Q 85m
2.7V + -
3V Current GND
Comparator
VCC

6A

SS
0.8V +
+EA
RT8293A
-

FB COMP

Pinning information

(TOP VIEW)
RT8293A 8
BOOT SS
VIN 2 7 EN
GND
SW 3 6 COMP
9
GND 4 5 FB

SOP-8 (Exposed Pad)

19220_030_120227.eps
120227

Figure 8-3 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 57

8.4 Diagram 10-3-6 DVBS supply B03A, TPS54227DDA (IC 7T00)

Block diagram

EN EN VIN
1
Logic
TPS54227
VIN
8

VREG5
VBST
Control Logic 7
Ref +

SS + PWM
1 shot
VFB SW VO
2 - 6

XCON
ON
VREG5
VREG5 Ceramic
3 Capacitor

SGND
SS SS 5
4 Softstart
GND
PGND

SGND
+ SW
OCP
- PGND

VIN

VREG5 UVLO Protection

TSD Logic
UVLO

REF Ref

Pinning information

1 EN VIN 5

2 VFB VBST 6
TPS54227
(HSOP8)

3 VREG5 Power PAD SW 7

4 SS GND 8

19220_029_120227.eps
120227

Figure 8-4 Internal block diagram and pin configuration

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 EN 58 8. Q552.4E LA IC Data Sheets

8.5 Diagram 10-3-7 Core voltage supply for DVBS demodulator B03B, LNBH25PQ (IC 7TP2)

Block diagram
ADDR SCL SDA

LNBH25
LX
DSQIN
I2C Digital core

PWM CTRL
DETIN

Isense
Tone
DSQOUT detector

DAC
Drop control
PGND
Tone ctrl
FLT
Diagnostics
Protections VUP

BPSW

Gate ctrl
Current
Linear
Limit
Regulator VOUT
selection

Voltage
reference

GND BYP VCC ISEL

Pinning information
24 23 22 21 20 19

NC DSQOUT DSQIN/
DSQIN VUP VOUT DETIN
EXTM

1 NC BPSW 18

2 FLT VCC 17

3 LX-A
LX VBYP 16

LNBH25
4 PGND GND 15

5 NC NC 14

6 ADDR NC 13

SCL SDA ISEL NC NC NC

7 8 9 10 11 12

19220_027_120227.eps
120227

Figure 8-5 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 59

8.6 Diagram 10-3-9 PNX 85500: Power B05A, PNX855xx (IC7S00)

Block diagram

PNX8550x
MEMORY
CONTROLLER

TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)

DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO analog CVBS
VIDEO ENCODER
OUTPUT analog Y/C
Low-IF
DIGITAL IF MULTI-
Direct-IF STANDARD Motion-accurate
VIDEO pixel processing
DECODER

SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION

AUDIO DACS analog audio

SPDIF AUDIO IN
AUDIO DSP
I2S
AUDIO OUT
HDMI SPDIF
HDMI 450 MHz
RECEIVER AV-DSP

SYSTEM 500 MHz DRAWING

CONTROLLER MIPS32 ENGINE
(8051) 24KEf CPU

Scatter/Gather
TS Demux

I2C PWM Px_x IR ADC SPI UART I2C GPIO Flash USB 2.0 SD Ethernet
x 10 Memory MAC
Card

Pinning information
ball A1 PNX8550xE
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

Transparent top view

18770_308_100217.eps
100217

Figure 8-6 Internal block diagram and pin configuration

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 EN 60 8. Q552.4E LA IC Data Sheets

8.7 Diagram 10-3-17 PNX 85500: Headphone B05I, TS489IST (IC 7NN1)

Block diagram

VDD 8

VDD/2
2 IN 1 VO1 1

+
3 BYPASS

TPA6111A2

6 IN 2
VO2 7
+

5 SHUTDOWN Bias 4
Control

Pinning information
D OR DGN PACKAGE
(TOP VIEW)

VO1 1 8 VDD
IN1 2 7 VO2
BYPASS 3 6 IN2
GND 4 5 SHUTDOWN

18770_309_100217.eps
110602

Figure 8-7 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 61

8.8 Diagram 10-3-23 PNX 85500: Temperature sensor B05O, LM75BDP (IC 7USA)

Block diagram
VCC

LM75B
BIAS POINTER CONFIGURATION
REFERENCE REGISTER REGISTER

TEMPERATURE
BAND GAP COUNTER
REGISTER
TEMP SENSOR 11-BIT
SIGMA-DELTA
A-to-D TOS
TIMER
CONVERTER REGISTER
OSCILLATOR
COMPARATOR/ THYST
INTERRUPT REGISTER
POWER-ON
RESET OS

LOGIC CONTROL AND INTERFACE

A2 A1 A0 SCL SDA GND

Pinning information

SDA 1 8 VCC
SCL 2 7 A0
LM75BDP
OS 3 6 A1
GND 4 5 A2

18770_300_100217.eps
100217

Figure 8-8 Pin configuration

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 EN 62 8. Q552.4E LA IC Data Sheets

8.9 Diagram 10-3-25 Class-D amplifier B06A, TAS5731PHP (IC 7D60)

Block diagram

OUT_A
2 HB
FET Out
OUT_B
Serial th
S 4 -Order
SDIN Audio Digital Audio Processor R
(DAP) Noise Shaper
Port C and PWM
OUT_C
2 HB
FET Out
OUT_D

Protection
Logic

MCLK Sample Rate

SCLK Autodetect
LRCLK and PLL TAS5731 Click and Pop
Control

Microcontroller
SDA Serial Based
Control System
SCL Control

Terminal Control

Pinning information
PGND_CD
PGND_CD
PGND_AB
PGND_AB

OUT_C
OUT_B

BST_C
BST_B
NC
NC

NC
NC

48 47 46 45 44 43 42 41 40 39 38 37
OUT_A 1 36 OUT_D
PVDD_AB 2 35 PVDD_CD
PVDD_AB 3 34 PVDD_CD
BST_A 4 33 BST_D
NC 5 32 GVDD_OUT
SSTIMER 6 31 VREG
NC 7
TAS5731 30 AGND
PBTL 8 29 GND
(Top View)
AVSS 9 28 DVSS
PLL_FLTM 10 27 DVDD
PLL_FLTP 11 26 STEST
VR_ANA 12 25 RESET
13 14 15 16 17 18 19 20 21 22 23 24
LRCLK
MCLK

PDN

SCL
VR_DIG

SDIN
SDA
OSC_RES
DVSSO
AVDD
A_SEL

SCLK

19220_086_120229.eps
120229

Figure 8-9 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 63

8.10 Diagram 10-3-26 USB hub B06B, CY7C65632-28LTXCT (IC 7FL5)

Block diagram
ADDR SCL SDA

LNBH25
LX
DSQIN
I2C Digital core

PWM CTRL
DETIN

Isense
Tone
DSQOUT detector

DAC
Drop control
PGND
Tone ctrl
FLT
Diagnostics
Protections VUP

BPSW

Gate ctrl
Current
Linear
Limit
Regulator VOUT
selection

Voltage
reference

GND BYP VCC ISEL

Pinning information
24 23 22 21 20 19

NC DSQOUT DSQIN/
DSQIN VUP VOUT DETIN
EXTM

1 NC BPSW 18

2 FLT VCC 17

3 LX-A
LX VBYP 16

LNBH25
4 PGND GND 15

5 NC NC 14

6 ADDR NC 13

SCL SDA ISEL NC NC NC

7 8 9 10 11 12

19220_027_120227.eps
120227

Figure 8-10 Internal block diagram and pin configuration

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 EN 64 8. Q552.4E LA IC Data Sheets

8.11 Diagram 10-3-27 Ethernet & service B06C, LAN8710A-EZKH (IC 7N10)

Block diagram
MODE0 HP Auto-MDIX
MODE1 Auto- 10M Tx 10M
MODE Control
MODE2 Negotiation Logic Transmitter TXP / TXN
Reset Transmit Section
nRST Control RXP / RXN
Management 100M Tx 100M
RMIISEL SMI Logic Transmitter
Control
MDIX
Control
TXD[0:3] XTAL1/CLKIN
TXEN PLL
100M Rx DSP System: Analog-to-
TXER XTAL2
TXCLK Logic Clock Digital
Data Recovery
Interrupt
Equalizer nINT
Generator
RMII / MII Logic

RXD[0:3]
RXDV 100M PLL
RXER Receive Section
RXCLK LED1
LED Circuitry
LED2
10M Rx Squelch &
CRS Logic Filters
COL/CRS_DV
Central
RBIAS
MDC 10M PLL Bias
MDIO
PHY
Address PHYAD[0:2]
Latches

Pinning information
VDD1A
RBIAS

RXDV

TXD3
RXN
RXP

TXN
TXP
32

31

30

29

28

27

26

25

VDD2A 1 24 TXD2

LED2/nINTSEL 2 23 TXD1

LED1/REGOFF 3 22 TXD0
SMSC
XTAL2 4 LAN8710/LAN8710i 21 TXEN

XTAL1/CLKIN 5 32 PIN QFN 20 TXCLK

VDDCR 6
(Top View) 19 nRST

RXCLK/PHYAD1 7 18 nINT/TXER/TXD4
VSS
RXD3/PHYAD2 8 17 MDC
10

11

12

13

14

15

16
9

RXD0/MDE0
RXD2/RMIISEL

RXD1/MODE1

CRS

COL/CRS_DV/MODE2

MDIO
VDDIO

RXER/RXD4/PHYAD0

18770_302_100217.eps
100217

Figure 8-11 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 65

8.12 Diagram 10-3-28 HDMI B06D, SiI9x87B (IC 7NC1)

Block diagram

Pinning information

18770_303_100217.eps
100217

Figure 8-12 Internal block diagram and pin configuration

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 EN 66 8. Q552.4E LA IC Data Sheets

8.13 Diagram 10-3-29 FPGA, power & control B07A, LD1117DT12 (IC 7J20)

Block diagram
LD1117DT

Pinning information

DPAK

F_15710_166.eps
100402

Figure 8-13 Internal block diagram and pin configuration

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 IC Data Sheets Q552.4E LA 8. EN 67

8.14 Diagram 10-3-31 Tuner, channel decoder B08A, CXD2834ER (IC 7KC0)

Block diagram
MPEG
TUNER Decoder
TAINP (IF)
IF+ 12-bit
TAINM (IF) ADC
IF-

DVB-T2 LDPC/BCH Stream

RFAIN 10-bit TSCLK
(RFAGC-MON) Demodulator Decoder Processor TSCLK
ADC
TSVALID
TSVALID
TSIF
GPIO1 (PWM) TSSYNC
(RFAGC) GPIO TSSYNC
DVB-T
TSDATA7-0
Demodulator TSDATA7-0
TS
RS Decoder
TIFAGC Smoothing
IFAGC AGC DVB-C
Demodulator

TTUSCL SCL
SCL SCL
TTUSDA I2C IF SDA
SDA SDA

41MHz or OSC
20.5 MHz PLL

XTALI
XTALO

Pinning information

19220_025_120227.eps
120227

Figure 8-14 Internal block diagram and pin configuration

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 EN 68 8. Q552.4E LA IC Data Sheets

8.15 Diagram 10-3-32 DVBS, FE B08B, STV6110AT (IC 7RA0)

Block diagram
STV6110AT RF_OUT

IP
RF_IN
IN
QP
AGC
QN

PLL, dividers DC offset compensation

SCL
XTAL_IN
2
XTAL_INN Amplifier I C bus interface

XTAL_OUT SDA

18770_304_100217.eps
110601

Figure 8-15 Internal block diagram and pin configuration

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 Block Diagrams Q552.4E LA 9. EN 69

9. Block Diagrams
9.1 Wiring diagram 4000 series 32"
WIRING DIAGRAM 32" 4000 Series

DISPLAY
PANEL

1316

1M95
14P
1M95
WOOFER 14P

1D02
(SP02)

3P
MAIN POWER SUPPLY
(1053)

1G51
51P
SSB
B (1150)

E1M95

1D01
4P
E1G51

1C20
11P
MOD CONTROL BOARD (Q1057)

TO DISPLAY

INLET

TWEETER TWEETER
(SP01) (SP01)

SENSOR BOARD (Q1056)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G51 (B09A) 4. GND
8. +12VAUDIO 1. +VDISP 5. KEYBOARD
9. GND 2. +VDISP 6. +3V3-STANDBY
10. GND 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A)
11. BL-ON-1 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+
12. BL-DIM-1 | 9. SCL-SET 2. LEFT-- 2. GND
13. BL-I-CTRL-1 | 10. GND 3. RIGHT-+ 3. RIGHT-- 19220_018_120224.eps
14. POWER-OK-1 51. 11. SDA-SET 4. RIGHT-- 120224

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 Block Diagrams Q552.4E LA 9. EN 70

9.2 Wiring diagram 4000 series 37"

WIRING DIAGRAM 37" 4000 Series

E1M95

DISPLAY
PANEL

1316
WOOFER
(SP02)

1M95
14P
1M95
14P

1D02
3P
MAIN POWER SUPPLY
(1053)

1G51
51P
SSB
B (1150)
MOD CONTROL BOARD (Q1057)

1D01
4P
E1G51

1C20
11P
TO DISPLAY

INLET

TWEETER TWEETER
(SP01) (SP01)

SENSOR BOARD (Q1056)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G51 (B09A) 4. GND
8. +12VAUDIO 1. +VDISP 5. KEYBOARD
9. GND 2. +VDISP 6. +3V3-STANDBY
10. GND 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A)
11. BL-ON-1 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+
12. BL-DIM-1 | 9. SCL-SET 2. LEFT-- 2. GND
13. BL-I-CTRL-1 | 10. GND 3. RIGHT-+ 3. RIGHT-- 19220_019_120224.eps
14. POWER-OK-1 51. 11. SDA-SET 4. RIGHT-- 120224

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 Block Diagrams Q552.4E LA 9. EN 71

9.3 Wiring diagram 4000 series 42"

WIRING DIAGRAM 42" 4000 series

DISPLAY
PANEL

1316

1M95
WOOFER 14P

1D02
14P
1M95

3P
(SP02) E1M95
MAIN POWER SUPPLY
(1053)

1G51
51P
SSB
B (1150)

INLET

1D01
4P
MOD CONTROL BOARD

E1G51

1C20
11P
TO DISPLAY
(Q1057)

TWEETER TWEETER
(SP01) (SP01)
SENSOR BOARD (1122)
SENSOR BOARD (Q1056)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G51 (B09A) 4. GND
8. +12VAUDIO 1. +VDISP 5. KEYBOARD
9. GND 2. +VDISP 6. +3V3-STANDBY
10. GND 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A)
11. BL-ON-1 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+
12. BL-DIM-1 | 9. SCL-SET 2. LEFT-- 2. GND
13. BL-I-CTRL-1 | 10. GND 3. RIGHT-+ 3. RIGHT-- 19220_020_120224.eps
14. POWER-OK-1 51. 11. SDA-SET 4. RIGHT-- 120224

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 Block Diagrams Q552.4E LA 9. EN 72

9.4 Wiring diagram 4000 series 47"

WIRING DIAGRAM 47" 4000 series

DISPLAY
PANEL

1M95
WOOFER 14P

1D02
14P
1M95

3P
(SP02) E1M95
MAIN POWER SUPPLY
(1053)

1G51
51P
SSB
B (1150)

INLET

1D01
4P
MOD CONTROL BOARD

E1G51

1C20
11P
TO DISPLAY
(Q1057)

TWEETER TWEETER
(SP01) (SP01)
SENSOR BOARD (1122)
SENSOR BOARD (Q1056)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G51 (B09A) 4. GND
8. +12VAUDIO 1. +VDISP 5. KEYBOARD
9. GND 2. +VDISP 6. +3V3-STANDBY
10. GND 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A)
11. BL-ON-1 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+
12. BL-DIM-1 | 9. SCL-SET 2. LEFT-- 2. GND
13. BL-I-CTRL-1 | 10. GND 3. RIGHT-+ 3. RIGHT-- 19220_021_120224.eps
14. POWER-OK-1 51. 11. SDA-SET 4. RIGHT-- 120224

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 Block Diagrams Q552.4E LA 9. EN 73

9.5 Wiring diagram 5000 & 5500 series 32"

WIRING DIAGRAM 32" 5000 and 5500 Series

8M95
DISPLAY
PANEL

1M95
14P

1M95
1316

WOOFER
14P
(5214)

1D02
3P
MAIN POWER SUPPLY
(1005)

1G51
51P
SSB
B (1150)

1G50
41P
2p3 8G50
1308

1C30 1D01
4P
4P
8G51

8308

1C20
11P
(1114)

TO DISPLAY TO DISPLAY
INLET
MOD CONTROL BOARD

8C20
TWEETER TWEETER
(5216) (5216)

8F24
WIFI (1115)
SENSOR BOARD (1122)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G50 (B09A) 1G51 (B09A) 4. GND
8. +12VAUDIO 1. GND 1. +VDISP 5. KEYBOARD
9. GND 2. GND 2. +VDISP 6. +3V3-STANDBY
10. GND | 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A) 1C30 (B06B)
11. BL-ON-1 | 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+ 1. +5V
12. BL-DIM-1 | | 9. SCL-SET 2. LEFT-- 2. GND 2. USB-WIFI-DDn
13. BL-I-CTRL-1 | | 10. GND 3. RIGHT-+ 3. RIGHT-- 3. USB-WIFI-DDp 19220_006_120215.eps
14. POWER-OK-1 41. 51. 11. SDA-SET 4. RIGHT-- 4. GND 120223

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 Block Diagrams Q552.4E LA 9. EN 74

9.6 Wiring diagram 5000 & 5500 series 40"

WIRING DIAGRAM 40" 5000 and 5500 Series

DISPLAY 8M95
PANEL

WOOFER
(5214)
1M95
14P

1D02
3P
1G51
51P
SSB
1316 1M95
14P
B (1150)

1G50
INLET

41P
1D01
4P
8G50

1C30
8308

4P
8G51
MAIN POWER SUPPLY
(1005)

1C20
11P
(1114)

1308
2p3
MOD CONTROL BOARD

TO DISPLAY TO DISPLAY

8C20
TWEETER TWEETER
(5216) (5216)

8F24
WIFI (1115) SENSOR BOARD (1122)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G50 (B09A) 1G51 (B09A) 4. GND
8. +12VAUDIO 1. GND 1. +VDISP 5. KEYBOARD
9. GND 2. GND 2. +VDISP 6. +3V3-STANDBY
10. GND | 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A) 1C30 (B06B)
11. BL-ON-1 | 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+ 1. +5V
12. BL-DIM-1 | | 9. SCL-SET 2. LEFT-- 2. GND 2. USB-WIFI-DDn 19220_013_120223.eps
13. BL-I-CTRL-1 | | 10. GND 3. RIGHT-+ 3. RIGHT-- 3. USB-WIFI-DDp 120223
14. POWER-OK-1 41. 51. 11. SDA-SET 4. RIGHT-- 4. GND

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 Block Diagrams Q552.4E LA 9. EN 75

9.7 Wiring diagram 5000 & 5500 series 46"

WIRING DIAGRAM 46" 5000 and 5500 Series

DISPLAY
PANEL

8M95

1316 1M95
14P

WOOFER
(5214)
MAIN POWER SUPPLY
(1005)
1M95
14P

1D02
3P
SSB
B (1150)

1G51
51P
8G51

1G50
41P
8G50

2p3

1D01
4P
1308

1C30
4P
1C20
11P
8308

TO DISPLAY TO DISPLAY
INLET
MOD CONTROL BOARD

8C20
TWEETER TWEETER
(1114)

(5216) (5216)

8F24

WIFI (1115) SENSOR BOARD (1122)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G50 (B09A) 1G51 (B09A) 4. GND
8. +12VAUDIO 1. GND 1. +VDISP 5. KEYBOARD
9. GND 2. GND 2. +VDISP 6. +3V3-STANDBY
10. GND | 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A) 1C30 (B06B)
11. BL-ON-1 | 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+ 1. +5V
12. BL-DIM-1 | | 9. SCL-SET 2. LEFT-- 2. GND 2. USB-WIFI-DDn
13. BL-I-CTRL-1 | | 10. GND 3. RIGHT-+ 3. RIGHT-- 3. USB-WIFI-DDp 19220_008_120223.eps
14. POWER-OK-1 41. 51. 11. SDA-SET 4. RIGHT-- 4. GND 120223

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 Block Diagrams Q552.4E LA 9. EN 76

9.8 Wiring diagram 5000 series 55"

WIRING DIAGRAM 55" 5000 and 5500 series

DISPLAY
PANEL
8M95

1M95
14P

1M95
14P

1D02
3P
MAIN POWER SUPPLY
(1005)

1G51
51P
SSB
2p3
B (1150)

1G50
41P
1308 8G50

WOOFER

1D01
4P
(5214)
8G51
MOD CONTROL BOARD

1C30
4P
8308

1C20
11P
TO DISPLAY TO DISPLAY
(1114)

8C20
INLET

TWEETER TWEETER
(5216) (5216)
8F24 SENSOR BOARD (1122)
WIFI (1115) SENSOR BOARD (1122)

1M95 (B01A)
1. +3V3STBY
2. STANDBY
3. GND 1C20 (B01B)
4. GND 1. LIGHT-SENSOR
5. +12Vin 2. 3D-LED
6. +12Vin 3. LED-2
7. +12VAUDIO 1G50 (B09A) 1G51 (B09A) 4. GND
8. +12VAUDIO 1. GND 1. +VDISP 5. KEYBOARD
9. GND 2. GND 2. +VDISP 6. +3V3-STANDBY
10. GND | 3. +VDISP 7. RC 1D01 (B06A) 1D02 (B06A) 1C30 (B06B)
11. BL-ON-1 | 4. +VDISP 8. +5V 1. LEFT-+ 1. LEFT-+ 1. +5V
12. BL-DIM-1 | | 9. SCL-SET 2. LEFT-- 2. GND 2. USB-WIFI-DDn
13. BL-I-CTRL-1 | | 10. GND 3. RIGHT-+ 3. RIGHT-- 3. USB-WIFI-DDp 19220_096_120301.eps
14. POWER-OK-1 41. 51. 11. SDA-SET 4. RIGHT-- 4. GND 120301

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 Block Diagrams Q552.4E LA 9. EN 77

9.9 Block Diagram Video

VIDEO
B05G COMMON INTERFACE 1P00 B05 PNX85500 B09A VIDEO OUT - LVDS
17
+5VCA 7S00 1G50
18
PNX85637EB 32
51 7F01
B05J VIDEO OUT-LVDS PX1
52 74LVC245APW
20 TO DISPLAY
PCMCIA +3V3 B05F CONDITIONAL

68P
LOUT1
ACCESS
PX2 ONLY 5000 SERIES
3 100Hz PANEL
CONDITIONAL MDO(0-7) BUFFER CA-MDO(0-7) MD0 SSB 3139 123 6532x
ACCESS 1G51
CA-MDI(0-7) LOUT2 40
MDI
PX3
B08B DVBS-FE 7RA0 7RA1 B08A TUNER-CHANNEL DECODER TO DISPLAY
STV6110A STV0903BAC
1R01
4 DVB-S 21 IP 7 DVB-S 78 TS-INT-VALID 9RC2-1 TS-CHDEC-VALID R23 TNR_SER1_MIVAL PX4 11 ONLY x000 SERIES
TUNER CHANNEL 75 TS-INT-SOP 9RC2-2 TS-CHDEC-SOP R22
SAT IN 20 IM 8 TNR_SER1_SOP SSB 3139 123 6532x
DECODER TS-INT-CLOCK 9RC2-4 TS-CHDEC-CLK
32 XTAL 122 74 T22 OR
30 18 QP 12 73 TS-INT-DATA 9RC2-3 TS-CHDEC-DATA
TNR_SER1_MICLK
T21 TNR_SER1_DATA
B10A FPGA I/O BANKS 7K01
1G50
XC65LX25
19 QM 11 32
1RA0

16M

2 AGC 16 7KC0 PX1 PX1

31 CXD2834R LOUT3
ONLY **PFL***7/K** TO DISPLAY
4 TS-CHDEC-VALID
B08A TUNER-CHANNEL DECODER DVBT2
3 PX2 PX2 3
CHANNEL TS-CHDEC-SOP
1F00 FPGA
SUT-RE214Z DECODER 5 TS-CHDEC-CLK
LOUT4 2D>3D
IF_AGC 48 8 TS-CHDEC-DATA 1G51
4
AGC1 BL 40
2 5KC8 3KA0 IF-N-DVBT2 5KC1 2KCF 3KCB 37 B05K ANALOG VIDEO PX3
IF1-_P PX3
3 5KC9 3KA1 IF-P-DVBT2 5KC0 2KCE 3KCA 38 TO DISPLAY
IF1-_N ONLY **PFL***7/T**
RF IN
MAIN HYBRID B05K PNX85500: ANALOG VIDEO PX4 PX4
11
TUNER ONLY 5500 SERIES

PNX85637
8 5FA5 3FA4 3S4V 2S77 SOC-IF-P AE12 SSB 3139 123 6530x
IF2-_N TUNER_P
B07B FPGA - I/O BANKS B01A POWER CONNECTORS

3S4U
7 5FA4 3FA3 3S4W 2S78 SOC-IF-N AF12 7J01 1M54
IF2-_P TUNER_N XC65LX4 1
B05B STANDBY
9 SOC-IF-AGC AD12 CONTROLLER
BL-DIM1-8 TO PSU
AGC2 IF_AGC AF24 PNX-SPI-CLK 67 9
AE23 PNX-SPI-SDO 66 FPGA
AF25 PNX-SPI-SDI 62 BL B01B INTERFACE CONNECTORS
AF23 61 1A04
B06D HDMI B05L ANALOGUE EXTERNALS A PNX-SPI-CS-BLn
27AMBI-SPI-OUT-MOSI 3

7NC1 26AMBI-SPI-OUT-CCLK 5
SII9287BC 1VA1 RES
1P05 10 AV1-R AC13
AV1_R B06B USB HUB +5V-USB1
1 DRX2+ 26 14 AV1-G AE13 1P08
3 AV1_G 7FL5 1
DRX2- 25 18 AV1-B AD13
AV1_B CY7C65632
1

4 USB1-DM 2
2

DRX1+ 24 5 AV1-CVBS AB15 15

6 CVBS_Y1 16 USB1-DP 3
DRX1- 23 EXT 1 7N05 7N06
RXD 4
7 DRX0+ 22 6 EF EF CVBS-MON-OUT1 AF11
CVBS1_OUT B05C MIPS
9 DRX0- 21
18

17 AV1-STATUS
19

10 DRXC+ 20 B05B +5V-USB2

12 7N03 AV1-BLK STANDBY CONTROLLER 1P07
HDMI SIDE DRXC- 19 1
9 R26 USB-DM 1
CONNECTOR USB_DN
R25 USB-DP 2 2
USB_DP 12 USB2-DM
HDMI 13 USB2-DP 3
1P04 USB 4
1 ARX2+ 72
SWITCH HUB
3 ARX2- 71 B05F NANDFLASH +5V-USB3
B05F NANDFLASH
1
2

4 ARX1+ 70 B05N VGA 1P06

1
7S0A 1
6 ARX1- 69 1N05
H27U4G8F2DTR

3 2
RXA
7 ARX0+ 68 1 R-VGA AF16 VGA_R 6 USB3-DM 2
3

4
9 67 2 G-VGA 7 USB3-DP
18

ARX0- AD16
10
19

15

VGA_G
5

10 ARXC+ 66 3 B-VGA AE16 4

12 13
VGA_B XIO_D XIO-D(00-07) NAND SIDE USB
HDMI 3 ARXC- 65 H-SYNC-VGA AB18 11
HSYNC_IN FLASH CONNECTOR
1

CONNECTOR +5V
11

14 V-SYNC-VGA AC18 1C30

1FL5
VSYNC_IN

12M
E21 NAND-CE1n 9 1
NAND_CE1
VGA F21 NAND-RDY1n 7 2
1P03 NAND_RDY1 10 3 USB-WIFI-DDn
CONNECTOR A21 NAND-WPn 19 3
1 8 NAND_WP_ 4 USB-WIFI-DDP
BRX2+
B05M ANALOGUE EXTERNALS B 4
3 BRX2- 7 VCC
5
1
2

4 BRX1+ 6 12,37
+3V3
6 BRX1- 5
RXB AV3-Y AE15
7 BRX0+ 4 Y_G1 B05E SDRAM
9 3
B04A DDR
BRX0-
18

AV3-PB AD15
19

EXT 3 A2
10 BRXC+ 2 PB_B1 VREF_1 DDR2-VREF-CTRL2
V1
HDMI 2 12 BRXC- 1 VREF_2 DDR2-VREF-CTRL3
CONNECTOR AV3-PR AC15
PR_R_C1
DQ DDR2-D(0-31)
1P02 7B00 7B01 7B02 7B03

D(16-23)

D(24-31)
D(8-15)
D(0-7)
1 CRX2+ 18 EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
B05E HDMI_DV
3 CRX2- 17
62 HDMIA-RXC+ W25
SDRAM SDRAM SDRAM SDRAM
1

4 CRX1+ 16 TXC_P RXC_A_P

2

63 HDMIA-RXC- W26
6 CRX1- 15
RXC
TXC_N
HDMIA-RX0+
RXC_A_N 128Mx8 128Mx8 128Mx8 128Mx8
60 V25
7 CRX0+ 14 TX0_P RX2_A_P
61 HDMIA-RX0- V26
9 CRX0- 13 TX0_N RX2_A_N

VDDL
VREF

VDDL
VREF

VDDL
VREF

VDDL
VREF
18

58 HDMIA-RX1+ U25
19

10 CRXC+ 12 TX1_P RX1_A_P

59 HDMIA-RX1- U26
HDMI 1 12 CRXC- 11 TX1_N RX1_A_N
56 HDMIA-RX2+ T25 A1 E2 A1 E2 A1 E2 A1 E2
CONNECTOR TX2_P RX0_A_P
57 HDMIA-RX2- T26 A DDR2-A(0-14)
9,27,64 TX2_N RX0_A_N
+3V3-HDMI VCC33 W24
RREF +1V8
3S0W

DDR2-VREF-DDR

+3V3

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 Block Diagrams Q552.4E LA 9. EN 78

9.10 Block Diagram Audio

AUDIO
B05G COMMON INTERFACE 1P00 B05 PNX85500 B06A CLASS-D AMPLIFIER 5D78
17
+5VCA 7S00 7D60 1D01
18 TAS5731
PNX85637EB L+ 1
51 7F01 1D02
52 74LVC245APW B05H PNX85500 AUDIO
5D75 2 1
20 L-
PCMCIA +3V3 B05F CONDITIONAL SPEAKER L 2
WS AD2 WSI2SOUT 20

68P
ACCESS R+ 3 3
I2S_OUT_SD1 AE1 SDI2SOUT1 22
I2SCLK 9D53
SCK AD1 21 5D80
CONDITIONAL MDO(0-7) BUFFER CA-MDO(0-7) MD0 R- 4 SPEAKER
ACCESS 9D52 15
SPEAKER R WOOFER
CA-MDI(0-7) MDI B05B STANDBY 7D61 5D72
CONTROLLER PASSIVE 2.1
P0.7 AC19 AUDIO-MUTE-UP 19
B08B DVBS-FE 7RA0 7RA1 B08A TUNER-CHANNEL DECODER 5D71
STV6110A STV0903BAC 1 L+
1R01 1D01
4 DVB-S 21 IP 7 DVB-S 78 TS-INT-VALID 9RC2-1 TS-CHDEC-VALID R23 TNR_SER1_MIVAL L+ 1
6D60
TUNER CHANNEL 75 TS-INT-SOP 9RC2-2 TS-CHDEC-SOP R22 P0.6
AB19 RESET-AUDIO CLASS D
46 L- 1D02
SAT IN 20 IM 8 TNR_SER1_SOP 7D50-2
DECODER TS-INT-CLOCK 9RC2-4 TS-CHDEC-CLK POWER L- 5D81 2 1
32 XTAL 122 74 T22
TNR_SER1_MICLK 25 39 R+
30 TS-INT-DATA 9RC2-3 TS-CHDEC-DATA 7D50-1 AMPLIFIER SPEAKER L 2
18 QP 12 73 T21 TNR_SER1_DATA
19 QM 11 P3.2 AA22 DETECT2 R+ 3 3
1RA0

16M

36 R-
2 AGC 16 7KC0
31 R- 5D83 4
CXD2834R SPEAKER
SPEAKER R WOOFER
ONLY **PFL***7/K**
4 TS-CHDEC-VALID 5D77
B08A TUNER-CHANNEL DECODER DVBT2
3
ACTIVE 2.1
CHANNEL TS-CHDEC-SOP
1F00
SUT-RE214Z DECODER 5 TS-CHDEC-CLK 1D01
4 IF_AGC 48 8 TS-CHDEC-DATA L+ 1
AGC1
2 5KC8 3KA0 IF-N-DVBT2 5KC1 2KCF 3KCB 37 B05K ANALOG VIDEO 5D75 2
IF1-_P L-
3 5KC9 3KA1 IF-P-DVBT2 5KC0 2KCE 3KCA SPEAKER L
38
IF1-_N ONLY **PFL***7/T** R+ 3
RF IN
MAIN HYBRID B05K PNX85500: ANALOG VIDEO
R- 5D80 4
TUNER SPEAKER R

PNX85637
8 5FA5 3FA4 3S4V 2S77 SOC-IF-P AE12 2.0
IF2-_N TUNER_P

3S4U
3FA3 3S4W 2S78 B05I HEADPHONE
7 5FA4 SOC-IF-N AF12 7NN1
IF2-_P TUNER_N TS489
7NN1-1,2
AD12 B05H PNX85500 AUDIO
9 SOC-IF-AGC IF_AGC 5
AGC2
1NN2
ADAC3 AF7 ADAC(3) 2 AMPLI- 1
AD6 ADAC(4) 6 FIER 7
B06D HDMI B05L ANALOGUE EXTERNALS A ADAC4
HEADPHONE
OUT 3.5 mm
7NC1 1VA1 B05H PNX85500 AUDIO
SII9287BC 23 AUDIO-IN1-R AF10 AIN1_R
1P05 EXT 1 19 AUDIO-IN1-L AE10 AIN1_L B06B USB HUB +5V-USB1
1 DRX2+ 26 1P08
3 AV1_G 7FL5 1
DRX2- 25
AV1_B CY7C65632
1

4 USB1-DM 2
2

DRX1+ 24 15
6 DRX1- 23 B05M ANALOGUE EXTERNALS B CVBS_Y1 16 USB1-DP 3
RXD 4
7 DRX0+ 22 1VA4
AUDIO-IN3-R AF9
9 DRX0- 21 AIN3_R B05C MIPS
18

YPbPr
19

10 20 AUDIO-IN3-L AE9 AIN3_L

DRXC+ AUDIO +5V-USB2
HDMI SIDE 12 DRXC- 19 1P07
R26 USB-DM 1 1
CONNECTOR USB_DN
R25 USB-DP 2 2
USB_DP 12 USB2-DM
1N09
HDMI AUDIO-IN4-R AC9
AIN4_R
13 USB2-DP 3
1P04 PC USB 4
1 ARX2+ 72
SWITCH AUDIO
AUDIO-IN4-L AD9 AIN4_L
HUB
3 ARX2- 71 B05F NANDFLASH +5V-USB3
B05F NANDFLASH
1
2

4 ARX1+ 70 1P06

1
7S0A 1
6 69
ARX1- B05H PNX85500 AUDIO H27U4G8F2DTR

3 2
RXA
7 ARX0+ 68 6 USB3-DM 2
+3V3 3

4
9 67 7 USB3-DP
18

ARX0-
19

10 ARXC+ 66 4
1N10 2 7S09
12 +3V3 2 XIO_D XIO-D(00-07) NAND SIDE USB
HDMI 3 ARXC- 65 SPDIF 1 SPDIF-OPT 3 & 11
1 SPDIF-OUT-PNX AF5 SPDIF-OUT FLASH +5V CONNECTOR
CONNECTOR OUT 3 1C30

1FL5

12M
4 E21 NAND-CE1n 9 1
NAND_CE1
B02G STANDBY F21 NAND-RDY1n 7
8 5 SEL-HDMI-ARC AF18 NAND_RDY1 10 3 USB-WIFI-DDn 2
1P03 P0_4 A21 NAND-WPn 19
NAND_WP_ 4 USB-WIFI-DDP 3
1 BRX2+ 8
4
3 BRX2- 7 VCC
5
1
2

4 BRX1+ 6 12,37
+3V3
6 BRX1- 5
RXB
7 BRX0+ 4 B05E SDRAM
9 3
B04A DDR
BRX0-
18
19

A2
10 BRXC+ 2 VREF_1 DDR2-VREF-CTRL2
V1
HDMI 2 12 BRXC- 1 VREF_2 DDR2-VREF-CTRL3
CONNECTOR
DQ DDR2-D(0-31)
1P02 7B00 7B01 7B02 7B03

D(16-23)

D(24-31)
D(8-15)
D(0-7)
1 CRX2+ 18 EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
B05E HDMI_DV
3 CRX2- 17
62 HDMIA-RXC+ W25
SDRAM SDRAM SDRAM SDRAM
1

4 CRX1+ 16 TXC_P RXC_A_P

2

63 HDMIA-RXC- W26
6 CRX1- 15
RXC
TXC_N
HDMIA-RX0+
RXC_A_N 128Mx8 128Mx8 128Mx8 128Mx8
60 V25
7 CRX0+ 14 TX0_P RX2_A_P
61 HDMIA-RX0- V26
9 CRX0- 13 TX0_N RX2_A_N

VDDL
VREF

VDDL
VREF

VDDL
VREF

VDDL
VREF
18

58 HDMIA-RX1+ U25
19

10 CRXC+ 12 TX1_P RX1_A_P

59 HDMIA-RX1- U26
HDMI 1 12 CRXC- 11 TX1_N RX1_A_N
56 HDMIA-RX2+ T25 A1 E2 A1 E2 A1 E2 A1 E2
CONNECTOR 14 TX2_P RX0_A_P
57 HDMIA-RX2- T26 A DDR2-A(0-14)
9,27,64 TX2_N RX0_A_N
VCC33 W24
RREF +1V8
+3V3-HDMI
3S0W

DDR2-VREF-DDR
ARC-eHDMI+ 5CN2 eHDMI+
+3V3

19220_002_111223.eps
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 Block Diagrams Q552.4E LA 9. EN 79

9.11 Block Diagram Control & Clock Signals

CONTROL + CLOCK SIGNALS
B06C ETHERNET + SERVICE B05x PNX85500 B04A DDR B09A VIDEO OUT - LVDS
7S00
PNX85637EB 1G51
7N10 B05B CTRL-DISP3 51
B05C ETHERNET B05E SDRAM
DDR2-D(0-31)
1N00 LAN8710A-EZK DQ
BL-PWM 44
ETH-RXD RXD B01A
7B00 7B02 7B03 7B01

D(16-23)

D(24-31)
D(8-15)
3D-LR 42

D(0-7)
ETHERNET ETH-TXD TXD H5PS1G83EFR H5PS1G83EFR H5PS1G83EFR H5PS1G83EFR B05C TO DISPLAY
7 ETH-RXCLK AA3
RXCLK SDRAM SDRAM SDRAM SDRAM
20 ETH-TXCLK AA2
TXCLK 128Mx8 128Mx8 128Mx8 128Mx8
ETHERNET 5 LGD 50Hz 3D PANEL
CONNECTOR

1N70

25M
RJ45 1G51
4 CTRL-DISP3 51
B05B
F8 E8 F8 E8 F8 E8 F8 E8 CTRL-DISP1 44
B05B
19 RESET-ETHERNETn A DDR2-A(0-13) CTRL-DISP2 43
B05B N5 DDR-CLK_N B05B TO DISPLAY
CLK_N 3D-LR-DISP 42
N4 DDR-CLK_P B07B B10A
1N06 CLK_P
B05C CONTROL
2 RXD1-MIPS Y23
GPIO_2
UART OTHER PANEL
SERVICE 3 TXD1-MIPS Y24
GPIO_3
CONNECTOR 1 B07B FPGA-I/O BANKS B07A FPGA PWR & CTL B10A FPGA-I/O BANKS B10B FPGA SUPPLY & CTL
7J01 7J26 +3V3 7K00
XC6SLX4 NCP803 XC6SLX25 7K20
3
VCC
B08B DVBS-FE B08A DVBT2 B05F VIDEO STREAM 37 PROG-B 2
RESET FPGA-SYS-CLK-LX25
1 M9
B05C BL-DIM 7 GND B05C BL-DIM P11
7RA0 7RA1
STV6110A STV0903BAC
9RC2-3 B05C PNX-SPI-CS-BLn 61 7J23 B05C PNX-SPI-CS-BLn F10
32 XTAL 122 73 TS-INT-DATA TS-CHDEC-DATA T21
TNR_SER1_DATA PNX-SPI-CLK 67 74LVC1GU04 PNX-SPI-CLK D11
18 QP 12 74 TS-INT-CLK 9RC2-4 TS-CHDEC-CLOCK T22 7K22
SATELLITE MULTI TNR_SER1_MICLK PNX-SPI-SDI 62 PNX-SPI-SDI E11
19 QM 11 STANDARD 75 TS-INT-SOP 9RC2-2 TS-CHDEC-SOP R22 50 FPGA-SYS-CLK 4 2 M25P40
TUNER 7 DEMODULATOR 78 9RC2-1
TNR_SER1_SOP PNX-SPI-SDO 66 PNX-SPI-SDO D12
21 IP TS-INT-VALID TS-CHDEC-VALID R23
TNR_SER1_MIVAL P10 MISO-LX25 2 FLASH
20 IM 8 FOR SAT DIG TV 62 RESET-DVBS T10 MOSI-LX25 5 16Mbit
B05B 1J21
R11 CCLK-LX25 6
FPGA FPGA
SENSE+1V0-DVBS 52 7KC0 T3 CSO-B-LX25 1
B03A B05B B05B PQ-FPGA
CXD2834R 12M
4 TS-CHDEC-VALID SW

IF-P-DVBT2 36 DVBT2 3 TS-CHDEC-SOP

CHANNEL 5 TS-CHDEC-CLOCK B01A BL-DIM1 17 B01A BL-DIM1 F9

PNX85637
IF-N-DVBT2 37
DECODER 8 TS-CHDEC-DATA
29
RESET-FUSION-OUTn B05C 3D-LR 17 B05C 3D-LR F12
B05C

3D-LR-DISP 46 B09A 3D-LR-DISP P12

B09A
B05F NANDFLASH B05G COMMON INTERFACE
1P00 7F00
5500 SERIES 5500 SERIES 5500 SERIES 5500 SERIES
1 20 MOCLK CA-MOCLK K24 B05C CONTROL
62 MOVAL CA-MOVAL L23
VS_2 B05C PNX85500: MIPS B06B USB HUB
+5V-USB1
MOVAL
63 MOSTRT CA-MOSTRT L22 PNX-SPI-CS-BLn 1P08
MOSTRT GPIO_7 V22
B07B B10A 7FL5 1
CY7C65632
MDI 15 USB1-DM 2
CA-MDI(0-7) cS53
AE4 RESET-SYSTEMn RESET-FUSION-OUTn 3
7F01 RESET_SYS B08A 16 USB1-DP
4
BL_PWM AD5 BL-DIM B07B B10A
MDO(0-7) CA-MDO(0-7) MDO +5V-USB2
COMMON INTERFACE

7F02 1P07
R26 USB-DM 1 1
7F03 B05F FLASH USB_DM
7S0A R25 USB-DP 2
H27U4G8F2DTR PCMCIA USB_DP 12 USB2-DM 2
13 USB2-DP 3
NAND CA-A(00-14) XIO-A(0-15) XIO_A
GPIO_10 V23 BL-I-CTRL-PNX USB 4
CONDITIONAL 7F04 B05D
FLASH HUB
12,37 ACCESS 7F05 Y22
VCC +3V3 GPIO_1 3D-LR
B07B B09A B10A +5V-USB3
1P06

1
CA-D(0-7) XIO-D(00-15) XIO_D 1
B06D HDMI

3 2
68 6 USB3-DM 2
MAIN 7NC1 3

4
XIO-D(00-07) 7 USB3-DP
SW SII9287BCNU 4
TO PIN:
31 ARX-HOTPLUG 1P02-19 SIDE USB
RX HDMIA-RX 11
35 BRX-HOTPLUG 1P03-19 CONNECTOR
HDMI +5V

1
1C30

2
B01B INTERFACE CONNECTORS B01A POWER CONNECTORS B05B STANDBY

1FL5

12M
41 CRX-HOTPLUG 1P04-19
B05E HDMI_DV 3S0W SWITCH 1
1C22 1C20 45
RREF W24 +3V3
DRX-HOTPLUG 1P05-19
10 3 USB-WIFI-DDn 2
1 1 LIGHT-SENSOR AE26 P5_1

18
USB-WIFI-DDP 3

19
2 2 4
3D-LED B07B B10A
9U41 4
3 3 LED-2 LED2 AC25 PWM_1 1P02-13 4x HDMI
7NC0 5
4 4 1P03-13
TO
P1_2 AF19 CEC-HDMI EF PCEC-HDMI 1P04-13 CONNECTOR
SENSOR 5 5 KEYBOARD AD23 P5_0
+3V3-STANDBY 1P05-13
& 6 6
LED-1 B01A +3V3-STANDBY
CONTROL
7 7 RC AD19 P1_0
BOARD
8 8
+5V 7U43 B05B PNX85500: STANDBY CONTROLLER B05D PNX85500-CONTROL
10 B01B LED-1 EF LED1 AD26 PWM_0
P2_4 AA21 CTRL-DISP1
B09A
P2_5 AB21 CTRL-DISP2
B09A
B01A POWER CONNECTORS B05B PNX85500: STANDBY CONTROLLER P0_0 AB17 CTRL-DISP3
B09A
1M95
B07B B10A
11 BL-ON AE20 7F52
P2_2
2 STANDBY AF20 P2_3 M25P05-AVMN6P
TO 3 AC21 P2_6
POWER SUPPLY
POWER-OK
AF24 PNX-SPI-CLK 6
FLASH
13 BL-I-CTRL SPI_CLK 512K
B05D AE22 PNX-SPI-WPn 3
P6_5 8
AF23 PNX-SPI-CSBn 1 VCC +3V3-STANDBY
12 BL-DIM-1 9U44 BL-DIM AV1-STATUS AE25 SPI_CSB
B05C B05L CADC_2 AE23 PNX-SPI-SDO 5
SPI_SDO STANDBY
LCD-PWR-ONn AC20 AF25 PNX-SPI-SDI 2
4000 AND 5000 SERIES B05P P2_0 SPI_SDI SW
RESET-DVBS AA18 AF18 SEL-HDMI-ARC 1F51
9U43 BL-DIM1 B07B B08B P0_1 P0_4 B05H
AE21 RXD-UP 3
B10A RESET-ETHERNETn AE18 P0_3 P3_0
B06C TXD-UP 1 LEVEL SHIFTED
5500 SERIES AF21
RESET-USBn AD18 P1_1 P3_1
B06B AB20 SDM FF04 2 FOR
P1_7
BL-PWM B09A DETECT2 AA22 P3_2 AA26 RESET-STBYn SDM 4 DEBUG USE
B01A RESET_IN ONLY
AV1-BLK AD22 P3_5 AF22 SPI-PROG FF29 5
B05L P6_4
+3V3-STANDBY SPI-PROG
RESET-SYSTEMn AB22 P3_3 7S20 RES
CONTROL

ENABLE-3V3-5V B02E AE17

B02C XTAL_IN NCP303LSN28G
ENABLE-1V8 RESET-AUDIO AB19 P0_6
B06A 1
1S02

B02A RESET-STBYn
54M

+12V 2
DETECT2 B06A
AUDIO-MUTE-UP AC19
P0_7 INP OUTP 9F51
+3V3-STANDBY B05B B06A AF17 3 BL-I-CTRL-PNX BL-I-CTRL
XTAL_OUT GND B05C B01A
ENABLE-3V3n AD21
P2_7
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 Block Diagrams Q552.4E LA 9. EN 80

9.12 Block Diagram I2C

IC
B05D PNX85500: CONTROL B05C PNX85500: MIPS B05D PNX85500-CONTROL B05O TEMP SENSOR B06D HDMI B03B DVBS-SUPPLY B06A CLASS-D B07B FPGA B05C PNX85500: MIPS B08B DVBS-FE B08A TUNER
AMPLIFIER I/O BANKS CHANNEL
7S00 +3V3 DECODER
PNX85637EB

3S6`L
3S6D
B05C
B25 3S5Y SDA-SSB-550 cS51 SDA-FE
3_SDA
A24 3S5Z SCL-SSB-550 cS52 SCL-FE
3_SCL

3NC5

3NC3

3TPD

3RA8

3RA7

3KC3

3KC2
3TPB

3D55

3D56
3FD3

3FD4
+3V3

3J04

3J03
AIN-5V
ERR
PNX85637 13
1 2 53 54 6 9 23 24 40 41 98 97 21 20

3NC1-1

3NC1-3
3S6A
3S69
CONTROL 1P04
C25 3S56 SDA-UP-MIPS 7FD1 7NC1 7TP2 7D60 7J01 7R01 18 7KC0
29 ARX-DDC-SDA 16 SDAT

1
2
1_SDA LM75BDP SII9287B LNBH25 TAS5731 XS65LX4 STV903BAC CXD2820R
C26 3S57 SCL-UP-MIPS 19
30 ARX-DDC-SCL 15 SCLT
1_SCL TEMP LNB AUDIO FPGA CHANNEL DEC DVBT2
7F52

18
19
SENSOR HDMI BIN-5V CONTROLLER AMPLIFIER BL DVBS CHANNEL

3F60

3F59
M25P05-AVMN6P B05B B05B PNX85500: STANDBY MUX HDMI DECODER
CONTROLER
5 6 CONNECTOR 3 13 12

3NCA-1

3NCA-2
ERR ERR ERR ERR ERR
FLASH 6 PNX-SPI-CLK AF24 +3V3-STANDBY 42 ERR 1P03 31 37 38 28
8 SPI_CLK 23
3 PNX-SPI-WPn AE22 STANDBY 7F58 33 BRX-DDC-SDA 16 7R02

1
+3V3-STANDBY VCC

2
P6_5
M24C64 STV6110A

3S6W
512K 1 PNX-SPI-CSBn

3S6V
AF23
SPI_CSB 34 BRX-DDC-SCL 15
5 PNX-SPI-SDO AE23 ERR ERR 3S2F

18
SPI_SDO

19
15 53 AC23 EEPROM CIN-5V SATELITE
2 PNX-SPI-SDI AF25 SPI_SDI MC_SDA (NVM) RES HDMI TUNER
STANDBY 3S2G
AC24 CONNECTOR 2

3NCA-3

3NCA-4
SW MC_SCL 1F52 B06D HDMI
ERR 1P02 ERR
RES 35 3F63 3 36
39 CRX-DDC-SDA 16

1
DEBUG

2
+3V3-STANDBY 3F62 1
MAIN NVM ONLY
40 CRX-DDC-SCL 15
SW
B05F

18
FLASH

19
DIN-5V

3S1G

3S1H
1F51 uP HDMI
AE21 RXD-UP 3F65 3 LEVEL CONNECTOR 1

3NCT-2

3NCT-1
7S0A P3_0 SHIFTED 1P05
AF21 TXD-UP 3F64 1 FOR DEBUG
H27U4G8F2DTR DRX-DDC-SDA 16
P3_1 43

1
HDMI

2
USE ONLY
CONNECTOR
FLASH RES 44 DRX-DDC-SCL 15
B05F SIDE

18
19
(4Gx16)
FLASH OPTIONAL OPTIONAL
XIO-D(00-07) XIO_D B05N VGA
+5V-EDID +5V-VGA
MAIN
B05K

3NCP-3

3NCP-1
SW

3FC1

3FC2
1N05
9FC1 12

10
B05K 47 VGA-SDA-EDID-HDMI

15
PNX85500:

5
ANALOGUE ANALOG VIDEO
VIDEO EDID 9FC3
48 VGA-SCL-EDID-HDMI 15
SW

6
11
AD25 3S5V-1 VGA-SDA-EDID 9FC2
VGA_EDID_SDA
B04A DDR 3S5V-3 9FC4 VGA
AD24 VGA-SCL-EDID
VGA_EDID_SCL CONNECTOR
RES +3V3
RES
7B00 7B01

3NCU-2

3NCU-4
EDE1108AGBG EDE1108AGBG
B05E
Y25 DDCA-SDA
SDRAM SDRAM DDC_A_SDA
128Mx8 128Mx8 Y26 DDCA-SCL
DDC_A_SCL
D(8-15)

+3V3
D(0-7)

B05E HDMI_DV
B08A TUNER

SDRAM
3S6G
3S6F

1FA0
DDR2-A(0-13) A 4_SDA B24 3S60 SDA-TUNER 3
DDR2-D(0-31) DQ DEBUG
4_SCL A23 3S61 SCL-TUNER 1 ONLY
7B02 7B03 RES
3FA1 5FA7

3FA2 5FA6
EDE1108AGBG EDE1108AGBG ERR
18
D(16-23)

D(24-31)

SDRAM SDRAM
128Mx8 128Mx8 11 10

1F00
SUT-RE214Z

MAIN
TUNER

ERR
34
B06C ETHERNET + SERVICE +3V3
3S6C
3S6B

B08A VIDEO OUT - LVDS 1G51

7N10
3S58 SDA-SET 9S12 SDA-DISP 3G2W 50
LAN8710A-EZK 2_SDA B26
LVDS
2_SCL 3S5W SCL-SET 9S11 SCL-DISP 3G2Y 49 CONNECTOR
A25
11 ETH-RXD(0) Y5 +3V3
RXD_0
10 ETH-RXD(1) Y6
RXD_1 ERR ERR
9 ETH-RXD(2) AB4 14
2 1 64
RXD_2
3S67

3S65

3S68

3S66

+3V3
ETHERNET 8 ETH-RXD(3) AC1
RXD_3
7 ETH-RXCLK AA3 7S01 4
RXCLK
3S81

3S80

PCA9540B B01B INTERFACE CONNECTORS TS1 TEMP SENSOR

5
22 ETH-TXD(0) AA1 GPIO_4 W21 RXD2-MIPS
TXD_0 2 CHAN. 1T71 1T02
23 ETH-TXD(1) AA4 3C83 3124
TXD_1 MULTIPLEX. 3 3 SDA-TEMP1
24 ETH-TXD(2) AB1 GPIO_5 W22 TXD2-MIPS 7
ETHERNET TXD_2
25 ETH-TXD(3) AB2 ERR
3C81 1 1 3123 SCL-TEMP1
CONNECTOR TXD_3 24 8
RJ45 20 ETH-TXCLK AA2
TXCLK +3V3 B06C ETHERNET + SERVICE
RES 1 2
3S83

3S84

1N06 9S13
3N53-4 3N53-3 SDA-BL 7104
Y23 RXD1-MIPS 3
GPIO_2 LM75ADP
UART 9S10 SCL-BL
Y24 TXD1-MIPS 3N53-2 3N53-1
GPIO_3 2 SERVICE TEMP
CONNECTOR 1C20 SENSOR
1
3C95 11
CONTROL
3C94 9
RES 19220_001_111223.eps
SW Programmable via USB 111223
OPTIONAL

2012-Jun-29 back to
div. table
 Block Diagrams Q552.4E LA 9. EN 81

9.13 Supply Lines Overview

SUPPLY LINES OVERVIEW
B01A POWER CONNECTORS B03B CORE VOLTAGE SUPPLY FOR DVBS B05I HEADPHONE B07A FPGA - POWER & CONTROL
DEMODULATOR
1M95 1M95 +3V3-STANDBY +3V3-STANDBY +3V3 +3V3
1TP1 B01a B02c
1 1 +3V3-STANDBY B01b,B02a, +12V +12V-DVBS
B01a B03a 5J20 VAUX
3V3SB B05a,B05b, B07b
2 2 STANDBY T 3.0A +3V3 +3V3
B05B B05c,B05d, 7TP2 B02c 7J20
STANDBY
3 3 B05i,B05p, LNBH25PQ VCCINT
GND1 IN OUT B07b
4 4 B06a,B06d
GND1 COM
5 5 cU40 +12VD 3 LNB 20 +V-LNB
+12V3 B05p B08b 5J21 VCCO3
CONTROLLER
+12V3
6 6 B05L ANALOGUE EXTERNALS A B07b

5J22 VCCO2

PSU
1U40 +12V B07b
B01b,B02a,
+3V3 +3V3
B02b,B02c, B02c
T 3.0A 5J23 VCCO1
B03b +5V +5V B07b
7 7 B04A DDR B02c
+VSND
8 8 +12V-AUDIO 5J24 VCCO0
+VSND B06a B07b
9 9 +1V8 +1V8
GND1 B02a
10 10 3B20
GND1
11 11 BL-ON
DDR2-VREF-DDR B05M ANALOGUE EXTERNALS B
BL-ON-1 B05B
BL-DIM-1
12 12 BACKLIGHT-PWM_BL-VS
B05C +3V3 +3V3
B07B FPGA - I/O BANKS
13 13 BL-I-CTRL B02c
BL-I-CTRL-1 B05D VAUX VAUX
14 14 POWER-OK
B05B
B05A PNX85500: POWER B07a
POWER-OK-1
VCCINT VCCINT
+1V1 +1V1 B07a
B02a

B02b
+1V2 +1V2 B05N VGA B07a
VCCO3 VCC03
1N05
+1V8 +1V8 VGA 9 +5V-VGA
+3V3 +3V3 B02a B06d
B02c CONNECTOR
+2V5 +2V5 VCCO2 VCCO2
B02b B07a
+2V5-AUDIO +2V5-AUDIO VCCO1 VCCO1
B05h B07a

B01B INTERFACE CONNECTORS B02b

+2V5-LVDS +2V5-LVDS B05O TEMP SENSOR
B07a
VCCO0 VCCO0
+3V3 +3V3 +3V3 +3V3
B01a +3V3-STANDBY +3V3-STANDBY B02c B02c
+3V3-STANDBY +3V3-STANDBY
+3V3 +3V3
B02c B01a
B08A TUNER-CHANNEL DECODER
5C54

7FA0
1T71 +5V 5FA0 +VCC-TUNER
B02c
B01a +12V 5C53 1C85
4 TEMP B05P VDISP - SWITCH IN OUT
SENSOR COM
T 1.0A (OPTIONAL) B05B PNX85500: STANDBY CONTROLLER
+3V3 +3V3
+3V3 5KC6 +3V3-DVBT2-D
RES B02c B02c
+1V1 +1V1 +3V3-STANDBY +3V3-STANDBY
B02a B01a
+1V2-FE 5KC7 +1V2-DVBT2-C
+12VD +12VD B03a
B01a
B02A DC / DC +3V3-STANDBY +3V3-STANDBY 3KCE +1V2-DVBT2-P
B01a
1UU0 +VDISP
7UU0 B09a
+3V3-STANDBY +3V3-STANDBY
B01a T 2.0A
+12V +12V
B01a
B05C PNX85500: MIPS 7UU2 B08B DVBS-FE
5U02

LCD-PWR-ONn 7RC1
+3V3 +3V3 +5V 5RC0 +3V3-DVBS
7U03 B02c B02c IN OUT
TPS53126PW 7U02-1 12V/1V8 COM
+3V3-STANDBY +3V3-STANDBY
CONVERSION 5RA0 +3V3-DEMOD
B01a
Dual
12
5U00 +1V8
B06A CLASS-D AMPLIFIER
B02b, 5RA1 +3V3RF
Synchronous 7U02-2
Step-Down B03a,B04a, +3V3-STANDBY 7D80 +3V3-AUDIO 7RC0
Controller 14 B05a,B05e, B05D PNX85500: CONTROL B01a
B02c
+3V3 +2V5-DVBS
B03a
B10b IN OUT
+3V3 +3V3 5D84 +3V3D COM

12V/1V1 B02c +1V0-DVBS +1V0-DVBS

7U01 +3V3-STANDBY

3D83
CONVERSION +3V3-STANDBY B03a
B01a
1 5U01 +1V1 +12V-AUDIO +12V-AUDIO
B05a,B05b B01a +V-LNB +V-LNB
+5V +5V B03b
7U04
B02c
23

B05E PNX85500: SDRAM B06B USB HUB B09A VIDEO OUT - LVDS

3 10 ENABLE-1V8 B01A +3V3 +3V3

+1V8 +1V8 +3V3 +3V3
B02a B02c B02c
3S20 DDR2-VREF-CTRL3 +VDISP +VDISP
+5V +5V B05p
B02c
B02B DC / DC 3S06 DDR2-VREF-CTRL2 3F32 +5V-USB1
+3V3 +3V3 +T 3F34-4 USB-OVR1
B01a
+12V +12V B02c 3FL2
B10A FPGA - I/O BANKS
+5V-USB2
+5V +5V VAUX-LX25 VAUX-LX25
+T 3FL4-4 USB-OVR2 B10b
B02c
7UA4 3FL7 +1V2-LX25 +1V2-LX25
B02a
+1V8 VOLT. +1V2
B05a
B05F PNX85500: NANDFLASH +5V-USB3 B10b
CONDITIONAL ACCESS +T 3FL8-4 USB-OVR3
REG. VCCO3-LX25 VCC03-LX25
+3V3 +3V3 B10b
B02c
7UC0 VCCO2-LX25 VCCO2-LX25
+3V3 +2V5 B10b
B02c VOLT. B05a,B05h
REG. VCCO1-LX25 VCCO1-LX25
B10b
+2V5-LVDS
B05a B05G COMMON INTERFACE B06C ETHERNET + SERVICE
+3V3 +3V3 VCCO0-LX25 VCCO0-LX25
B02c B10b
+3V3 +3V3
B02c 5N08 +3V3-ET-ANA

B02C DC / DC +5V +5V

7UD0 +5V
B02c
B02b,B03a, 3F01 +5VCA
B10B FPGA - POWER & CONTROL

B01a
+12V 5UD0 VOLT. B05d,B05g,
+T B06D HDMI
+3V3 +3V3
REG. ENABLE-3V3-5V B01A B05l,B06b, B02c
B06d,B08a, B02c +3V3 +3V3
5K20 VAUX-LX25
B08b,B10b B10a
5NC0 +3V3-HDMI
B01a,B01b, 5K21 VCCO3-LX25
7UD1 +3V3 +3V3-STANDBY +3V3-STANDBY B10a
B02b,B03a, B01a
5UD3 VOLT. B05a,B05c,
ENABLE-3V3-5V 5K22 VCCO2-LX25
REG. B01A B05d,B05e, +5V-VGA +5V-VGA B10a
B05f,B05g, B05n
B05h,B05i, 5K23 VCCO1-LX25
B10a
B05l,B05m, +5V-EDID
B05o,B05p, 5K24 VCCO0-LX25
B03A
6NC1

DVBS-SUPPLY B06b,B06c,
B10a
B06d,B07a, +5V +5V 7K24
B02c
+3V3 +3V3 B09a,B08a, +1V8 +1V2-LX25
B02c
B08b,B10b
B05H PNX85500: AUDIO
1P04
B02a IN OUT
COM
B10a
HDMI 3 AIN-5V
+5V +5V 18
B02c +2V5 +2V5 CONNECTOR
B02b +5V +5V
+2V5-DVBS +2V5-DVBS B02c
B08b +3V3 +3V3 1P03
B02c HDMI 2 BIN-5V
7T00 18
CONNECTOR
+12V-DVBS 5T00 VOLT. +1V0-DVBS 3S11 +3V3-ARC
B03b
REG. B08b 7S08 1P02
HDMI 1 CIN-5V
+2V5-AUDIO 18
IN OUT B05a CONNECTOR
7T03
+1V8 5T03 +1V2-FE COM
B02a VOLT.
1P05
REG. B08a HDMI SIDE DIN-5V
18
CONNECTOR
19220_004_111229.eps
111229

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 82

10. Circuit Diagrams and PWB Layouts

10.1 A 715G5194 PSU 32" & 37" 3500/4000 series
10-1-1 AC Side

AC Side
A01 A01

HOT
!
F9902 FB9901
T4.0AH/250V SG9901 C9905 SG9903
4 3 NR9902 SPG-201M-LF 470PF 250V SPG-201M-LF
2 1 1 2 1 2
BEAD
COLD
t
2

FUSE-NC NTCR R9904

CN9901 510K-NC R9903
! L9901 L9902
! BD9901

3
1NF 250V-NC
TS6B06G-05-X0
AC SOCKET 220K 1/4W-NC
!

3
C9911
FB9906

TVR14561KFAOZF-NC
IC9901
!
TVR14561KFAOZF

! CAP004DG-NC C9902 C9901

1

B+

RV9903
1 8 220NF 220NF 4 11 2

2
NC NC 7
RV9901

!
-
2 +
D1 D2 6 BEAD
3
4 D1
NC NC
D2 5
R9902
220K 1/4W-NC 12MH ! 12MH
C9904
! ! 470PF 250V C9912

2
C9903 47PF-NC C9906 + C9909 + C9907 + +
2
4

47UF 450V 47UF 450V 47UF 450V 10NF

R9906 FB9902
F9901
FUSE ! 2M2 5% 1/2W
R9901
510K-NC R9905
SG9902
SPG-201M-LF
2 1 C9913
47UF 450V-NC
T4.0AH/250V 220K 1/4W-NC SG9904
SPG-201M-LF
1
3

NR9901 BEAD
1 2
t

2
1
NTCR

L
N
RV9902 SG9905 SG9906 BO
TVR14561KFAOZF-NC DA38-622MT-A21F-NC DA38-622MT-A21F-NC

CN9902
CONN-NC
! ! !

HS9901 HS9902 HS9101 HS9102 HS9302

1 1 1 1 1
2 2 2 2 2
3 3 3 3 3 C9908 C9910
4 4 4 4 4 1NF 250V-NC 470PF 250V

HEAT SINK-NC HEAT SINK-NC HEAT SINK HEAT SINK HEAT SINK
!
1

FB9302
BEAD
2

1 2012-01-09

AC Side
715G5194

19240_500_120213.eps
120213

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 83

10-1-2 LED

LED
A02 A02
DIM IC8102 COMP
C8119
1 8 1UF 16V
EN DIM COMP
D8102 L8102 2 7
3UH 3 EN GM 6
+12V2 VCC ISET
1 2 4 5

2
+24V1 VLED LED GND R8101
LED2
PF7700S 10K 1/8W 1%
+ C8108 L8101 SR510-22
150UF 35V 25UH + R8121
C8125 + R8120 100K R8122 C8109
R8109
12UF 160V 100K 100K 470NF 50V
C8132
R8115 220UF 100V
R8125 820K 1%
2R2 +-5% 1/8W Q8101 NC
AOD4126

1 R8124 R8123
22OHM +-5% 1/8W 10K OHM +-5% 1/8W
DIM IC8105 COMP
D8101 C8101
SS1060FL 1 8 1UF 16V
EN DIM COMP
2 7
3 EN GM 6
2

+12V2 +12V2 VCC ISET

4 5
LED GND R8104
LED5
R8116 PF7700S 10K 1/8W 1%
0.05R

R8134 R8117 470NF 50V

R8114 R8112
0 OHM +-5% 1/8W-NC 820K 1% C8107
FB COMP
+12V
R8119
510K 1% 1/8W NC
DIM
C8122
2

C8123 IC8107 0R05 1/4W R8113 NC R8131

8
7
6
5

100N 50V 91KOHM +-1% 1/8W 0 OHM +-5% 1/8W

C8127 + ZD8101 R8126
VCC
OUT
GND
DIM

DIM IC8104 COMP

PF7900S

10UF 50V MTZJ13B-NC 200 OHM 1/4W C8103

1 8 1UF 16V
1

EN DIM COMP
GM

CS
RT

Q8103 2 7
FB

+12V EN GM
C8120 MMBT3906-NC 3 6
+12V2 VCC ISET
1N 50V 2 3 4 5
1
2
3
4

+12V2 LED GND

100KOHM +-5% 1/8W R8107
LED4
R8118 R8130 PF7700S 10K 1/8W 1%
10K OHM +-5% 1/8W-NC

1
R8133
FB
24K 1/8W 1%-NC 470NF 50V
R8103
R8127 C8111
180K +-1% 1/8W C8126 C8124 R8128
1N 50V EN
100N 50V 10K OHM +-5% 1/8W-NC
9

CN8102
R8132 NC
1 LED5 9.1K OHM-NC
2 10K OHM +-5% 1/8W-NC
LED3
3 LED4 R8129
4
LED6 ON/OFF
5 LED1
6
LED2
7 C8113 Q8102
DIM IC8106 COMP
8 100N 50V-NC MMBT3904-NC C8102
VLED
1 8 1UF 16V
EN DIM COMP
CONN-NC 2 7
3 EN GM 6
10

+12V2 VCC ISET

4 5
LED GND R8111
DIM IC8103 COMP LED6
C8104 PF7700S 10K 1/8W 1%
1 8 1UF 16V
EN DIM COMP
2 7
EN GM
14

CN8101 3 6 470NF 50V

+12V2 VCC ISET R8102
4 5 C8106
LED GND R8108
DIM IC8101 COMP LED3
12 C8105 PF7700S 10K 1/8W 1%
VLED
11 1 8 1UF 16V
EN DIM COMP NC
10 2 7
LED4 EN GM
9 3 6 470NF 50V
LED1 +12V2 VCC ISET R8105
8 4 5 C8115
LED5 LED GND
7 R8110
LED1
6 PF7700S 10K 1/8W 1%
5
LED2 NC
4
LED6
3 0.47UF 50V
LED3 R8106
2 C8110
1
VLED

CONN NC
13

1 2012-01-09

LED
715G5194

19240_501_120213.eps
120213

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 84

10-1-3 Main Power

Main Power
A03 A03
B+_main

HOT COLD R9104

R9147 100 OHM 1/4W
2Mohm 1/4W +/-1%-NC

R9103
100 OHM 1/4W

B+_main
R9105
R9148 100 OHM 1/4W +12V
2Mohm 1/4W +/-1%-NC +12V1

T9101 !
C9108 8 9 C9103

3
10NF 10 D9102 1.5NF L9101
C9120 FMEN210A 3UH
1.5NF 15 2
R9149 R9113 6 16
2Mohm 1/4W +/-1%-NC 100KOHM +-5% 2WS 5 14 C9112
C9106 + C9105 + C9107 + 0.47UF 50V R9158 R9159 R9160 R9161 R9162

1
470UF 35V 470UF 35V 270UF 25V 1.5K 1/4W 1.5K 1/4W 1.5K 1/4W 1.5K 1/4W-NC1.5K 1/4W-NC
R9164 R9182
Q9108 VCC1 1 13 24R 1% 24R 1%
TK2P60D-NC 12
D9101 R9163 R9181
C9132 R9155 PR1007 24R 1% 24R 1%
100N 50V-NC 10K OHM +-5% 1/8W
11
POWER X'FMR R9106 R9153
R9177 R9111 24R 1% 24R 1%
100KOHM +-5% 1/8W-NC 10K OHM +-5% 1/8W
IC9103 R9102 R9152
1 8 22OHM +-5% 1/8W SS1060FL 24R 1% 24R 1%
2 BNO OVP 7 R9109 D9104
R9129 3 COMP VCC 6 2 1
0 OHM +-5% 1/8W 4 NC OUT 5 Q9101 R9107 R9154
CS GND TK6A65D 24R 1% 24R 1% +24V2 +24V +24V2
+24V1
LD7523GS
R9127
100R 1/8W 5% R9110
10K OHM +-5% 1/8W C9102

3
D9103 1.5NF L9102
R9150 C9113 FMXA-2202S 3UH
470NF 50V VCC1
2K 1/8W 1% 2
Q9107

2
C9114 R9138 C9125 AOD409-NC
100N 50V R9108 10 OHM 1/4W-NC ZD9106 1N 50V-NC +24V

1
+24V1
0.27R MTZJ27B C9101 R9180 R9178 R9179
C9135 R9171 220UF 35V 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC
C9134 1uF-NC 470R R9137

1
1uF-NC 680 OHM 1/4W-NC
C9136 C9104 + + R9173

2
1uF-NC 560UF 35V 100KOHM +-5% 1/8W-NC
220 OHM 1/4W C9109 ZD9107 Q9111 R9172 R9174
R9112 560UF 35V P6KE27A-NC 2SD1624T-TD-E 1K OHM +-5% 1/8W 100KOHM +-5% 1/8W-NC R9135 + C9111
R9156 27K 1/8W 1%-NC 0.47UF 50V
ZD9104 680 OHM 1/4W-NC
C9124

1
B6V2-NC 100N 50V-NC
C9128 1 2
1N 50V C9131 R9176 MMBT3904-NC
100N 50V 3K 1/8W +/-1% Q9112 R9151
IC9105 1K OHM +-5% 1/8W-NC
+12V1 R9175 AS431AN-E1-NC
1K OHM +-5% 1/8W-NC

R9136
3K 1/8W +/-1%-NC

R9115
470OHM +-5% 1/8W +12V +24V1 +24V1

R9124
2K 1/8W 1%-NC
4

C9129 IC9101 R9114

C9133 PC123X8YFZOF
1NF 250V-NC C9117 3K 1/8W +/-1% R9118 R9116
6.8nF 9K1 1/8W 1% 120KOHM +-1% 1/8W R9139 R9140 R9141 R9142 R9143 R9144 R9145 R9146 R9165 R9166
3

470PF 250V
! C9119
10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC

100N 50V R9101

5K1 1/8W 1% C9126 C9127
! 470NF 50V-NC 470NF 50V-NC
2

D9107
FB9905 C9122 C9130 BAV99
2

1NF 250V-NC 470PF 250V

1 2 ZD9105
MTZJ15B
3

BEAD R9117 DV5 5.2V

! AS431AZTR-E1 1K8 +/-1% 1/8W
1

IC9102
C9110 C9123 Q9106
4.7uF 25V 4.7uF 25V R9126 MMBT3906 PNP
110R
R9128 R9134
200 OHM 1/4W 10K OHM +-5% 1/8W

5.2V HOT R9123

Protect 5.2V R9131
R9130 0 OHM +-5% 1/8W
10K 1/4W
VCC

1
2K 1/8W 5% R9132
+24V +12V IC9104
! 100KOHM +-5% 1/8W-NC

PC123X8YFZOF

2
R9169 R9167 Q9103 Q9105 R9133
10K OHM +-5% 1/8W 1K OHM +-5% 1/8W 2SD1624T-TD-E 2N7002K-NC Q9104 20K +-5% 1/8W
2N7002K
2

Protect PS_ON

100N 50V-NC
C9121
D9108 ZD9102 R9125 C9116
SS1060FL MTZJ30B ZD9101 100KOHM +-5% 1/8W 100N 50V R9120
Q9110 MTZJ18B R9119 100KOHM +-5% 1/8W

2
VCC1
1 2 MMBT3906 100KOHM +-5% 1/8W-NC
1 1

1 1

ZD9103
D9105 MTZJ18B
SS1060FL
D9106 R9170 C9118 +

1
R9168 R9122 SS1060FL 5.1K 1/4W 4.7UF 50V-NC
1K OHM +-5% 1/8W 10K OHM +-5% 1/8W
2

MMBT3904
Q9102
C9115 R9121
470NF 50V 10K OHM +-5% 1/8W

1 2012-01-09

Main Power
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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 85

10-1-4 Standby

Standby
A04 A04

FB9304
C9137 C9139
! 1 2 CN9301 CN9303

BEAD 12 12
470PF 250V-NC220PF 250V +24V
11 11
10 10
HOT COLD 9 9

1
8 8
R9319 D9306 7 7
47 OHM 1/4W SJPW-T4VL-NC 6 6
5 5
C9301 4 4

2
B+_main R9303 1.5NF 3 3
FB9301
0.1R 47 OHM 1/4W 2 2
R9302 1 1
1 2
R9304
B+ BEAD 47 OHM 1/4W L9302
3UH-NC CONN-NC CONN-NC
R9301
100KOHM +-5% 2WS-NC T9301
1 D9302
C9312 FMW-2156
BO
10NF 1.5NF
!
1
C9302

3
ZD9315 2 6 R9309 + C9316
P6KE160A 7 10K 1/4W 100UF 50V
5.2V
D9301 2
1N4007 9 L9301
2

3 10 3UH
5 + + + C9313

1
270UF 25V C9305
R9305 C9303 C9304 0.47UF 50V
2R2 +-5% 1/4W D9308 470UF 10V 470UF 10V
4 CN9302 CN9304
D9303 POWER X'FMR 1 2
D9304 PR1007 13 13
ON/OFF
R9306 PR1007 12 12
DIM
1.5M 1% SR240S-NC 11 11
VCC
R9307 10 10
+12V
220R 1% 9 9
R9308 + C9306 8 8
0.75R 100UF 50V 7 7
6 6
R9310 IC9301 5 5
1.5M 1% 1 8 R9311 4 4
PS_ON
1

1
2 S/OCP D/ST 7 8K2 1/8W 1% 3 3
3 BR D/ST IC9302 1K OHM +-5% 1/8W 2 2
GND GND_Audio 5.2V
4 5 D9305 R9312 1 1
FB/OLP VCC PC123X8YFZOF P_OK
SS1060FL
3

A6069H C9307 R9314

2

R9313
1.5M 1%
! 220N 50V 1K OHM +-5% 1/8W
CONN CONN-NC
C9308
1N 50V R9315
4.7M 5% 1/8W

IC9303 5.2V
AS431AN-E1
+ C9309 R9316 R9318
R9317 C9311 10UF 50V 9K1 1/8W 1% 43K 1/8W 1%
C9310 560K 1/8W 1% 100N 50V
220NF
2

R9323
ZD9316 Q9301 10K OHM +-5% 1/8W 10K 1/4W-NC
GDZJ5.6B 2N7002K R9320 R9321
0R05 1/4W-NC
DV5
1

P_OK EN
R9332
100KOHM +-5% 1/8W
R9324
0 OHM +-5% 1/8W
ON/OFF

C9314 C9317
470PF 250V 1NF 250V-NC

!
1 2012-01-09

Standby
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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 86

10-1-5 Power layout top

GND3 CN9301 GND4

CN8102 CN8101

J943
J942
L8102 CN9303
GND10
D8102

GND11
J937

J947
J924
J938

J925
C8128
L8101 C8125 J939

J940 C9101
J927

R8116 C8132 J928

J930
C8129

J931

J932
L9102
C8108

J945
L9101

J923
C9107

J948

J949

J950

J944

CN9304
ZD9107 J951
J922

CN9302
ZD9104

J952

J933
CTI1

J934

J935
J965

J966
L9302 C9316
J967

R9171 C9109
J953

J954
C9313

J946
ZD9106 J955

C9104 J929

J936
C9102

ZD9101

ZD9102
J921

J926

J941
C9105
D9103

C9301
C8127
C9106

J961
D9308
L9301

J962
J956 J958
HS9302 D9302
GND7 HS9102 J957 J959
GND9
J960

J969

C9103 C9304 C9303

J963

J919
D9102

J912
J920

C9317

ZD9316

J968
FB9304

FB9303
IC9102
C9130
T9301
T9101

IC9302

IC9104
J973
C9139

C9314
IC9101

ZD9105

ZD9103

D9303
C9137
R9113

D9101
C9120

C9122
J974

J918
GND13

D9304 GND12
J913

J917
J915

FB9905 C9302
IC9301 C9306
FB9302

C9309
ZD9315

R9108

J971
C9911
GND2 C9118 GND5
R9308

C9310

C9910 J916
Q9101
R9301

C9108 C9312

C9905
R9313

C9904
J903

HS9101 J907
J904
C9908
J970

R9310
FB9301
J908

J909
R9306 SG9902

RV9903 C9901
D9301

SG9901

L9901
C9912 J911
R9302
J910
FB9906

SG9904
C9903

J901

J902
R9901

C9902
R9904
J964

FB9902

L9902
CN9902

C9907 C9906
FB9901

GND8 C9909 C9913 BD9901

SG9903 NR9901
R9906

NR9902
RV9901
J972

C9129
HS9902 HS9901 SG9905
SG9906
J906

F9901
J905

F9902
C9133 RV9902

CN9901

GND1 GND6 1 2011-12-21

Power
715G5194
layout top

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 10-1-6

R9120
R9133 R9132
C9116
R9131
Q9104
D9105

R9324
C9121

RJ906
Q9105
R9119

Q9106 R9130 D9106 C9305 C9112

R9134
R9321

RJ908
R9323

RJ917
Q9102 C9115

D9108
R9168
R9121
R9122

R9123 R9167 R9309 R9158

Q9110

R9128
R9169 R9162

Q9103
C9111

Q9301

R9320 R9332
R9318
R9159

R9170
R9314
Power layout bottom

IC9901 R9304 R9160

R9161

RJ903

R9125
IC9303 D9306

R9311 R9316

C9307
R9303

R9905
R9312
R9319

R9902
D9305 R9307
RJ902

R9903
C9311

R9305
C9308
RJ911

R9317
R9315
C8102 C8101
R9178
IC8106 IC8105 IC8104 C8103
C9134 R9180
R8102
R8111
R8104
R8112

C8106 C8107 C8111

R8103
R8107

C9136 R9179
RJ915
RJ916
RJ905

C8104 C8119 C8105

IC8103 IC8102 IC8101

RJ909
R8105
R8108
R8101
R8109
R8110
R8106

RJ913
C8115 C8109 C8110

R8133
R8132
R8121

R8120 R8122
R8129
Q8102

R9147
Q8103
C8113 R8130
R8128 R8131
R8134

R8114 R8117

R9148
C9132 R8115
R8119
R9177
RJ901

C9135 C8122
Circuit Diagrams and PWB Layouts

R9155 Q9108

R9129
R8113

R9149
RJ904 C8124 C8123
R8118

C8126
R8127
C9114
D9104 C8120 IC8107
R9150 R9111
C9113 R8126

R9109
R9127
R9110
C9117

IC9103 D8101
R9103 R9107 R9154 R8125
R9112
R8123
R8124

C9128 R9104 R9106 R9153

Q9107
R9138

R9105 R9164 R9182

R9115 Q8101

RJ907
RJ919
R9102 R9152
C9125
Q552.4E LA

D9107 R9163 R9181

RJ914 R9173
R9174
C9110 R9137
R9114

R9116 R9172
Q9112
R9156

R9118
R9124

C9123 C9126
R9175

C9127
Q9111

C9119 R9101
R9176
C9131
R9144
R9139
R9140
R9143
R9141

R9117

R9126
R9166
R9165
R9146
R9142
R9145

IC9105
C9124

R9136
10.

RJ910 R9135 R9151

TEST1
EN 87

2012-Jun-29 back to
div. table
Power
layout bottom
715G5194
1
2011-12-21

120215
19240_505_120215.eps
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 88

10.2 A01 715G5246 PSU 42" 3500/4000 series

10-2-1 Power Circuit

Power Circuit
A01 A01
D9802 FB9803
1N5408-11 60R SB+
1 2 B1+

2
RV9902
TVR14561KFAOZF
FB902
BEAD ! FB9804
BEAD FMN-1106S
FB9801
BEAD R9330
24V
CN903

+
L9801 D9801 R9329 T9301 ! 47 OHM 1/4W
! R-
4 - 1 1 2 300UH 1 2 1 2 1 12
11
0.1R R9331 10

1
C9833 FB9802 R9325 R9327 47 OHM 1/4W 9
! SG9904
DSPL201M-A21F
BD9901
C9820
47pF
1 2
100K 100K
2 6
7
8
7

1
4 L9903 1 TS10B06G-06-X0 6

3
1UF 450V BEAD + + + + 1NF ZD9302 9 1NF 5
SG9905 C9171 C9801 C9802 C9804 C9805 C9803 C9331 P6KE160A 3 10 C9338 4

1
2
DSPL201M-A21F
! 2.2NF 47UF 450V 47UF 450V 47UF 450V 47UF 450V 470PF1KV 5 D9308 3

1
3 2 R9326 R9328 L9304 2

L
N

2
FMW-2156 DIM
1
On/Off
12MH 100K 100K 2
5.2V
4
BOX CN904
POWER X'FMR 5uH
R- VCC R9332 + C9340 + + C9341 C9342 CONN

3
C9911 CONN-NC C9831 2R2 +-5% 1/4W 470uF 16V 100N 50V
470uF 16V C9344
470NF 305V D9305
NC VCC1 NC
D9803
R9807 RB160M Q9801 FR107 5.2V
IC9801 R9323
470 OHM 1/4W R9808 2 1 TK18A60V
1 8 10R 1/8W 5% 4.7M OHM +-5% 1/4W D9307
2 FB VCC 7 R9334
COMP OUT FR103
R9904
510K ! !
R9905
510K
3
4 RT
VREF
GND
CS
6
5 R9809 ! IC9301 D9306
220 OHM 1/4W
IC9901 A6069H
ZD9106 ZD9107 30 OHM
!1 1N4148

1
NC BZT52-B5V1 BZT52-B22 R9813 8
R2A20113ASP

2
1 8 R9804 10K 1/4W 2 S/OCP D/ST 7 + C9337 R9342
NC NC BR D/ST
2
3 D1 D2
7
6 ! R9805
200KOHM 1/8W +/-5%
NC + C9830
10UF 50V
C9828
100N 50V
R9801
0.05R
3
4 GND 5
47UF 50V
! R9343 10K 1/8W 1%

1
4 D1 D2 5 C9826 FB/OLP VCC R9335 On/Off

2
NC NC R- P_OK EN
220pF 50V

1
+ C9336 3K3 1/8W 5% 0 OHM 1/8W
R9806 C9829 100N 50V R9301 C9335 IC9303

2
B1+ 10UF 50V
C9901 56K 1/8W 1.2R 100N 50V PC123X8YFZOF
100 OHM 1/4W 0R05 680K OHM +-1% 1/4W R9345
NC R9817 DIM
On/Off
R9320 R9337
C9824 C9825 R9811 510K 1% 1/8W 12.7 KOHM +-1% 1/8W NC

2
C9906 C9907 C9827 R9810 R9816 R9815 R9814 C9333 CN902
470PF 250V 470PF 250V 22N 50V 220N 50V 100P 50V 13K OHM 1% 680K OHM +-1% 1/4W 0.47UF 50V ZD9303
1K 1/8W 680K OHM +-1% 1/4W C9334 GDZJ15B 13
R9818 1N 50V C9343 12
R9336
220N 50V 1K 1/8W 1% 11

1
12V
Q9802 10
! ! ! NTD4906NT4G VCC1
!
24V 9
8

100N 50V
C9832
10K 1/8W R9317 R9318 R9319 7
R9819 1.5M 1% 1/4W 1.5M 1% 1/4W 1.5M 1% 1/4W D9304 R9339 6

3
NC 5
R9141 BOX
ZD9304 1 Q9301 4
VBoot PS-On
NC NC 3
B1+ IC9304
! FR107 2

2
R9144 R9150 R9142 5.2V
0.1R D9113 ! AZ432AZTR-G1 R9338 1

1
P_OK
2 L9901 3 R9102 7.87K 1%
T9101
SG9903 SG9902 NTD4906NT4G
UF4007
2
RB160M
1
10 OHM
Q9101
TK10A50D ! 11
CONN
GS41-201MA GS41-201MA Q9104 1M 1% 1/4W 1.5M 1% 1/4W 1.5M 1% 1/4W D9114 R9151
1 4 1K 1/8W 10 OHM D9115

1
R9164 R9155 15 FMEN-2308 R9340
R9152
12MH 14 R9341 NC
100 OHM 1/4W
! ! 2
NC
100N 50V

10K 1/8W
R9165

R9901 IC9101 47OHM +-5% 1/8W

VCC1
C9162

R9153
1 18 1 13

3
1MOHM +-5% 1/2W 2 Vsen NC 17 10K 1/8W 1% 2 12
Vcc NC DV5
3 16
4 FB VGH 15 6 24V
5 GND VS 14 7 +24V
C9910 6 Css VB 13 9
OC NC
470NF 305V
! C9145
R9145 7
8 RC
Reg
NC
VGL
12
11
D9112
8

100N 50V 20K 1/8W 1% 9 10 D9116 L9103 L9105

1
C9908 C9909 RV COM RB160M FMEN-2308 5uH 5uH
470PF 250V 470PF 250V SSC9512S-TL 2 1 10
24V-LED
C9151
1UF R9154 ! POWER X'FMR 2
2

C9153 47OHM +-5% 1/8W R9103 Q9102

C9152 ZD9104 TK10A50D

3
1

!! ! ! 1.5NF 1UF GDZJ15B

C9160 + C9161 + + C9164
D145T60P7_5-1_2-R 10 OHM 560UF 35V R9174 C9165 330UF 35V R9171 R9172 R9173
1

VCC1 VBoot R9156 560UF 35V 5.1K 1/4W 100N 50V 5.1K 1/4W 5.1K 1/4W 5.1K 1/4W
t NR9902
NTCR
10K 1/8W 1%
2 2

t
D145T60P7_5-1_2-R
470 OHM 1/8W
NR9901
NTCR ! C9146
100N 50V + C9147 R9149 C9156
22UF 50V
1

! RV9901
R9101 100PF1KV L9106

TVR14561KFAOZF
C9150
0.47UF 50V
R9148
NC
C9154
560P 50V
200R 1/8W 1% C9155
1N 50V ! C9157
27NF
5uH
12V

C9163
+ C9168 + + C9169 C9170
2
4

24V HS9101 470UF 25V 470UF 25V R9175 R9176 R9177 100N 50V
F9901 470UF 25V 1.5K 1/4W 1.5K 1/4W 1.5K 1/4W

3 1
FUSE 4 2
1
3

! R9147
12V 24V Main_ov
24V 12V

470 OHM 1/8W R9158

3.9K 1/4W HEAT SINK
5.2V DV5 5.2V
DV5
! R9146
R9159
3.3K 1/4W Q9305

2
2K43 1/8W 1%
! R9180
4

1 2 IC9106 R9161 27K 1/8W 1% MMBT3906 PNP ZD9101 ZD9102

PC123X8YFZOF 24K 1/8W 1% GDZJ30B GDZJ15B
Main_ov
HEAT SINK CN901 C9158 R9308 R9311 R9143 R9111
HS9901 SOCKET NC VCC1 VCC R9346 10K 1/8W 1%
3

1
C9149 1K 1/4W NC NC NC
1 100N 50V C9159
1
2

2 CN905 C9148 R9160 R9178 5.2V

3 CONN 4.7UF 10V 330NF 50V 5.1K 1/4W R9307 D9109 D9110
10K 1/8W 1% R9333 R9324
4 Q9303 10K 1% 1/4W 1N4148 1N4148
2

1
C9166 2SD1624T-TD-E 1K 1/8W 1% 1K 1/8W 1%
ZD9105 NC D9302
1 NC R9306
2 10K 1/8W 1% RB160M
R- R9309
3 R9163
1

1 2

4 HS9801 2K 1/8W 1% 100K 1/8W 1% D9301

Q9302
4

IC9107 HS9301 Q9304 20K OHM 1 2 Q9106

RK7002BM
FB903
NC C9904
AS431AZTR-E1
! HEAT SINK (D9308) + C9302
22UF 50V
IC9302
PC123X8YFZOF
2N7002
R9303 R9139
NC HEAT SINK RB160M MMBT3906 PNP 100 OHM 1%
3

PS-On Q9103
1 2 1 R9310
C9345 R9138
2 100N 50V PMBS3904
2

R9304
! 3
4 ZD9301 !R9302 100K 1/8W 1% C9301
100N 50V 100K 1/8W 1%
GDZJ18B 100K 1/6W 5% 1K 1/8W 1%
C9144
HS9802 FB9302 C9912 100N 50V R9140
1

470PF 250V 1K 1/8W 1%

1 1 2 HS9103
2
3 HS9102 ! C9903
BEAD !
FB9904 C9905 1
3 1 470PF 250V 2
SHIELD 4 2 1 2 3
SB+
470PF 250V 4
BEAD

HEAT SINK 1 2012-01-10

! HEAT SINK
Power Circuit
! 715G5246

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 89

10-2-2 24 V to VLED

24 V to VLED
A02 A02
1
2
24V-LED VLED

2
3
L8101
D8120
25UH MBRF10150CT R8154 R8155
C8118 + + C8108 100K 100K R8156
100UF 100V 100UF 100V 100K

4
Q8101
R8145
TK12A10K3 270K 1/4W

R8147
110K OHM 1%

R8161
R8177 R8157 2.2 OHM 1/8W
12V_LED NC R8175 10K 1/8W 1%
0.1R
R8144
R8158
430K 5%

1
22 OHM 1/8W
LED-COMP R9316
R8176
12V NC
0 OHM 1/4W
D8118
RB160M R8141

2
C8111 IC8103 20K 1% 1/8W Q9306
2

8
7
6
5

100N 50V R8162 C8106

MMBT3906 PNP
ZD8103 C8121+ 1K 1/8W 1% NC 12V 12V_LED
FB VCC
GM OUT
RT GND
CS DIM

PF7900S

BZT52-B13 R8153
22UF 50V R9313
DIM
15K 1% 1/8W
1

0 OHM 1/8W
1
2
3
4

R9344
R8148
10K 1/8W
1K 1/8W 1%
R9312
51K OHM
C8105
R8163 1N 50V C8119
EN
200K 1% NC
C8113 R9321
1N 50V Q9308
On/Off
PMBS3904

33K OHM R9315

3.9K1% 1/8W
R9322
C9346 100K 1/8W 1%
100N 50V

1 2012-01-10

24 V to VLED
715G5246

19240_507_120213.eps
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2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 90

10-2-3 LED Driver

LED Driver
A03 A03
IC8501
1 8 IC8502 IC8503
DIM DIM COMP LED-COMP
2 7 1 8 1 8
EN FLAG GM DIM DIM COMP LED-COMP DIM DIM COMP LED-COMP
3 6 2 7 2 7
12V_LED VCC ISET EN FLAG GM EN FLAG GM
4 5 3 6 3 6
LED-1 LED GND 12V_LED VCC ISET 12V_LED VCC ISET
R8501 4 5 4 5
LED-6 LED GND LED-2 LED GND
PF7703S 11K 1% C8501 R8502 R8503
1UF 16V 11K 1% C8502 11K 1% C8503
PF7703S PF7703S
C8158 + C8157 1UF 16V 1UF 16V
100N 50V C8529
NC C8523 100N 50V
100N 50V

IC8504 IC8506
1 8 IC8505 1 8
DIM DIM COMP LED-COMP DIM DIM COMP LED-COMP
2 7 1 8 2 7
EN FLAG GM DIM DIM COMP LED-COMP EN FLAG GM
3 6 2 7 3 6
12V_LED VCC ISET EN FLAG GM 12V_LED VCC ISET
4 5 3 6 4 5
LED-5 LED GND 12V_LED VCC ISET LED-4 LED GND
R8504 C8504 4 5 R8506 C8506
1UF 16V LED-3 LED GND 1UF 16V
PF7703S 11K 1% R8505 PF7703S 11K 1%
PF7703S 11K 1% C8505
C8518 1UF 16V C8530
100N 50V C8524 100N 50V
100N 50V

IC8507
1 8 IC8508
DIM DIM COMP LED-COMP IC8509
2 7 1 8
EN FLAG GM DIM DIM COMP LED-COMP
3 6 2 7 1 8
12V_LED VCC ISET EN FLAG GM DIM DIM COMP LED-COMP
4 5 3 6 2 7
LED-8 LED GND 12V_LED VCC ISET EN FLAG GM
R8507 C8507 4 5 3 6
1UF 16V LED-7 LED GND 12V_LED VCC ISET
NC 11K 1% R8508 C8508 4 5
1UF 16V LED-14 LED GND
NC 11K 1% R8509 C8509
C8519 11K 1% 1UF 16V
PF7703S
100N 50V C8525
100N 50V C8531
100N 50V
IC8510
1 8 IC8511 IC8512
DIM DIM COMP LED-COMP
2 7 1 8 1 8
EN FLAG GM DIM DIM COMP LED-COMP DIM DIM COMP LED-COMP CN8503
3 6 2 7 2 7
12V_LED VCC ISET EN FLAG GM EN FLAG GM
4 5 3 6 3 6
LED-15 LED GND 12V_LED VCC ISET 12V_LED VCC ISET
R8510 C8510 4 5 R8511 4 5 R8512 C8512 1
1UF 16V LED-12 LED GND LED-16 LED GND 1UF 16V LED-11
PF7703S 11K 1% 11K 1% C8511 11K 1% 2
1UF 16V LED-16
PF7703S PF7703S 3
LED-12
4
LED-15
C8520 C8526 5
100N 50V 100N 50V LED-13
C8532 6
100N 50V LED-14
7
8
IC8513 VLED
1 8 IC8514
DIM DIM COMP LED-COMP
2 7 1 8
EN FLAG GM DIM DIM COMP LED-COMP
3 6 2 7 NC
12V_LED VCC ISET EN FLAG GM VLED VLED
4 5 R8513 3 6
LED-9 LED GND 12V_LED VCC ISET
11K 1% 4 5 CN8501
LED-10 LED GND CN8502
NC C8513 R8514 C8514
1UF 16V 11K 1% 1UF 16V
NC CN8504
12 12
C8521 11 11
100N 50V C8527 10 10 1
100N 50V LED-9 LED-1 VLED
9 9 2
LED-10 LED-2
8 8 3
LED-11 LED-3 LED-4
7 7 4
IC8516 LED-12 LED-4 LED-3
6 6 5
IC8515 LED-13 LED-5 LED-5
1 8 5 5 6
DIM DIM COMP LED-COMP LED-14 LED-6 LED-2
1 8 2 7 4 4 7
DIM DIM COMP LED-COMP EN FLAG GM LED-15 LED-7 LED-6
2 7 3 6 3 3 8
EN FLAG GM 12V_LED VCC ISET LED-16 LED-8 LED-1
3 6 4 5 C8516 2 2
12V_LED VCC ISET LED-13 LED GND 1UF 16V
4 5 R8516 1 1
LED-11 LED GND R8515 C8515 PF7703S 11K 1%
11K 1% 1UF 16V NC
PF7703S
C8528 NC NC
C8522 100N 50V VLED VLED
100N 50V

1 2012-01-10

LED Driver
715G5246

19240_508_120213.eps
120213

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 91

10-2-4 Power layout top

J8536

J8540
CN8504 CN8503

J8535

J9106
J8558
CN8502 L8101

J8513
CN8501 J8533
J8532 J8534

C8108

C8118
J8531

D8120

CN903
J8564
J8537 J8538 J8539 J9118
J8501 J8504 J8507 J8510 J8514 J8517 J8521 J8524

J8502 J8505 J8508 J8511 J8515 J8518 J8522 J8525

HS9101 R8175
J8547
L9105

J9108
J8528 J8541 J8543 J8545 J8548 Q8101
C9164

J9117
J8520
J8529 J8542 J8544 J8546

C8121
J8503

J8506

J8509

J8512

J8516

J8519

J8523

J8552
J8527
J8526

J8554
J8553

J9101
J8530

J8549

J8550

J8551
J8565

HS9103

J9102
C8158

ZD9105
IC9107

IC9106 D9115 D9116

C9820
C9152 C9163
L9801
ZD9104
FB902

HS9901 BD9901

D9114
L9106
R9801

Q9102 C9168
J9910

J9114
J9902

HS9102
C9833 T9101 C9169

J9104
J9105
J9110
J9906
C9171 Q9101

J9103
J9111
CN902

C9160

C9161
FB9802

J9116
C9147 L9103
FB9801
D9802

FB9804

R9141
CN904 C9341
Q9801 C9156

J8561
D9801
J9909

J9107
J9904
J9911

J9912

J9113
J9903
RV9902
C9803
C9340 C9344
FB9302 C9912

J9112

J9109
SG9903 FB9803

J9905 J9115

ZD9101
FB9904 L9304

ZD9102
BD1
J9908

ZD9302
HS9801 C9905
SG9905

C9338
C9830
C9157
SG9904

L9903

D9109
D9110
C9331
J9907

D9304

D9305
R9329

D9308
T9301
R9905

C9802 C9805 C9801 C9804 R9301

NR9902 NR9901 J9309

C9911 IC9301
L9901 HS9301
J9307

D9307
C9901

J9901

F9901
R9901

R9904 C9336

J9305
J9308
D9306
C9910 RV9901 J9302 C9903

J9304
SG9902
J9301

ZD9303
C9337 IC9304
C9906 IC9303
C9907 C9908 HS9802 R9302
J9303

ZD9304
FB903

J9306
C9909 IC9302
ZD9301
CN901 C9302
CN905 C9904
GND1

1 2011-12-22

Power
715G5246
layout top

19240_509_120215.eps
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2012-Jun-29 back to
div. table
 10-2-5

R9343
R9139 C9170

C9144
R9140
R9342
C9165

Q9106

R9111

R9303
R9309

C9342
Q9302

R9177
R9311 R9304

R9138
Q9103

R9176
R9175
R9310 R9171
C9301 R9341
Power layout bottom

Q9304 C9345 R9172

R9340 Q9301

R9324
R9333
R9173

R9174
R9143

R9307
R9330
D9301
R9339
Q9305 R9331

R9308
R9338

R9337
R9336

C9343
R8154

R9178
R9335 R8156

R9346 R8155
R8157
R9334
D9302 R8161
R8162

R8158 D8118

R8153 C8105
IC8103
R8176 R8163

R9345 ZD8103
R9161 C8119
C8111
R9158
R8148

C8113

R9306
R9325
R9327
R9180
R9163

C8106

Q9303
JR8101

R8177

R9160
R9332 R8141
R9159

R9328
R8144 R8147
C9335 R9326 C9159
R8145

JR9102

C9158

R9316
R9313

Q9306
C9166
Circuit Diagrams and PWB Layouts

R9312
C9346
R9322
R9321

C9334
R9315

Q9308
C9333
R9320 C8528 C8532 R9344

IC8516 IC8512
R8512

C8512

R9323
R8516
C8520
C8516 C8526
R9142
IC8511 IC8510
Q552.4E LA

R8511 R8510
R9150

R9103 C8511 C8510

R9156

R9102
R9153

R9152 C8522 C8531

R9144

R9155 D9113 D9112

IC8515 IC8509
R9154 R8515
R8509

R9317
C9145
R9145

Q9104 C8515
10.

C8509
C8527
R9164
R9165
C9162

IC8514

R9318
C9146

C9153 R8514
C9150
C8514
R9148
R9149
IC9101

C9154
R9151

C8521
EN 92

R9319
R9101

IC8513
R8513
C9155

C9151
JR9101

C8513
C9149

2012-Jun-29 back to
div. table
C9148 R9146 R9147 C8519

IC8507
R8507
C8507
JR9104

R9817 C8525
R9814

IC8508
R8508
Q9802 C8508
R9816
R9815

R9811 C8523
C9832
R9819

R9818

JR9103 ZD9107 IC8502

D9803 R8502
R9810 C9828
R9809 C8502
C9827
IC9801
C9825

R9806
C8518
R9808

C9824
R9805 IC8504
R9813

C9826
C9829 ZD9106 R8504
R9804
C8504
R9807
C9831

C8530

IC8506
R8506
C8506

C8524

IC8505
R8505
C8505

C8529

IC8503
R8503
C8503

C8157

IC9901 IC8501
R8501
C8501
Power
layout bottom
715G5246
1
2011-12-22

120215
19240_510_120215.eps
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 93

10.3 B 313912365313 SSB

10-3-1 Power connectors

Power connectors
B01A B01A
* 1M54 FU7A
1 +3V3 +3V3-STANDBY
FU7B 3U84-1 1 8 100R BL-DIM1 ** To be connect directly to 1A04 with 3mm Track width
2
FU7C 3U84-2 2 7 100R BL-DIM2 ** 1M99
3
FU7D 3U84-3 3 6 100R **
4 BL-DIM3 1 GND-AL LED-2

RES 10K

RES 10K
FU7F 3U84-4 4 5 100R BL-DIM4 FU48
5 2

3U74

3U75
FU7G 3U85-1 1 8 100R BL-DIM5 **
6
FU7H
3 GND-AL ** +5V +3V3-STANDBY
3U85-2 2 7 100R BL-DIM6 +12V-AL
7 4
FU7J 3U85-3 3 6 100R BL-DIM7 IU43
8 5 9U41
FU7K 3U85-4 4 5 100R BL-DIM8
9 6

* AL 2U89

* AL 2U56
10n

10u

RES 10K
7

3U68

3U69
2041145-9

10K
1n0
1n0
1n0

1n0
1n0
1n0

1n0
1n0

8
IU44 3U41 3U59
2041145-8 IU45 LED2 LED2
LED-1 9U42 10K RES 10K RES
2U81
2U82
2U83
2U84
2U85
2U86
2U87
2U88

4 Pin stuffing variant 1M11 RES

GND-AL 7U42 RES +3V3
RES
RES
RES
RES
RES
RES
RES
RES

6 Pin stuffing variant 1M1B +12VIN BC847BW

IU47 3U70 3U53
7U43 LED1 LED1

RES 2U8D
BC847BW

10n
10K 10K

+3V3-STANDBY
2U47

2U68
10n

1u0

STANDBY-1 3U71
STANDBY
3U82
100R
2U54

10n

1K0 RES
7U48-1
BC857BS(COL) FU77
1 3U83-1 8 ENABLE-3V3-5V

6
100K

4 3U83-4 5
100K
2
2U71

100n
cU40 +12VD
+12VIN 1U40 +12V

T 3.0A 32V +3V3-STANDBY

2U50

10n

3
1M95
FU58 100HZ 3D 100HZ 2D LGD 50HZ
1
2
FU59
FU60
* with LX4 & LX25 3D TM100 7U48-2
BC857BS(COL)

5
3
3U42 x x --

6
4 7U40-2 3U83-3

3U62-3
9U43 x -- -- 2 3U83-2 7 6 3

10K
FU63 BC847BPN(COL)
5
FU75 9U44 -- x x 4
100K 100K
6 FU66 IU48

3
7 +12V-AUDIO
FU67 5
8

4
3

3U62-4
9
1 3U60-1 8
2U49

FU73 ENABLE-1V8

10K
10n

10
BL-ON-1

PDZ6.2B(COL)
11 IU56 22K

RES 10K
2

3U61
BL-DIM-1 3U81 10K BL-ON
+3V3

5
12

3U62-2
6U40
BL-I-CTRL-1

10K
13 IU49
POWER-OK-1 BL-PWM
14 6

2
7U40-1

7
3U60-2
IU51
1-2041145-4 FU51 3U45 100R
* 9U43 FU72

22K
BL-DIM1 BC847BPN(COL) DETECT2
2

* * 9U44
3U72
FU52 3U42 100R 1

1K0
BL-DIM 7U41-2

7
1u0 RES
3 BC847BS(COL)

6
2U55
FU53 3U43 100R BL-I-CTRL

3U60-3
FU76
5 3U60-4 4 ENABLE-3V3n

3U80
5

4K7

22K
IU55 3U73 3U62-1 22K
FU55 3U64 POWER-OK 4

3
+3V3-STANDBY
1 8
10K 6
1K0 3K3

3U63

RES 10K
7U41-1
100p

1n0

10n

BC847BS(COL) 2
2U53

3U65

100K

1
1n0

2U45
2U44

2U46
RES

4 2012-04-23

Power connectors 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_031_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 94

10-3-2 Interface connectors

Interface connectors
B01B B01B
+3V3

3C74

100K
RES
5C56 IC79 1C04 FC9F 2C76
+3V3 V-AMBI
30R T 1.0A63V FC87 3C75 100p
LIGHT-SENSOR
2C93 100R 2C77
V-AMBI V-AMBI
RESERVED
+3V3 47n RES 3C76 100p
RES 2C7G

2C7F
To sensor & control
1u0

1u0
RC

PDZ5.6B(COL)
IC73 100R 2C78
**

6C02
1C22

RES
FC88
RES IC74 100p 1
3C77

3C7F
LED-2

RES
1A05 1A04

10K
FC89 2
1 100R FC90
1 IC7A RES 9C08 FC71 3
RES 5C57 30R 2 9C06 FC91
2 3C7G 4
3 FC72 33R AMBI-SPI-OUT-MOSI +3V3-STANDBY FC92
3 5
4 2C7M 10p 2C79 FC93
4 6
5 FC73 3C7H 33R AMBI-SPI-OUT-CCLK FC94
5 IC7D 7
6 FC74 5C55 30R 2C7N 10p IC75 +5V
6 LED-1 3C78 100p 8

PDZ5.6B(COL)
7 FC75 AMBI-TEMP 3C70 100R AV2-STATUS
7
8 2041145-8

RES 6C07
8 100R 2C80

2C71

2C70

2C81
100n

100n
9

1u0
9 GND-AL
10
10 RES 2C94 100p
11 FC76
11 FC95 3C79
12 GND-AL KEYBOARD
12 IC7G RES 9C09 100n
13 9C07

RES
13 1C86 10R 2C82

6C03 RES
14 FC77 RES
**

PDZ5.6B(COL)

PDZ5.6B(COL)
14 +12V-AL
15 1C20 1C21
15 T 2.0A 63V 100p
FH52-18S-0.5SH

6C05
16 FH52-11S-0.5SH
16
RES 2C7K

RES 2C7L

2C95

2C96
17 1
10u

10n

10u

10n
17 1
18 2
18 2
19

19

20 20 3
3
4
4
FH34SRJ-18S-0.5SH(50) FH34SRJ-18S-0.5SH(50) 5
5
GND-AL GND-AL +3V3-STANDBY 6
6
7
7

2C90
IC7H 8

1u0
8
9
+3V3 9
10
10

**

** 2C91
2C99

100p
11

1u0
11
RES

* HOTEL TV * 1C03 12 13
12

**
**+T3C97 13

3C96
100R FC9L
* RES 3C98 1

4K7
RXD1-MIPS +5V 14
RES 3C99 100R FC9K 2
TXD1-MIPS
* 3 RES
0R3
FC9A
15
16
+5V 4 SCL-SET 3C94 47R
17
+12V 5 RES
FC9B 18
AMP1 6 SDA-SET 3C95 47R
AMP2 7 19 20
3C72 FC9D
8 3D-LED
9 10 100R

RES 2C86

RES 2C87

2C97

100p
502386-0870

10p

10p
RES 3C71 FC9G
1T71 TACHO cC01 IRQ-CRP
FC85 3C81 100R FC96
SCL-BL 1 RES 100R FC9H
TXD2-MIPS 3C73 47R
FC86 3C83 FC97 2
SDA-BL FC98 RES
3 3C7A FC9J
100R RXD2-MIPS 47R
4
5 6
2C84
2C83

10p
10p

502386-0470
TEMPERATURE

RES 2C7C
RES 2C7B

RES 2C72

100p
10p

10p
SENSOR

FC99

5C54
2C85

1u0

+3V3
30R
T 1.0A 63V
RES
1C85

RES 5C53 4 2012-04-23

+12V IC78
30R Interface connectors 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_032_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 95

10-3-3 DC/DC

DC/DC
B02A B02A
5U03 RES

30R
FU05 5U02 IU22
+12V
0R

7U02-1

2U24

2U23

2U20
2U25

2U19
10u

1u0
10u

10u

10u
SI4952DY
7 8
IU10
2
12V/1V8 CONVERSION

1
3U11

3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6

22u
3U23-4

3U23-3

3U23-2

3U23-1

2U15

2U16
47R

47R

47R

47R

47u
7U02-2
SI4952DY

1
5 6
IU09
4 IU23

2U17

1n0
IU15
7U01
SI4778DY-GE3

2U18

1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3
2U00

3U14
10u

3R3
3R3

3U04
2U22
IU06 2U02 IU07
IU05 IU13 220p

3U28

10R
100n
2U01

100n

3R3
7U04
7U03 3U05 SI4778DY-GE3
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
3 1
12V/1V1 CONVERSION
1 1
ENABLE-1V8 10 EN DRVH 12
2 2
1n0 RES

5U01 FU01
FU06
2U03

+1V1 4 24 +1V1
1 1

STPS2L30A
+1V8 9 VO SW 13

RES 100u 2.0V

2 2 2u0

6U00

2U14
5 22

3U24-4

3U24-3

3U24-2
1 1

3U24-1

RES
3U20

2U12

2U13
8 VFB PGND 15

22u
47R

47R

47R

47R

10R

47u
RES RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 IU02
GND-SIG 12K GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5

2U11
RES

1n0
+3V3-STANDBY 3U00 RES 2U06
+1V1 GND
2U04

2U05
6

10u

1u0

10K 100n
3U01

IU18
10K
RES

GND-SIG

2U09

2U10
1n0

1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%

3U17

1% 330R

2U29

100n
RES
IU20

100p RES

3U19
2U08

3U18
5K6

1% 1K0
3U08 3U22 FU09 FU08
IU04 CU00
+1V8
330R 1% 1K0 1% IU21
RES 100p

CU01
1K0 1%
3U09

3U10

2U07

CU02
22K

CU03
GND-SIG GND-SIG GND-SIG
CU04
CU05

GND-SIG GND-SIG GND-SIG

GND-SIG

4 2012-04-23

DC/DC 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_033_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 96

10-3-4 DC/DC, 1.8 V to 1.2 V conversion

DC/DC
B02B 1.8 V to 1.2 V conversion B02B

+12V +5V

+3V3 7UC0
LF25ABDT
FUA4

1 3UB0-1 8

2 3UB0-2 7

3 3UB0-3 6

4 3UB0-4 5

RES 9UA0
1 3 +2V5
IN OUT

4K7

4K7

4K7

4K7
COM

22u 16V
2UA4

2UB6
CUA0

1u0
+2V5-LVDS
FUA0

2
PDZ5.1B(COL)
6UA0

2UB1

1u0
7UA4-1

4
VDD RT9025-12GSP
FUA3
+1V8 3 6 +1V2
VIN VOUT
2 7
EN ADJ
2UB0

2UB2

2UB3
10u

10u

1n0
1
PGOOD
5
NC
GND
GND HS FUA5
3UB1
8

SENSE+1V2
3K9
1%

1%
22
23
24
25
26

3UB2

3UB3
10K

82K
7UA4-2
RT9025-12GSP
VIA

18 10
19 11
20 VIA VIA 12
21 13

VIA
14
15
16
17

4 2012-04-23

DC/DC 3 2011-12-12

3139 123 6533 2 2011-05-25

1.8 V to 1.2 V conversion

19220_034_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 97

10-3-5 DC/DC, 12 V to 5 V/3.3 V conversion

DC/DC
B02C 12 V to 5 V/3.3 V conversion B02C

12V/5V CONVERSION
7UD0
RT8293AHGSP
5UD0 IUD3 3UD0 IUD7 2UD5
IUD0 2 1
+12V VIN BOOT
0R 1R0 100n 5UD1 FUD3
7 3 +5V
EN SW
2UD0

2UD1

2UD2
10u
10u

10u

10u
2UD4 IUDC IUD6
8 5

100u 16V

100u 16V
10K 1%
SS FB

2UDD

2UDC

RES 2UDH
3UD5

RES 2UDF
2UDB
2UDA
22u

22u

22u
22u
100n 10 6
IUDH
VIA COMP
GND
GND HS
SS2_GND

2UD6

3UD2
4

RES

10R
3n3
ENABLE-3V3-5V
RES 1n0

IUDA
2UD3

cUD1

2UDG
3UD1

RES 2UD7

470p
RES
15K

10n
SS2_GND

2K2 1%
3UD4
3UD3

12K
SS2_GND
SS2_GND
SS2_GND
SS2_GND
12V/3V3 CONVERSION
7UD1
RT8293AHGSP
5UD3 IUD2 3UF1 IUD8 2UF2
IUD1 2 1
+12V VIN BOOT
0R IUDF 1R0 100n 5UD2 FUD2
7 3
EN SW +3V3
2UD8

2UD9

2UF0
10u

10u

10u

2UF1 IUDG IUD5 10u

8 5

4K7 1%

100u 16V

100u 16V
SS FB

RES 2UFA

RES 2UFB
3UF4

RES 2UF8

RES 2UF9
2UF7
2UF6

22u

22u

22u

22u
100n IUD4
10 6
VIA COMP
GND
GND HS

2UF3

3UF3
4

RES

10R
3n3
ENABLE-3V3-5V SS1_GND

1K5 1%
3UF5

3UF6
100K
IUD9
cUD2
3UF2

RES 2UF4

2UF5
RES

470p
12K

10n
SS1_GND SS1_GND SS1_GND

SS1_GND SS1_GND

4 2012-04-23

DC/DC 3 2011-12-12

3139 123 6533 2 2011-05-25

12 V to 5 V/3.3 V conversion

19220_035_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 98

10-3-6 DVBS supply

DVBS supply
B03A B03A

5T00 IT00
+12V-DVBS
30R
7T00

2T00

2T01

2T02

100n
TPS54227DDA

10u

10u

8
VIN

STEP DOWN IT02 2T05
2 7
VFB VBST 5T01 FT06
100n +1V0-DVBS
4 6 IT18
SS SW 3u0

RES 2T15

2T12
1

22u

22u
+2V5-DVBS EN
3 IT24
VREG5
IT01 3T00 RES
VIA

2T10
GND_HS GND

1u0
68K

10
11
3T04 RES

1n0
8K2 1%

RES 2T03

2T04

10n
IT04 2T13

1n0

1%
RES 2T14 FT07

470K

3T01
RES 3T02

22K
GND-1V0 GND-1V0 22p
3T05
SENSE+1V0-DVBS
8K2 1%
GND-1V0 GND-1V0 3T06

68K

cT01

GND-1V0

22
23
24
25
26
+5V 7T03-2
+3V3 RT9025-12GSP
2T16
5T03 VIA
+1V8 7T03-1 1u0
RT9025-12GSP 18 10
4

30R
VDD 19 11
3 6 FT09 20 VIA VIA 12
VIN VOUT +1V2-FE
21 13
220u 6.3V

2 7
EN ADJ
2T17

2T18

RES 2T20
10u

10u

VIA
1
PGOOD

14
15
16
17
5
NC
GND
GND HS
8

4 2012-04-23

DVBS supply 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_036_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 99

10-3-7 Core voltage supply for DVBS demodulator

Core voltage supply for DVBS demodulator

B03B B03B

+12V +12V-DVBS
1TP1

T 3.0A 32V

+12V-DVBS

ITPJ

2TPD

2TPC
2TPL

100n
10u

10u
+12V-DVBS +V-LNB

5TP5
10u
7TP2

17
LNBH25PQ
VCC
ITP4
LX
3
ITPF 2TPJ

B230LA-M3
16
VBYP

RS1D
6TP6

6TP5
470n
21
VUP
6 +V-LNB
ADDR FTPA
20 ITPG
VOUT
SCL-SSB-550 3TPB 47R 7
SCL

B230LA-M3
1

2TPK

6TP4
220n
SDA-SSB-550 3TPD 47R 8 DSQ 5

47u 35V

47u 35V
SDA

2TPG
2TPH
2TPF

470n
10
19 11
DETIN
NC 12
F22-DISECQ-TX 22 13
DEBUG IN
DEBUG 23 14
6TP1 OUT
+5V 3TP3 24
2 26
FLT
27
1K0 LTST-C190KGKT 18 28
BPSW
ITP2 29
3TPF 9 VIA 30
ISEL
22K 31
32
GND_HS

33
PGND
GND
15

25

4 2012-04-23

Core voltage supply for 3 2011-12-12

3139 123 6533 2 2011-05-25

DVBS demodulator

19220_037_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 100

10-3-8 DDR

DDR
B04A +1V8 DDR2-VREF-DDR +1V8 DDR2-VREF-DDR B04A

2B08
100p

100n
2B36
2B04

2B05

2B06

2B07
2B00

2B01

2B02

2B03
2B40

100n

100n

100n

100n
100n

100n

100n

100n
47u

2B37
2B17

100p
100n
2B41

2B09

2B10

2B11

2B12

2B13

2B14

2B15

2B16
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B02

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
EDE1108AGBG-1J-F 7B03

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF
AT T-POINT DDR2-A1 H3
0
DDR2-A0 H8
VDD VDDQ

3B22
DDR2-A2 H7
1
2 SDRAM 0
C8 2
3B00-2
7 DDR2-D16 DDR2-A1 H3
0
1 3B04-2
DDR2-CLK_P DDR2-A3 J2 C2 3 6 3B02-3 33R DDR2-D17 DDR2-A2 H7 SDRAM C8 2 7 DDR2-D24
3 1 2 0
DDR2-A4 J8 D7 33R 3 6 3B00-3 DDR2-D18 DDR2-A3 J2 3B05-3
C2 3 6 33R DDR2-D25
240R 4 2 3 1
DDR2-CLK_N DDR2-A5 J3 D3 1 8 3B02-1 33R DDR2-D19 DDR2-A4 J8 3B04-3
D7 3 6 33R DDR2-D26
5 3 4 2
DDR2-A6 J7 DQ D1 33R 2
3B02-2 7 DDR2-D20 DDR2-A5 J3 D3 33R 33R 2 7 3B05-2 DDR2-D27
3B27 6 A 4 5 3
DDR2-CLK_P DDR2-A7 K2 D9 3B00-4 4 5 33R DDR2-D21 DDR2-A6 J7 DQ D1 1 8 3B05-1 DDR2-D28
7 5 6 A 4
DDR2-A8 K8 B1 3B02-4
33R 4 5 DDR2-D22 DDR2-A7 K2 D93B04-4 4 5 33R DDR2-D29
240R 8 6 7 5
DDR2-CLK_N DDR2-A9 K3 B9 3B00-1 1 8 33R DDR2-D23 DDR2-A8 K8 B1 33R 4 5 3B05-4 DDR2-D30
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B04-1 1 8 33R DDR2-D31
3B28 10 9 7
DDR2-CLK_P DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B12 DDR2-DQS2_P DDR2-A11 K7
240R 12 11
DDR2-CLK_N DDR2-A13 L8 DQS A8 3B13 33R DDR2-DQS2_N DDR2-A12 L2 B7 3B14 DDR2-DQS3_P
13 12
2B44 DDR2-A13 L8 DQS A8 3B15 33R DDR2-DQS3_N
33R 13
DDR2-BA0 G2 RES 2p2 2B45
0 33R
DDR2-BA1 G3 A2 DDR2-BA0 G2 RES 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
RES 3B01 F9 DDR2-ODT
ODT
DDR2-CLK_P 240R E8 RES 3B03 F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM2 3B23 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM3 3B24 B3
33R VSS VSSQ DM|RDQS
VSSDL
33R VSS VSSQ

J1
K9

E7

A7
B2
B8
D2
D8
A3
E3
VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
+1V8
+1V8
DDR2-VREF-DDR

DDR2-VREF-DDR

2B26

2B38
100p
100n
2B42

2B18

2B19

2B20

2B21

2B22

2B23

2B24

2B25
100n

100n

100n

100n

100n

100n

100n

100n

2B39
47u

2B35

100p
100n
2B43

2B27

2B28

2B29

2B30

2B31

2B32

2B33

2B34
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B00
H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1

EDE1108AGBG-1J-F 7B01

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF

0 VDD VDDQ
DDR2-A1 H3 DDR2-A0 H8
DDR2-A2 H7
J2
1
2 SDRAM 0
C8
C23B08-4 4 5
2
3B07-2
7
33R
DDR2-D0 DDR2-A1 H3
H7
0
1 C8 2
3B10-2
7
DDR2-A3 3 1
33R
DDR2-D1 DDR2-A2 2 SDRAM 0 DDR2-D8
DDR2-A4 J8 D7 3 6 3B07-3 DDR2-D3 DDR2-A3 J2 C2
3B11-3 3 6 33R DDR2-D14
4 2 3 1
DDR2-A5 J3 D3 3B08-2 2 7 33R DDR2-D2 DDR2-A4 J8 3B10-3 33R 3
D7 6 33R DDR2-D10
5 3 4 2
DDR2-A6 J7 DQ D1 33R 1 8 3B08-1 DDR2-D4 DDR2-A5 J3 D3 2 7 3B11-2 DDR2-D11
6 A 4 5 3
DDR2-A7 K2 D9 3B07-4 4 5 33R DDR2-D5 DDR2-A6 J7 DQ D1 1 8 33R DDR2-D12
7 5 6 A 4
DDR2-A8 K8 B1 33R 3 6 3B08-3 DDR2-D6 DDR2-A7 K2 D93B10-4 4 5 3B11-1 33R DDR2-D13
8 6 7 5
DDR2-A9 K3 B9 3B07-1 1 8 33R DDR2-D7 DDR2-A8 K8 B1 33R 4 5 3B11-4 DDR2-D9
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B10-1 1 8 33R DDR2-D15
10 9 7
DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B16 DDR2-DQS0_P DDR2-A11 K7
12 11
DDR2-A13 L8 DQS A8 3B17 33R DDR2-DQS0_N DDR2-A12 L2 B7 3B18 DDR2-DQS1_P
13 12
2B46 DDR2-A13 L8 DQS A8 3B19 33R DDR2-DQS1_N
+1V8 33R 13
DDR2-BA0 G2 RES 2p2 2B47
0 33R
DDR2-BA1 G3 A2 DDR2-BA0 G2 RES 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
RES 3B06 F9 DDR2-ODT
ODT
180R 1%

DDR2-CLK_P 240R E8 3B09 RES F9

ODT
3B20

DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8

DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
FB00 RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
DDR2-VREF-DDR CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM0 3B25 B3 DDR2-WE F3
DM|RDQS WE
180R 1%

DDR2-DQM1 3B26 B3
33R VSS VSSQ DM|RDQS
3B21

VSSDL
33R VSS VSSQ
B8
D2
D8
A3
E3
J1
K9

E7

A7
B2

VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
1X20 1X21 1X22 1X23 1X24
HOOK1 HOOK1 HOOK1 HOOK1 HOOK1

4 2012-04-23

DDR 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_038_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 101

10-3-9 PNX 85500: Power

PNX 85500: Power

B05A IS3Q 5S80

30R
+1V1 B05A

10u
2S5A
2S6A

100n
1
5S81
+2V5

2
30R

10u
2S6B

2S5B
100n
1
+1V8
IS3S 5S82

2S26

2S61
2S60

2S62

2S63

2S66

2S67

2S68
2S64

2S65
100u

100n
100n

100n

100n

100n

100n

100n
100n

100n
+3V3
30R

10u
2S5C

2S5D
100n
SENSE+1V1 c001
5S93
7S00-10

G6

G7
R6
R7
U7

C6
D6
A5
A6
B5
B6

E6
F6

F7
L6
L7
PNX85500 +2V5
30R

2S6R 2

220u 6.3V
VDD_1V8

2S4M
2S6D

100n
100n
+1V1 AF1 V20

7
AE2 HDMI_VDDA_1V1 V21

5
AD3

1
2S5G-1

2S5G-2

2S5G-3

2S5G-4

2S5H-1

2S5H-2

2S5H-3

2S5H-4
2S4Q

2S4R
2S28
2S43

2S27

2S23
100n

100n
100n

100n

100n

100n

100n

100n

100n

100n

100n

100u
AC4 VDD U20

22u

22u

1
AB5 HDMI_VDDA_2V5 U21
H20

4
F11 U22 +2V5-LVDS

2
HDMI_VDDA_3V3_TERM
G11
F13 N6

2S4N

2S4P
100n
G13 VDD_2V5 N7

10u
F15

8
8

5
G15 C7

2S5K-1

2S5K-2

2S5K-3

2S5K-4

2S5J-3

2S5J-1

2S5J-2

2S5J-4
100n

100n

100n

100n

100n

100n

100n

100n
F17 C9

220u 2V0
2S29
G17 C11
5S85
F19 VDD_2V5_LVDS C14

4
+3V3

2
2

1 2S6G 2
G19 C16

1
30R

2S6N

2S6C

2S6P
2S6F

100n

100n

100n
100n
J9 C18

10u
J11
AA16
AA8
Y11
Y14

J13 W20
Y16
Y9

7S00-12

1
1
PNX85500 J15 P20
J17 M20
VSSA
A1 M7 L9 VDD_3V3 K20
+3V3-STANDBY
A10 N2 L11 V7

2S4U
2S4V

100n
A12 N20 L13 Y8

10u
A15 P10 L15
VDD_1V1
A17 P12 L17 Y19
A19 P14 N9 VDD_3V3_SBY Y18
A26 VSS P16 N11 IS3K 5S83
A3 P18 N13 B13
VDDA_1V1_LVDS_PLL +1V1
A8 P4 N15
IS3L 30R

2S4W
2S4Y

100n
B1 P6 N17 AA15

1u0
B20 P7 R9 Y15
VDDA_1V2
C20 T10 R11 AA13
C4 T12 R13
5S95 +2V5
D2 VSS T14 R15 Y12
VSS VDDA_2V5 5S84
D20 T16 R17
30R

6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R

2S4Z
2S51

2S52

2S50
100n
100n
E20 T2 U11

10u
E4 T6 U13 AA7 c000 SENSE+1V2

10u
VDDA_2V5_ADAC
F10 T7 U15
F12 U4 U17 Y17
VDDA_2V5_DCS
F14 V10 J6
F16 V12 AA6 D13
VDDA_2V5_LVDS_BG
F18 V14 Y7
F20 V16 W7 T20

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG
VDDA_2V5_USB
F8 V18 F9
G10 V2 G9 Y13
VDDA_2V5_VADC +2V5-AUDIO
G12 Y20

HDMI_AGND
5S94

2S46

100n
J7 Y10

VSSA_USB
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC
30R
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

R21
VDDA_3V3_USB
2S4S

2S5P

2S21
100n
10u

1u0

U24
V24

A13

C13

R20
1

+2V5-AUDIO

2S45

100n
5S87
+2V5
30R

2S55

2S56
100n

1u0
5S88
+2V5-LVDS
30R

2S5M

2S57
100n

10u
5S89
+2V5

2
30R

2S6H

2S6K
100n

100n
2S58

10u
1

1
5S90
+2V5
30R

2S4T

2S53
100n

10u
2SHW

100n
IS58 5S92
+3V3

2
30R

2S6M

2S6L

2S59
100n

100n

1u0
1

1
4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Power

19220_039_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 102

10-3-10 PNX 85500: Standby controller

PNX 85500: Standby controller

B05B B05B

+1V1
IS3B

5S04
RES

30R

2S13

2S10

100n
1u0
2S37

1u0

2S11 IS20

100n

POL
DS50 2S4G
3
1 10p

AC17
AA17

AF26
2

1S02

54M
7S00-9
PNX85500 4
2S4F
1

VDDA_1V1_DCS

VDDA_ADC2V5

VDD_XTAL
+3V3-STANDBY 2S4D AE17 +3V3-STANDBY
3S1B XTAL_IN 10p
1n0 RC RC AD19
3S1C 0
RES 10K TACHO TACHO AE19 AF17
1 XTAL_OUT
10K 3S1D CEC-HDMI CEC-HDMI AF19
2 P1
3S1A RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20 AA26 RESET-STBYn
3 RESET_IN
10K 3S1F SDM SDM AB20 IS3F
7 3S44
+3V3-STANDBY 10K STANDBY EA
AB24 EA EA
3S3L RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3G 10K 3S43
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
1 ALE
10K 3S3N RES BL-ON BL-ON AE20
2 IS3D 10K
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN 10K 3S42
3 PSEN
10K 3S3Q RES CTRL-DISP1 CTRL-DISP1 AA21 P2
4 RES 3S6V
RES 3S3S 10K CTRL-DISP2 CTRL-DISP2 AB21 AC23 3S2F 100R SDA-UP-MIPS SDA-UP-MIPS
5 SDA
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
6 SCL
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21 4K7 RES
7 LED1 RES 3S1P
+3V3-STANDBY 10K AD26 3S2H 100R LED1
3S1G 0
RXD-UP RXD-UP AE21 PWM AC25 3S2K 100R LED2 LED2 10K 3S41
0 1
3S1H 10K TXD-UP TXD-UP AF21
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO
3S2A 2 SDO
DETECT2 AB22 P3 AF25 PNX-SPI-SDI
3 SDI
AC22 SPI AF24 PNX-SPI-CLK
10K 4 CLK
RES AD22 AF23 PNX-SPI-CSBn
5 CSB
3S1K FS0Y
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 3S4A 100R CTRL-DISP3 CTRL-DISP3 RES 3S2L 10K
0 0
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS RES 3S46 10K
10K 1 1
RES AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J 2 2 +3V3-STANDBY
KEYBOARD KEYBOARD AE24 AE18 RESET-ETHERNETn RESET-ETHERNETn RES 3S47 10K
3 3
LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC RES 3S2S 10K
100K 2S4C 4
RES AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP RES 3S2M 10K
4 5

VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 3S49 10K
7

AD17
3S1L
SPI-PROG SPI-PROG
10K PNX-SPI-WPn

+3V3-STANDBY

3S2V

10K
3
2S4K

100n

7S20
NCP803
VCC
FS0Z
2 RESET-STBYn
RESET

RES 2S4L
GND

1n0
1

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Standby controller

19220_040_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 103

10-3-11 PNX 85500: MIPS

PNX 85500: MIPS

B05C B05C
+3V3
* 3D ACTIVE 7S00-3
PNX85500
CONTROL C25 1
3S56
2
3S69
IS05 SDA-UP-MIPS SDA-UP-MIPS
3S45 SDA 2 3S57
BOOTMODE 1 C26 100R 1 SCL-UP-MIPS SCL-UP-MIPS 3S6A 4K7 4K7
+3V3 SCL
100R
10K 3S58
BOOTMODE Y21 B26 1 2 SDA-SET SDA-SET 3S6B 2K2
GPIO_0
+3V3 * 3S40 FS54 3D-LR 3D-LR
RXD1-MIPS
IS17
* 9S09 IS16 Y22
Y23
GPIO_1
2
SDA
SCL
A25 100R 1
100R
2 3S5W SCL-SET SCL-SET 3S6C 2K2
10K GPIO_2 3S5Y
TXD1-MIPS Y24 B25 1 2 SDA-SSB-550 SDA-SSB-550 3S6D 2K2
3S82 GPIO_3 SDA
BL-I-CTRL-PNX RXD2-MIPS W21 3 A24 100R 1 2 3S5Z SCL-SSB-550 SCL-SSB-550 3S6L 2K2
+3V3 GPIO_4 SCL
TXD2-MIPS W22 100R
10K GPIO_5 3S60
3S80 FS10 TXD2-MIPS GPIO6 W23 B24 1 2 SDA-TUNER SDA-TUNER 3S6F 2K2
+3V3 GPIO_6 SDA
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 2K2
+3V3 GPIO_7 SCL
10K BL-I-CTRL-PNX V23 100R
RES 3S21 IS04 GPIO_10
GPIO6 SELECT-SAW U23 AA25 EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K
+3V3 GPIO_11
TRSTN
10K AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K
TMS +3V3-STANDBY
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
RES 3S62 PNX-SPI-CS-BLn DN TCK
USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
+3V3 DP USB TDO
IS4Z R24 AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4
10K RREF TDI
10K
3S00 RES
AE4 RESET-SYSTEMn
RESET_SYS 1F10

3S55

5K6
RES 3S64 33R FS44
SELECT-SAW AD5 BL-DIM EJTAG-TRSTn-PNX85500
+3V3 BL_PWM 1
FS64 EJTAG-TMS-PNX85500 FS49
10K 2
AC5 SDA-SSB-550 cS51 SDA-FE EJTAG-TDO-PNX85500 FS50
CLK_54_OUT 3 FOR FACTORY

3S26

3S27
RES 3S6J
cS52

10K

10K

10K
SCL-SSB-550 SCL-FE EJTAG-TCK-PNX85500 FS51
4
RESET-SYSTEMn cS53 RESET-FUSION-OUTn EJTAG-TDI-PNX85500 FS52
5 USE ONLY
3S83 6
RXD1-MIPS EJTAG-DETECTn FS53
+3V3 7
10K 3D-VS 8
+3V3 +3V3 10 9
3S84 3S72
+3V3 TXD1-MIPS BL-DIM
10K 100R

FS57 +3V3
BM08B-SRSS-TBT

RES

+3V3

RES
2S89

100n +3V3
RES

3
7S01
PCA9540B
VDD SC0 5 SCL-DISP SCL-DISP RES 3S65 4K7

SC1 8 SCL-BL SCL-BL RES 3S66 4K7

SCL-SET 1 SCL SD0 4 SDA-DISP SDA-DISP RES 3S67 4K7

I 2 C
INP
-BUS
SDA-SET 2 SDA FIL
CTRL SD1 7 SDA-BL SDA-BL RES 3S68 4K7

VSS

6
FS31

9S10 RES SCL-BL

IS08
SCL-SET 9S11 FS2W SCL-DISP

9S12 FS2Y SDA-DISP

IS09
7S00-4 SDA-SET 9S13 RES SDA-BL
PNX85500

+3V3
ETH-RXCLK AA3
RXCLK ETHERNET
ETH-RXD(0) Y5
0
ETH-RXD(1) Y6 AA2 ETH-TXCLK
IS50 1 TXCLK
3S85-3 3 6 47K SDIO-CMD ETH-RXD(2) AB4 RXD ETH
2
3S85-2 2 7 47K SDIO-DAT0 ETH-RXD(3) AC1 AA1 ETH-TXD(0)
3 0
3S86-2 2 7 47K SDIO-WP AA4 ETH-TXD(1)
1
3S85-4 4 5 47K SDIO-DAT2 ETH-RXDV AC2 TXD AB1 ETH-TXD(2)
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3)
RXER 3
3S86-4 4 5 47K SDIO-DAT3 ETH AA5 ETH-TXEN
TXEN
3S85-1 1 8 47K SDIO-DAT1 SDIO-DAT3 W2 AB3 ETH-TXER
CC_DAT3 TXER
3S86-3 3 6 47K SDIO-CDn SDIO-CLK W1 AC3 ETH-COL
CLK COL
3S86-1 1 8 47K SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC
0 MDC
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
RES 3S87 1 DAT MDIO
SDIO-CLK SDIO-DAT2 W3
2
47K SDIO-CDn U6
SDCD
SDIO-WP V6
SDWP

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

MIPS

19220_041_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 104

10-3-12 PNX 85500: Control

PNX 85500: Control

B05D B05D
+3V3-STANDBY +3V3-STANDBY

+3V3-STANDBY
+3V3 +3V3 +3V3

RES
2F49

100p

100n
2F52

RES
3F66

10K
3F52

10K
8
7F52

RES 3F67
M25P05-AVMN6

10K
BL-I-CTRL
VCC
PNX-SPI-SDI 2
Q D
5 PNX-SPI-SDO 7F53 RES
PDTA114EU +5V
512K
6 PNX-SPI-CLK
FLASH C

3F68 RES
1 PNX-SPI-CSBn
S
IF54
3 IF55

47K
W PNX-SPI-WPn BL-I-CTRL-PNX
7F54-1 RES
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF28 FF29 7F54-2 RES IF56
VSS SPI-PROG BC847BPN(COL)
4 2
IF57 1
4

5
FF03 FF04
SDM
3

RES 3F53 FF58

10K

RES 2F53

RES 3F69

RES 3F54

1K0
1u0

10K
+3V3 MAIN NVM
DEBUG ONLY 9F51
RES
1F52
2F58 RES FF61 3F62 100R
SCL-SSB-550 1 SCL
FF62
100n 2
7F58 SDA-SSB-550 3 SDA
3F63
8

FF63 100R 4 5

10K

3F58 (8K 8) 7
WC
EEPROM 3F59 FF55
IF59 1 6 SCL-UP-MIPS
0 SCL
2 100R
1 ADR 3F60 FF56
3 5 SDA-UP-MIPS
2 SDA
100R
4

FF57

DEBUG / RS232 INTERFACE LEVEL

RES SHIFTED
1F51
FF65 3F64
TXD-UP 1
FF66 100R 3F65
FF64
2 FOR
RXD-UP 3
UP
RESET-STBYn 100R
SPI-PROG
4 DEBUG
5
7 6
USE ONLY

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Control

19220_042_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 105

10-3-13 PNX 85500: SDRAM

PNX 85500: SDRAM

B05E B05E

7S00-6
PNX85500

HDMIA-RX2+ T25 HDMI_DV

P
HDMIA-RX2- T26 RX0_A
N

HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A

HDMIA-RXC+ W25
P
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W
W24
RREF
12K
RES
2S2A

10u

7S00-8
PNX85500
DDR2-BA0 H1 MEMORY J1 DDR2-A0
0 0
DDR2-BA1 H2 J3 DDR2-A1
1 BA 1
DDR2-BA2 G1 K1 DDR2-A2
2 2
G4 DDR2-A3
3
DDR2-DQM0 D1
0 M0 4
L3 DDR2-A4
DDR2-DQM1 D5 G3 DDR2-A5
1 5
DDR2-DQM2 R3 DM L2 DDR2-A6
2 6
DDR2-DQM3 T5 H5 DDR2-A7
3 7
L1 DDR2-A8
A 8
DDR2-D0 F3 J5 DDR2-A9
0 9
DDR2-D1 C2 J2 DDR2-A10
1 10
DDR2-D3 F2 M3 DDR2-A11
+1V8 2 11
DDR2-D2 C3 J4 DDR2-A12
3 12
DDR2-D6 B4 M2 DDR2-A13
4 13
DDR2-D5 F1 K5 DDR2-A14
5 14
DDR2-D4 C1
6
DDR2-D7 E1 N5 3S30 DDR2-CLK_N
7 N
100u 2.0V
DDR2-D8 F4 CLK N4 10R 3S33 DDR2-CLK_P
180R 1%

180R 1%

8 P
3S20

3S06

2S12

DDR2-D9 B2 10R
9
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
DDR2-D11 C5 DQS0 E3 DDR2-DQS0_P
FS02 11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
B3 DQS1 D4 DDR2-DQS1_P
180R 1%

DDR2-D14 14 P
3S22

DDR2-D15 F5
15
U3 DQ R1 DDR2-DQS2_N
180R 1%

DDR2-D16 16 N
3S07

DDR2-D17 P2 DQS2 R2 DDR2-DQS2_P

17 P
DDR2-D19 U2
18
DDR2-D18 P3 T3 DDR2-DQS3_N
19 N
DDR2-D22 N1 DQS3 T4 DDR2-DQS3_P
20 P
DDR2-D23 U1
21
DDR2-D20 P1 K3 DDR2-CAS
22 CASB 3S6Q
DDR2-D21 T1 K4 DDR2-CKE DDR2-CKE
23 CKE
DDR2-D24 V4 L5 DDR2-CS
24 CSB 10K
DDR2-D30 R5 M4 DDR2-ODT
25 ODT
DDR2-D26 U5 M1
26 PCAL 3S6P
DDR2-D25 P5 M5 DDR2-RAS DDR2-ODT
27 RASB
DDR2-D28 N3 H3 DDR2-WE
28 WEB 10K
DDR2-D31 V3
29 RES
DDR2-D27 R4 A2 DDR2-VREF-CTRL2
30 1
DDR2-D29 V5 VREF V1 DDR2-VREF-CTRL3
31 2

IS42

2S20

2S17

1%
2S24

2S25
100p

100n

100p
100n

3S0V

261R
4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

SDRAM

19220_043_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 106

10-3-14 PNX 85500: Nandflash - conditional access

PNX 85500: Nandflash - conditional access

B05F +3V3
B05F

Non CI
* 3S1W
10K
7S00-5
PNX85500

FLASH D25 XIO-D00

00
D26 XIO-D01
01
C24 XIO-D02
02
D23 XIO-D03
03
NAND-ALE D22 C23 XIO-D04
ALE 04
NAND-CLE C21 NAND B23 XIO-D05
CLE 05
A22 XIO-D06
06
XIO-A00 J25 E22 XIO-D07
00 07
XIO-A01 J26 XIO_D F24 XIO-D08
01 08
XIO-A02 H21 F25 XIO-D09
02 09
XIO-A03 H22 F26 XIO-D10
03 10
XIO-A04 H23 E23 XIO-D11
04 11
XIO-A05 H24 E24
05 12 IS26 3S15
XIO-A06 H25 E25 INPACK INPACK
06 13
XIO-A07 H26 E26 XIO-D14 10K
07 14
XIO-A08 G21 XIO_A D24 XIO-D15
08 15
XIO-A09 G22
09
XIO-A10 G23 B22 XIO-OEn
10 OE_
XIO-A11 G24 XIO C22 XIO-WEn
11 WE_
XIO-A12 G25
12
XIO-A13 G26 B21 +3V3
13 CLK_BURST
XIO-A14 F22
IS25 14
F23 E21 NAND-CE1n
15 CE1_
D21
CE2_
A20
NAND RDY2

3S1V

RES
F21

10K
RDY1 NAND-RDY1n
A21 9S08 +3V3
WP_ NAND-WPn

IS00

2S0A

2S0B
100n

100n
+3V3

Non CI
*3S1X
10K
7S00-11 7S0A

12

37
PNX85500 H27U4G8F2D

VIDEO_STREAM VCC
CA-MDI0 3S01-1 8 1 P21 N26 CA-MDO0
0 0
CA-MDI1 33R 7 3S01-2 2 P22 M21 CA-MDO1 XIO-D00 3S0A-1 1 8 100R 29 1
1 1 0
CA-MDI2 3S01-3 6 3 33R P23 M22 CA-MDO2 XIO-D01 3S0A-2 2 7 100R 30 2
2 2 1
CA-MDI3 33R 5 3S02-4 4 P24 M23 CA-MDO3 XIO-D02 3S0A-3 3 6 100R 31 3
3 3 2
CA-MDI4 7 3S02-2 2 33R P25 MDI MDO M24 CA-MDO4 XIO-D03 3S0A-4 4 5 100R 32 4
4 4 3 IO
CA-MDI5 33R 8 3S02-1 1 P26 M25 CA-MDO5 XIO-D04 3S0B-1 1 8 100R 41 5
5 5 4
CA-MDI6 6 3 33R N21 M26 CA-MDO6 XIO-D05 3S0B-2 2 7 100R 42 10
6 6 5
CA-MDI7 3S02-3 33R 5 3S01-4 4 N22 L21 CA-MDO7 XIO-D06 3S0B-3 3 6 100R 43 11
7 7 6
33R XIO-D07 3S0B-4 4 5 100R 44 14
IS0A 7
CA-ADDENn J22 NAND-CE1n 15
ADD_EN
NAND-CLE 3S0C-2 2 7 100R 16 20
CLE
CA-DATADIR K25 K23 CA-VS1n NAND-ALE 3S0C-3 3 6 100R 17 21
DATA_DIR 1 ALE
VS K24 9S00 CA-MOCLK +3V3 3S0D 10K 9 22
2 CE_
CA-DATAENn K26 XIO-OEn 3S0C-1 1 8 100R 8 23
DATA_EN RE
K21 CA-CD1n XIO-WEn 3S0C-4 4 5 100R 18 24
3S03 1 IS0B WE
CA-MICLK N23 CD K22 CA-CD2n NAND-WPn 19 NC 25
I 2 WP
10R 6 26
MCLK SE
CA-MOCLK L25
O CA +3V3 3S0F 7
R
27
+3V3 28
2K2 B
N24 NAND-RDY1n 33
MISTRT
3S31 IS0C 34
CA-MIVAL N25 TS-CHDEC-DATA 3S1R 560R 35
MIVAL

3S0G
38

10K
33R
CA-MOSTRT L22 TS-CHDEC-CLK 3S1S 560R 39
MOSTRT
40
CA-MOVAL L23
MOVAL TS-CHDEC-VALID 3S1T 560R
* Non DVBS / T2 / LATAM 45
46
J21 TS-CHDEC-SOP 3S1U 560R
* Non DVBS / T2 / LATAM 47

+3V3
OOB_EN
48
CA-RDY L24
RDY
470R VSS
CA-RST L26
RST DATA
T21 TS-CHDEC-DATA TS-CHDEC-DATA 3S23
* DVBS
DVBS / T2 / LATAM

13

36
T23 TS-FE-ERR

CA-MISTRT
RES
9S01
J23
VCCEN
ERR
TNR_SER1 MICLK
T22
R23
TS-CHDEC-CLK
TS-CHDEC-VALID
TS-CHDEC-CLK 3S24
470R
* / T2 / LATAM
MIVAL
J24 R22 TS-CHDEC-SOP TS-CHDEC-VALID RES 3S28 470R
VPPEN SOP
+3V3
TS-CHDEC-SOP RES 3S29 470R
3S04
2S09

100n
33R

7S02
5

1
4
2

3
74LVC1G08GW

4 2012-04-23
PNX 85500 3 2011-12-12

Nandflash 3139 123 6533 2 2011-05-25

conditional access
19220_044_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 107

10-3-15 PNX 85500: Common interface

PNX 85500: Common interface

B05G +3V3
CA-RST
3F06
100K
B05G
3F01 2F00
+5V +5VCA TRANSPORT STREAM FROM CAM RES
3F07-4
+T 7F00 CA-CD1n 4 5
0R3 100n

20
74LVC245A 10K

22u 16V
3F07-2

2F01
1 CA-CD2n 2 7
3EN1
10K
3EN2 3F07-3
19 CA-DATAENn 3 6
G3 +3V3
10K
3F02 3F07-1
CA-MOCLK 2 18 MOCLK CA-DATADIR 1 8
1
100R 10K
3F03-1 2
CA-MOVAL 1 8 3 17 MOVAL
CA-MOSTRT 3F03-2 2 7 100R 4 16 MOSTRT CA-ADDENn 1 3F08-1 8
5 15 10K
100R 3F08-2
6 14 MOCLK 2 7
7 13 10K
3F08-3
8 12 MOVAL 3 6
9 11 10K
MOSTRT 4 3F08-4 5

10
10K
3F09-1
MDO0 1 8
+3V3 10K
3F09-2
MDO1 2 7
2F02
RES 10K
3F09-3
7F01 MDO2 3 6
100n

20
74LVC245A 10K
3F09-4 IF04
1 MDO3 4 5
3EN1
10K
3EN2
19
G3 3F10-1
IF05 MDO4 1 8
CA-MDO0 3F04-1 1 8 100R 2 18 MDO0 10K
1 3F10-2
IF06 MDO5 2 7
2
CA-MDO1 3F04-2 2 7 100R 3 17 MDO1 10K
CA-MDO2 3F04-3 3 6 100R 4 16 MDO2 MDO6 3 3F10-3 6
CA-MDO3 3F04-4 4 5 100R 5 15 MDO3 10K
3F10-4
CA-MDO4 3F05-1 1 8 100R 6 14 MDO4 MDO7 4 5
CA-MDO5 3F05-2 2 7 100R 7 13 MDO5 10K
CA-MDO6 3F05-3 3 6 100R 8 12 MDO6
CA-MDO7 3F05-4 4 5 100R 9 11 MDO7
3F12 +3V3
IF07 CA-RDY +3V3

10
10K
3F11-2
CA-WAITn 2 7
10K
3F11-3 IF08
+3V3 CA-INPACKn 3 6
+5VCA

RES 3F14
RES 3F13

10K
10K
10K
2F03 3F11-4
15-BIT ADDRESS RES CA-WP 4 5
7F02 10K
100n 3F11-1

20
74LVC245A CA-VS1n 8 1
+3V3
1 10K 1P00
3EN1
3EN2 1
19 CA-ADDENn CA-D03
G3 2
CA-D04
3
XIO-A00 18 2 CA-A00 CA-D05
1 4
2 CA-D06 5
XIO-A01 17 3 CA-A01 CA-D07
6
XIO-A02 16 4 CA-A02 CA-CE1n 7
XIO-A03 15 5 CA-A03 CA-A10 8
XIO-A04 14 6 CA-A04 CA-OEn
9
XIO-A05 13 7 CA-A05 CA-A11 10
XIO-A06 12 8 CA-A06 CA-A09 11
XIO-A07 11 9 CA-A07 CA-A08 12
CA-A13 13

10
CA-A14 14
CA-WEn 15
CA-RDY 16
+3V3
+5VCA 17
2F04 18
RES CA-MIVAL 19
7F03 CA-MICLK
100n 20

20
74LVC245A CA-A12 21
1 CA-A07
3EN1 22
3EN2 CA-A06 23
19 CA-ADDENn CA-A05
G3 24
CA-A04
25
XIO-A08 18 2 CA-A08 CA-A03
1 26
2 CA-A02 27
XIO-A09 17 3 CA-A09 CA-A01
28
XIO-A10 16 4 CA-A10 CA-A00 29
XIO-A11 15 5 CA-A11 CA-D00 30
XIO-A12 14 6 CA-A12 CA-D01
31
XIO-A13 13 7 CA-A13 CA-D02 32
XIO-A14 12 8 CA-A14 CA-WP 33
11 9
34
35

10
CA-CD1n 36
MDO3 37
MDO4 38
+3V3 MDO5 39
2F05 MDO6 40
8-BIT DATA RES MDO7 41
100n CA-CE2n 42
7F04
20
CA-VS1n 43
74LVC245A
1 CA-DATADIR CA-IORDn
3EN1 44
3EN2 CA-IOWRn 45
19 CA-DATAENn CA-MISTRT
G3 46
CA-MDI0
47
XIO-D00 18 2 CA-D00 CA-MDI1
1 48
2 CA-MDI2 49
XIO-D01 17 3 CA-D01 CA-MDI3
50
XIO-D02 16 4 CA-D02 +5VCA 51
XIO-D03 15 5 CA-D03 52
XIO-D04 14 6 CA-D04 CA-MDI4
53
XIO-D05 13 7 CA-D05 CA-MDI5 54
XIO-D06 12 8 CA-D06 CA-MDI6 55
XIO-D07 11 9 CA-D07 CA-MDI7 56
MOCLK 57
10

CA-RST 58
CA-WAITn 59
CA-INPACKn 60
+3V3 CA-REGn 61
2F06 MOVAL 62
CONTROL MOSTRT 63
7F05 MDO0
100n 64
20

74LVC245A MDO1 65
1 MDO2
3EN1 66
3EN2 CA-CD2n 67
19 CA-ADDENn 68
1X01 1X02 1X06 1X05 1X04 G3
REF EMC HOLE REF EMC HOLE REF EMC HOLE REF EMC HOLE EMC HOLE 71 69
XIO-D11 18 2 CA-REGn 72 70
1
2
XIO-D09 17 3 CA-CE1n MPC-20-5V-PBT-BRF-V0
XIO-D08 16 4 CA-CE2n
XIO-OEn 15 5 CA-OEn
XIO-WEn 14 6 CA-WEn
XIO-D14 13 7 CA-IORDn
XIO-D15 12 8 CA-IOWRn
CA-WAITn 11 9 XIO-D10 4 2012-04-23

PNX 85500 3 2011-12-12

10

3139 123 6533 2 2011-05-25

Common interface

19220_045_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 108

10-3-16 PNX 85500: Audio

PNX 85500: Audio

B05H 3S53-1 +2V5-AUDIO
B05H
100R +3V3
3S53-2
7S08
100R LD3985M25
1 IS1H 1 3S16-1 8
3S12-1 2S2W 3S53-3 FS08
AUDIO-IN1-L 8 10K 5 1
OUT IN
22K 1u0 100R IS12 IS13

10u RES
4 3 4S14
3S16-2 3S53-4 BP INH +2V5

2S2R

2S2S
2 7

10u
2 3S12-2 IS1J 2S2V

1u0 RES
AUDIO-IN1-R 7 10K 100R COM

2S2T

100n
22K 1u0

2S34
2
IS1M

100u 4V
3S51

2S42

2S41
4R7

1u0
3S17-4
IS0R 4 5 7S00-2
3S13-4 2S31
AUDIO-IN3-L 10K PNX85500
4 5 2S36
22K 1u0 AUDIO
3 AE10 AC7
L P
3S17-3 6 AF10 AIN1 ADACL AB7
3S13-3 IS1R 2S30 R N 1u0
AUDIO-IN3-R 3 6 10K
AD10 AC6
22K 1u0 L P
AC10 AIN2 ADACR AB6
3S17-1 R N
3S13-1 IS1P 1 8 2S33
AUDIO-IN4-L 10K AE9 AD7
L 1
1 8 AF9 AIN3 AE7
22K 1u0 R 2
AF7 3S34 33R ADAC(3)
2 3
IS1Q 3S17-2 7 AD9 ADAC AD6 3S35 33R ADAC(4)
3S13-2 2S32 L 4
AUDIO-IN4-R 2 10K AC9 AIN4 AE6
7 R 5
AF6
22K 1u0 6
AF8
L
AE8 AIN5 AD4 3S36 10R SCKI2SOUT
R OSCLK
3S10 AD1 3S37 10R I2SCLK
I2S_OUT SCK
2S2L 100R AB9 AD2 3S38 10R WSI2SOUT
POS WS
IS1B AB8 VR_AADC
1u0 NEG
IS19 AE1 3S39 10R SDI2SOUT1
1
AD8 AF2
VREF_AADC 2
AE3
IS1A I2S_OUT_SD 3
AC8 AF3
VCOM_AADC 4
3S3F
AF5
SPDIF_OUT
56R

3S32

2S35

2S38
DBS8 AE5

10K

1n0

1n0
SPDIF_IN1
2S3G
2S3N

2S3H
2S3F

100n

100n
10u

10u

9S06
RES +3V3
+3V3-ARC

3S11 IS1L
1R0

2S3Q

100n
7S09-1
3S6N

14
74LVC00APW SPDIF-OPT
SPDIF-OUT-PNX SPDIF-OUT-PNX 1 & 47R
3
2
+3V3
+3V3 7

+3V3-ARC
3S19

+3V3-ARC
10K

7S09-2
14

74LVC00APW 7S09-3

14
4 & 74LVC00APW
6 9 & 2S3L IS1K 2S3M IS44
IS1C 180R
SEL-HDMI-ARC 5 8 eHDMI+
10 3S6M
+3V3 100n 100n
7

3S25

68R
+3V3-ARC

7S09-4
14

74LVC00APW
12 &
11
13
+3V3
7

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Audio

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div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 109

10-3-17 PNX 85500: Headphone

PNX 85500: Headphone

B05I B05I

+3V3-STANDBY

4 7NN2-2
6 PUMD12
5
RESET-AUDIO 2 7NN2-1 RESET-HP
PUMD12 3
1

2NN0

47p
3NN1-2
4 3NN1-4 5 2 7
22K 22K

3NN1-3
3NN1-1
1 8 3 6
22K 22K
2NN5

47p +3V3

2NN1

100n
7NN1
TS489IST AMP1
3 3NN2-3 6

CDS4C12GTA
8

8
VDD

3NN5-1
33R

1NN8

6NN8

2NN8
1K0

12V

22n
2NN6 FNN1
ADAC(3) 2NN3 1u0 3NN0-1 1 8 10K 2 AMPLIFIER 1
INN7
4 3NN2-4 5 AMP1
1 1 1NN2

RES
1
IN- 4V 100u 33R MSJ-035-12D-B-AG-PBT-BRF
ADAC(4) 2NN4 1u0 3NN0-2 2 7 10K 6
2 VO
2NN7 FNN2 2
INN5 INN8 3NN2-2
RESET-HP 3NN0-4 4 5 10K 5 7 2 7 AMP2 AMP2 3
SHUTDOWN 2
1

CDS4C12GTA
2NN2 INN6 4V 100u 33R

5
3

3NN5-4
BYPASS
1 3NN2-1 8

1NN9

6NN9

2NN9
1K0

12V

22n
1u0
RES 3NN6

GND
22K

33R FNN7
4

RES
4
4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Headphone

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 110

10-3-18 PNX 85500: Video out - LVDS

PNX 85500: Video out - LVDS

B05J B05J

7S00-7
PNX85500

PX1A- A7 LVDS D7 PX3A-

N N
PX1A+ B7 A A E7 PX3A+
P P

PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P

PX1CLK- 3S91 22R C10 E10 3S95 22R PX3CLK-

N N
PX1CLK+ 3S92 22R B10 CLK CLK D10 3S96 22R PX3CLK+
P P

PX1C- A9 LOUT1 LOUT3 D9 PX3C-

N N
PX1C+ B9 C C E9 PX3C+
P P

PX1D- A11 D11 PX3D-

N N
PX1D+ B11 D D E11 PX3D+
P P

PX1E- C12 E12 PX3E-

N N
PX1E+ B12 E E D12 PX3E+
P P

PX2A- A14 D14 PX4A-

N N
PX2A+ B14 A A E14 PX4A+
P P

PX2B- C15 E15 PX4B-

N N
PX2B+ B15 B B D15 PX4B+
P P

PX2CLK- 3S93 22R C17 E17 3S97 22R PX4CLK-

N N
PX2CLK+ 3S94 22R B17 CLK CLK D17 3S98 22R PX4CLK+
P P
LOUT2 LOUT4
PX2C- A16 D16 PX4C-
N
PX2C+ B16 N C E16 PX4C+
C P
P
PX2D- A18 D18 PX4D-
N
PX2D+ B18 N D E18 PX4D+
D P
P
PX2E- C19 E19 PX4E-
N
PX2E+ B19 N E D19 PX4E+
E P
P

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Video out - LVDS

19220_048_120228.eps
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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 111

10-3-19 PNX 85500: Analog video

PNX 85500: Analog video

B05K B05K
AV1-CVBS 2S87

22n 2S8A Y-SVHS

3S59

47R
Connectivity 22n

3S5B
47R
AV1-R 2S7J

22n 2S22 C-SVHS

3S4J

56R
22n

3S05

56R
EU: SCART1 CVBS-MON-OUT1
AV1-B 2S7K
AP: -

3S5F

560R
22n

3S4L

56R
IS4V

560R
2S40

3S08
47p
2S7H
AV1-G
22n

3S4K

56R
IS4W

3S09

8K2
2S7M
YPBPR1-SYNCIN1
10n
2S7L
AV3-Y
22n

3S4P

56R
2S7N
AV3-PR
YPBPR1 22n

3S4R
EU:

56R
7S00-1
AP: YPBPR1 PNX85500
2S7P ANALOG_VIDEO
AV3-PB
AB15 AC12
22n CVBS_Y1 ATV_CVBS_Y3

3S4T

2S19

2S18

2S16

2S15

2S14
AC13

56R
AF13

22n

22n

22n

22n

22n
R C3
AD13
B AV1
AE13 AD11
G CVBS_Y7
AC11
C7
AF15
SYNCIN1 FS13
AE15 AF11
Y_G1 CVBS1_OUT
AC15 AE11
PR_R_C1 CVBS2_OUT
AD15
PB_B1
AB10
RESREF
AB14 AA11 IS5E 3S5S
CVBS_Y2 CURREF
AF14 10K
SYNCIN2
AE14 AC16 IS5D
Y_G2 1
AC14 AB16 IS5F
PR_R_C2 2
AD14 AB13 IS5G
PB_B2 3
REF AB12 IS5H
4
AF16 AA12 IS5J
R 5 3S75
AD16 AA10 SOC-IF-AGC
G VGA 6
AE16
B 10K

2S75
AB18 AD12 FS15

10n
HSYNC_IN IF_AGC
AC18 AB11
IN RF_AGC
AF4 VSYNC
OUT
AD24 AE12
SCL VGA_EDID P
AD25 TUNER N AF12 BS10
SDA

AGND

AA14
2S77 3S4V
SOC-IF-P
10n 100R

3S4U

680R
2S78 3S4W
SOC-IF-N
10n 100R

2S84
R-VGA
22n
3S50

56R

2S85
G-VGA
22n
3S52

56R

2S86
B-VGA
22n
3S54

56R

EU: VGA

7
3S5V-4

3S5V-2
3S5T-4

3S5T-2
AP: VGA

100R

100R

100R

100R
3S5T-1
H-SYNC-VGA 1 8

2
100R
3S5T-3
V-SYNC-VGA 3 6
100R

RES 3S5V-3
VGA-SCL-EDID 3 6
100R
RES 3S5V-1 4 2012-04-23
VGA-SDA-EDID 1 8
100R PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Analog video

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 112

10-3-20 PNX 85500: Analogue externals A

PNX 85500: Analogue externals A

B05L B05L
FNA2 3N02 FN71
AUDIO-IN1-R
1K0

CDS4C12GTA
RES 6N03
2N06

1N31

2N88
100p

12V

1n0
AUDIO-IN1-L 3N03
FNA3 1K0

CDS4C12GTA
AV2-STATUS

1N54
2N04

6N09

2N91
IN05

100p

12V

1n0
+5V * EU

3N17

10K
RES
3N74 18R

3NA2

1R0
FNA4 5N73 FNA1 3N75
AV1-B 1VA1
1u8 49045-0011

CDS4C12GTA
18R IN90
25 26
2N79

1N12

2N15
2N80

RES 6N23
150p

100p
150p

12V
24
23 +3V3

2NB1

3NA1
9N01

3N06
100n

1K0

5K6
22
RES 21
FN73 20 IN89
19 IN13

3N73
FN74

4K7
IN18 3N31 18
AV1-STATUS FN75 17 IN61

2NB3

3N18
4

39K
2N99

1u0
CDS4C12GTA
12K 16 7N06-2
15 IN51
3N32

RES 6N22

1N55

2N18

100p
5
4K7

12V
14 4p7 AV2-BLK
6 7N06-1
13
3 BC847BPN(COL) IN70 5N80
12 2N81 IN59 CVBS-MON-OUT1
2
3N76 18R 11

18p
10 3NB1 IN60 2u2 10u

2N97

2N98
1

39p
9

3N19
BC847BPN(COL)

18K
FNA5 5N74 3N77 8 820R
AV1-G FN80
7

3NB3

330R
CDS4C12GTA

1u8 18R 6
2N83

2N84
150p

150p

5
1N18
RES 6N26

2N14

100p
12V

4
3
RES 2
1

3N78 FN85
+5V
18R
FNA6 5N76 3N79
AV1-R FN81
CDS4C12GTA

1u8 18R
2N86

2N74
2N85

150p

100n
150p

RES 6N28

1N19

2N12

100p
12V

IN96 3NB6-1 IN91

RES 1 8
470R
3NB6-2 IN92 3N45
2 7 7N05
BC847BW CVBS-OUT-SC1
+3V3
470R 68R

5
3NB6-4
3NB6-3

470R
3 6
3N44

2N24

100n
4K7

470R

4
RES
3N48
FNA7
AV1-BLK 3
68R
3N42 FN82
7N03 1
BC847BW
CDS4C12GTA

4K7
2
6N29
3N43

1N22

RES 2N75

100p
75R

12V

*
RES

FNA8 5N77 3N62

AV1-CVBS FN84
CDS4C12GTA

1u8 27R
2N45

RES 6N32

2N44

1N25
150p

150p
12V

CVBS-OUT-SC1 FN83
CDS4C12GTA
RES 6N30

1N23

RES 2N76

100p
12V

DEBUG
4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Analogue externals A

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 113

10-3-21 PNX 85500: Analogue externals B

PNX 85500: Analogue externals B

B05M FN48 3N90 FN5C
AV3-PR
B05M
18R

CDS4C12GTA
2N68

1N39

RES 6N52
100p

12V
YPBPR
1VA8 5
4
FN51 3N89 FN5B
3 AV3-PB

CDS4C12GTA
18R
2
FN42

2N67

1N28

RES 6N51
100p
1

12V
MSJ-035-75C-G-RF-PBT-BRF

FN54 3N87 FN5A

AV3-Y
18R

CDS4C12GTA
YPBPR1-SYNCIN1

2N27

RES 6N40
1N43
100p

12V
CVBS & AUDIO

1VA4 5
4
3N97 FN5D
3 AUDIO-IN3-R

CDS4C12GTA
FN50 1K0
2

2N39

1N29

RES 6N06

2N72

100p
1 FN43

12V
1n0
MSJ-035-75C-Y-RF-PBT-BRF

FN49 3N96 FN5G

AUDIO-IN3-L

CDS4C12GTA
1K0
2N40

1N42

2N71

100p
RES 6N38

12V
1n0

VGA ( OR DVI ) AUDIO

1N09 5
4 FN01
3N20 IN10
3 AUDIO-IN4-R

CDS4C12GTA
1K0
2
V_NOM

RES 6N20

2N38
1N38
2N37

100p
1

12V
1n0

MSJ-035-75C-BL-RF-PBT-BRF

FN02 3N21 IN09

AUDIO-IN4-L
CDS4C12GTA

1K0
V_NOM
2N36

1N37

RES 6N19

2N35

100p
12V
1n0

FN03

+3V3
3N9C

1R0

1N10
3150-831-030-H1 FN5H
2
VCC
FN55
1 SPDIF-OPT
VIN
3
GND
CDS4C12GTA

MT
V_NOM

5 4
2N73

1N80

RES 6N53
RES 2N77
100n

100p

12V

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Analogue externals B

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 114

10-3-22 PNX 85500: VGA

PNX 85500: VGA

B05N B05N

FFC1 3FC5
R-VGA

CDS4C12GTA
18R

RES 2FC1

1FC1

RES 6FC1
100p

12V
FFC2 3FC6
G-VGA

CDS4C12GTA
18R

RES 6FC2
RES 2FC2

1FC2
100p

12V
1N05
1
2
3FC7
3 B-VGA
4

CDS4C12GTA
FFC3 18R
5

RES 6FC3
RES 2FC3

1FC3
100p
6

12V
VGA 7
8
CONNECTOR 9 FFC4
10
11
FFC5
12 9FC5 H-SYNC-VGA
13
14

RES 6FC4

CDS4C12GTA
2FC4

1FC4

3FC3
15

12V
47p

4K7
17 16

FFC6
MDS-15P-V-11-B-8.2-U4-ZN-PBT-BRF

FFC7
9FC6 V-SYNC-VGA

CDS4C12GTA
RES 6FC5
2FC5

1FC5

3FC4
12V

4K7
47p
9FC1 VGA-SDA-EDID-HDMI
RES
3FC1 FFC8
9FC2 VGA-SDA-EDID
RES

CDS4C12GTA
10K

RES 6FC6
2FC6

12V
47p
9FC3 VGA-SCL-EDID-HDMI
RES
3FC2 FFC9
9FC4 VGA-SCL-EDID

CDS4C12GTA
RES
10K

2FC7

RES 6FC7

12V
47p

+5V-VGA

CDS4C12GTA
2FC8

1FC6

RES 6FC8

12V
47p

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

VGA

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 115

10-3-23 PNX 85500: Temperature sensor

PNX 85500: Temperature sensor

B05O B05O

+3V3

9USA RES

9USB RES
3USA
RES

1K0

3USG
2USA

100n

1K0
For DEV Use Only

LTST-C190KGKT
RES

8
7USA
LM75BDP

6USA

+VS
3 7 IUSA
OS A0

SDA-SSB-550 3USB 47R 1 6 IUSB

SDA A1

SCL-SSB-550 3USC 47R 2 5 IUSC

SCL A2

GND

3USD

9USC
RES
3USF
1K0

1K0
4

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Temperature sensor

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 116

10-3-24 PNX 85500: Vdisp-switch

PNX 85500: Vdisp-switch

B05P B05P

1 9UU0-1
RES *8
2 9UU0-2
RES *7
3 9UU0-3
RES *6
4 9UU0-4
RES *5
1 9UU1-1
RES *8
2 9UU1-2
RES *7
3 9UU1-3
RES *6 FUU0
4 9UU1-4
RES *5

7UU0
SI4835DDY 1UU0 FUU2
RES
7UU1 6
5 +VDISP
+12VD SI3441BDV T 2.0A 63V
2

RES 3UU8

2UU2

RES 2UU3
4 1

47R

22n

22u
6UU1
RES 3UU4
3UU3-2
7 2 2K2
RES LTST-C190KGKT
4

3
2UU4 47K
PUMD12 FOR DEVELOPMENT USE ONLY
3UU1 2UU1 RES 2UU5
5 7UU2-2
1n0
47R IUU1 1u0 220n
3 IUU3 7UU3 RES
IUU0 3UU6 3UU3-1
1 8 BC847BW
47K IUU2 47K RES
6 3 IUU4 3UU3-3 IUU5 3UU3-4

3UU7

RES 3UU9
1 6 3 4 5

47K

22K
3UU5 +3V3
+3V3-STANDBY * 2 7UU2-1
PUMD12 2
47K RES 47K RES
10K

2UU0

RES 100n
1

FUU1
VDISP-SWITCH
3UU2
+3V3
4K7 RES

LCD-PWR-ONn 9UU2

LCD-PWR-ON-FPGAn
* 9UU3 3
RES
3
RES
DONE-LX25 1 7UU4 1 7UU5
PDTC114EU PDTC114EU
2 2

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Vdisp-switch

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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 117

10-3-25 Class-D amplifier

Class-D amplifier
B06A B06A
7D80
SI2304
FD34
+3V3-STANDBY +3V3-AUDIO

3D83 6D61 2D39

+12V-AUDIO
1K0 PDZ2.7B(COL) 1n0

3D84

10K
+12V-AUDIO +12V-AUDIO

47u 35V
47u 35V
2D60

2D61

5D50

2D64
2D57

5D51
220n

220n
30R

30R
5D84
+3V3D +3V3-AUDIO
ID54 ID55 30R

5D85 RES

2D5A
3D78

2D5C

3D80
100u 16V

100u 16V
+3V3

10K

10K
30R
* * * *

2D69
2D86

2D68

100n

100n
10u
SPEAKER-L- SPEAKER-R-
+3V3D

2D5B
3D79

2D5D

3D81
100u 16V

100u 16V
3D58

10K

10K
* * 1R0
3D57
ID78
ID77 7D60
* *
1R0 TAS5731PHP

13

27

34
35
+3V3D

2
3
AVDD

DVDD

PVDD_AB

PVDD_CD
WSI2SOUT FD67 20
LRCLK 5D70 5D00
9D52 SPEAKER-L+
3D50

9D53 21
10K

RESET-AUDIO I2SCLK SCLK 10u 30R

1 ID50
OUT_A
RES 9D54

3D73

2D56

2D71

2D78
RES

220n

220n
FD66 15

18R

10n
SCKI2SOUT MCLK
+3V3-STANDBY 4 ID81 2D79 33n
BST_A ID82 ID51
D-RESET SDI2SOUT1 FD50 22 43 2D80 33n
SDIN BST_B

ID92
6D60

7D50-2 SDA-SSB-550 3D55 47R 23 46

SDA OUT_B
3D54

3D74
PUMH2 3D56 47R 24
BAT54 COL

18R
47K

SCL-SSB-550 SCL FD92

2D75
ID52

330p
39 SPEAKER-L+
OUT_C
RES 3D76 15K 14
+3V3D A_SEL ID62

ID93
3D77 15K 42 2D82 33n
BST_C

2D99

2D98

2D70
ID87 ID56 ID63

RES
25 33 2D85 33n

10n

10n

10n
D-RESET RESET BST_D
1D01 1D02
Left+ FD30 1 RES 5D78

2D94

330p
19 36 SUB+ 1
+3V3D PDN OUT_D 5D74 RES 5D75 FD31
ID65 2D50 4n7 ID66 SPEAKER-L- SPEAKER-L- Left- 2 30R 2
DETECT2 7D50-1 2D51 47n 3D51 470R 11 16 ID84 3D71 18K2 1% 10u SPEAKER-R+ Right+ 3 SUB- 3
P OSC_RES 30R RES 5D72 FD95
PUMH2 3D52 470R 2D52 47n ID69 10 PLL_FLT FD32 Right- 4
M ID75

RES 2D73

5D81
2D53 4n7 32 2D67 1u0

30R
30R 2041145-3

10n
9D51 GVDD_OUT 5D71 FD33
2D5F

3D82

2D76
RES
8 2041145-4
10K
1n0

10n
PBTL
30R

2D87

1D52

1D50

1D51
2D54 2n2 ID70 6

10n
ID61 SSTIMER
5D76 5D01 SPEAKER-R-
26 5 SPEAKER-R+
STEST
7
10u 30R

1D53

1D55

1D56
1D54
AUDIO-MUTE-UP 7D61 12 40
VR_ANA

2D89

2D83

2D55

2D81
3D75

220n

220n

220n
RES
PDTC144EU 2D72 10u NC 41

18R

10n
2D74 100n ID79 18 44
VR_DIG
45
ID80

ID94
2D77 100n 31
VREG
50 60

2D95

330p
51 61
52 62
53 63
54 64
55 VIA VIA 65
5D79 RES 5D80
56 66 ID53 SPEAKER-R-
57 67
38 PGND_CD
48 PGND_AB

10u 30R
58 68
GND_HS
DVSSO

3D72

RES 2D91

5D83
59 69

18R

30R
10n
AGND

DVSS
AVSS

GND

ID95
30

47

37
28

17

29

49

CD00
5D77

2D88

330p
GND-PLL 30R

GND-PLL

+12V-AUDIO (5000 & 5500 series) +24V-AUDIO (4500 series)

2D57 100uF 16V (2022 031 00538) 47uF 35V (2020 031 00753)
2D60 100uF 16V (2022 031 00538) 47uF 35V (2020 031 00753)
3D83 1K0 (3198 031 01020) 6K8 (3198 031 06820)
6D61 BZX2V7 (3198 020 52780) BZX5V6 (3198 020 55680)

Speaker Configuration 1D02 2D70 2D87 2D98 2D55 2D71 2D83 5D71 5D77 2D56 2D73 2D76 2D89 2D91 2D99 5D75 5D80 5D72 5D78 5D81 5D83 2D5A 2D5B 2D5C 2D5D 3D78 3D79 3D81 3D81
Active 2.1 (with Virtual Ground) Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes
Active 2.1 ( E-cap in speaker) Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No Yes Yes No No No No No No No No
* Passive 2.1 Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No 4 2012-04-23
2.0 No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No
Class-D amplifier 3 2011-12-12

3139 123 6533 2 2011-05-25

* Current Configuration
19220_055_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 118

10-3-26 USB hub

USB hub
B06B B06B

100n
2FLA
+3V3 +3V3
USB1
1P08
+5V-USB1 1
USB1-DM FL36 2
USB1-DP FL37 3
4
FL32 5 6

2FL2 100n
100n

100n

100n
1u0

1u0
USB-16-PBT-B-30-CU1-BRF

2FL1
2FL4
2FL9
2FL5

2FL8

100n
1FL5
1 3

2FLB
12M
USB2
2FL6

2FL7
18p

18p

7FL5

27

14

21
CY7C65632-28LTXCT 1P07

5
9
VCC

VCC_A_1
VCC_A_2
VCC_A_3

VCC_D
+5V-USB2 1
IFL4 10 FL47 2
XIN USB2-DM
USB2-DP FL41 3
IFLG 11 4
XOUT
1 USB-DM FL42 5 6
D-
USB-WIFI-DDn 3 2 USB-DP
DD1- D+
USB-WIFI-DDp 4 USB-16-PBT-B-30-CU1-BRF
DD1+
+3V3 * 3FLK 10K 25
OVR1
RES

100n
USB3-DM 6 26 3FLL 10K +3V3
DD2- SDA
USB3-DP 7
DD2+
IFLH 24

2FLC
USB-OVR3 OVR2

USB2-DM 12 RES
USB3
DD3-
USB2-DP
IFLJ
13
20
DD3+ TEST|SCL
18 3FLN 10K
+5V-USB3
* *1 1P06
USB-OVR2 OVR3
USB3-DM FL44 2
USB1-DM 15 USB3-DP FL45 3
DD4-
USB1-DP 16 4
DD4+
IFLK 19 FL46 5 6
3FLF USB-OVR1 OVR4
+3V3 30
+3V3 VIA1
28 31 USB-01-PBT-B-30-CU2-BRF
10K VREG VIA2
RESET-USBn IFLA 17 32
RESET VIA3
+3V3 3FLD 10K 22 33
SELFPWR VIA4
3FLB 100K 23

GND_HS
GANG
3FLM
2FLH

3FLC 470R 3FLP 180R 8

47K
1u0

RREF
1% 1%
10u 16V
RES 2FLG
RES 2FLF

100n

29

3FLJ
(WIFI)
3FL2 +5V * RES
3F32
+5V +T 0R3
+5V
* 3FL7
+5V
+T 0R3
FL38 *1 1C30
+T 0R3 +T 0R3 USB-WIFI-DDn FL39 2
4
3F34-4 FL43
+5V-USB1 4
3FL4-4
5
FL33
+5V-USB2 * 4
3FL8-4 FL40
+5V-USB3
USB-WIFI-DDp
2 3 FL30 3
4
100K 100K 100K

FL31
1 4 5
3 3F34-3 6 3 3FL4-3 6 *3 3FL8-3 6 1F01

100n
USB-OVR1 USB-OVR2 USB-OVR3 ACM2012 6 7
100K 100K 100K
502386-0570
*2 3FL8-2 7

2FLD
2 3F34-2 7 2 3FL4-2 7
100K 100K 100K
1 3F34-1 8 1 3FL4-1 8 * 1 3FL8-1 8 *
100K 100K 100K
ONLY FOR 6000
*

7FL5
5000 2 USB CY7C65634
6000 3 USB + WIFI CY7C65632

4 2012-04-23

USB hub 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_056_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 119

10-3-27 Ethernet & service

Ethernet & service

B06C B06C
5N08 IN07
+3V3 +3V3-ET-ANA
30R
3N53-2 3N53-1 FN56

2N62

2N63

2N66
100n

100n
TXD1-MIPS 7 2 1 8

10u
47R 47R 1N06
2
3N53-3 4
3N53-4
5 FN57 3
UART
RXD1-MIPS 6 3
1 SERVICE

PDZ5.1B(COL)

PDZ5.1B(COL)
+3V3-ET-ANA +3V3 47R 47R
+3V3 CONNECTOR

1N85
6N43

6N44

1N86
MSJ-035-69A-B-RF-PBT-BRF
FN58
IN32 IN38

10K 3N30 IN33

10K
10K

10K
10K

2N52

2N53

2N48
100n

100n
2N49
4n7

10u
1M0
1N70
NX3225GA
3N81
3N82
3N67

3N33
3N66

25M

2N55

2N54
10p

10p
7N10-1

27

12
LAN8710A-EZK

1
RES
RES
RES
RES

CR 1A 2A IO
VDD
CLKIN
5
1
4 XTAL 31 ETH-RXP
2 P
RES 2N70 10p RX 30 ETH-RXN
IN26 N
RESET-ETHERNETn 19
RST
29 ETH-TXP
P
ETH-RXD(0) 11 TX 28 ETH-TXN
0 N
ETH-RXD(1) 10 MODE
1
ETH-RXD(2) 9 20 ETH-TXCLK
RMIISEL TXCLK
ETH-RXD(3) 8
PHYAD2
3N69 10K 26 ETH-RXDV

43
44
45
RXD<0:3> RXDV 7N10-2
3N70 RES
IN63 LAN8710A-EZK
ETH-COL RES 10K 15 13 ETH-RXER
COL RXER VIA
RES 3N71 10K 3N64 10K
CRS_DV RXD4 +3V3 34 40
RES 3N80 10K +3V3 MODE2 0 IN64 RES 35 VIA VIA 41
PHYAD 7 ETH-RXCLK
1 36 42
ETH-TXEN 21 3N65 10K
TXEN RXCLK +3V3
RES VIA
ETH-TXD(0) 22 3 ETH-REGOFF
0 REGOFF
ETH-TXD(1) 23 10K 3N34 3N68 10K

37
38
39
1 1 +3V3
ETH-TXD(2) 24 LED 2 RES ETH-INTSEL
2 TXD 2
ETH-TXD(3) 25 10K 3N72 3N35 10K +3V3
3 INTSEL
ETH-TXER 18 RES
4
14 9N42 ETH-CRS
INT CRS
TXER
32
RBIAS
ETH-MDC 17 IN39

1%
MDC

3N40

12K1
ETH-MDIO 16
MDIO
3N51 1K5 +3V3 VSS
33

+3V3-ET-ANA

CONFIGURATION RESISTOR SETTINGS

Resistor POP EMPTY

1%

1%

1%
1%
3N22

49R9

3N25

49R9

3N99

49R9
3N95

49R9

3N64 (RES) PHYADD(0) = 1 PHYADD(0) = 0

ETHERNET CONNECTOR
5N0C-1
1N87 E2101
3N65 (RES) PHYADD(1) = 1 PHYADD(1) = 0
1N00
ETH-TXP FN27 3 ACM2012 2 16 RD+ RX+ 1
1
4
FN60
2 3N66 (RES) PHYADD(2) = 1 PHYADD(2) = 0
ETH-TXN FN28 1 15 RDTC RXCT 2
3
1N88 4
14 RD- RX- 3
5
3N67 (RES) RMII mode selected MII mode selected
ETH-RXP FN29 3 ACM2012 2 FN61
5N0C-2 6
4 1 E2101 7
ETH-RXN FN31
8 3N68 (RES) Internal 1.2V reg. disabled Internal 1.2V reg. enabled
+3V3-ET-ANA 11 TD+ TX+ 6
CDA5C16GTH

CDA5C16GTH

CDA5C16GTH

CDA5C16GTH
5

7
6

9
6N47-4

6N47-3

6N47-2

6N47-1
5N01

5N02

5N03

5N04

RES

3N69 (RES)
RES

10 TCT TXCT 7 98435-111LF

RES

RES
16V

16V

16V

16V
RES 27n

RES 27n

RES 27n

RES 27n

MODE(0) = 0 MODE(0) = 1
FN34
9 TD- TX- 8
4

2
3

75R
75R
75R
75R
3N26

3N98

IN0B 3N70 (RES)

22R

22R

MODE(1) = 0 MODE(1) = 1

8
7
6
5
2N08

2N09
2N05

2N07

RES 15p

RES 15p
RES 15p

RES 15p

FN30 1 3N71 (RES) MODE(2) = 0 MODE(2) = 1

2
3
4
RES 2N56

RES 2N57

RES 2N58

RES 2N59

2N60

3N72
15p

15p

15p

15p

22n

INTERRUPT FUNCTION INTERRUPT FUNCTION

3N27

RES 0 ohm

RES 0 ohm

3N29

0 ohm

RES 0 ohm
3N39

3N0A-1
3N0A-2
3N0A-3
3N0A-4
3N28

Primary Secondary DISABLED ON ENABLED ON

RES

FN32
IN0A nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL
2N0L
1n0

ETH-INTSEL

ETH-REGOFF
FN33

4 2012-04-23

Ethernet & service 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_057_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 120

10-3-28 HDMI

HDMI
B06D +3V3 B06D
I2C Address

5NC4

30R
7NC2
+5V RT9715EGB FNC3
5NC0 FNC0 MICOM-VCC33
FNCS
5 3 30R
SII9187B = 0xB2
VIN FLG
HDMI CONNECTOR 3 +3V3

3NCH
2NCV
2NC0

2NC2
RES 2NC1

100n

10K
10u

1u0
100u 16V
1P04
FNCT

2NC4
4 1

PDZ2.4B(COL)
ARX2+

1u0
1 EN VOUT
2 EN FNCB

6NC2
3K3
3 ARX2-

3NC6
RES
ARX1+ GND
4
5
ARX1- INC8

2
6 AIN-5V 5NC3 RES +3V3
ARX0+ +3V3-HDMI
7
8 30R

RES 2NCW
2NC6

2NC7

2NC8

2NC3

100n
100n

100n

100n

10u
9 ARX0-

3NC7

2K2
10 ARXC+

3
3NC1-3
11
ARXC-

47K
12
13 PCEC-HDMI
Reserved 7NC1

6
14

27
64

37

38
FNC1 SII9287B

9
15 ARX-DDC-SCL ARX-DDC-SCL

MICOM_VCC33

SBVCC33
FNC2 ARX-DDC-SDA ARX-DDC-SDA VCC33
16
17 ARX-HOTPLUG +5V-EDID
FNC4

8
4 5 31
AIN-5V

3NC1-1
18 3NCM-1 IN42 (CBUS) HPD0

6
19 FNC5 ARX-HOTPLUG 1 8 3NCN-4 100K 32

47K

3NCP-1

3NCP-3
AIN-5V R0PWR5V

RES 2NCZ

100n
FNC6 21 20 2NCM 1u0

10K

10K
10R
23 22 ARX-DDC-SDA 29

1
DSDA0
ARX-DDC-SCL 30 49

3
DSCL0 R4PWR5V
47266-9002
ARXC- 65 48
N DSCL4 VGA-SCL-EDID-HDMI
ARXC+ 66 R0XC 47
AIN-5V P DSDA4 VGA-SDA-EDID-HDMI
HDMI CONNECTOR 2
1P03 ARX0- 67 51 9NC2 CEC-HDMI
N CEC_D
BRX2+ ARX0+ 68 R0X0 RES
1 P
2
BRX2- ARX1- 69
3 N
BRX1+ ARX1+ 70 R0X1
4 P
5
BRX1- ARX2- 71
6 BIN-5V N
BRX0+ ARX2+ 72 R0X2
7 P
BRX-HOTPLUG 57 HDMIA-RX2-
8 N
BRX0- 3 6 35 TX2 56 HDMIA-RX2+
9 3NCM-2 IN43 (CBUS) HPD1 P
BRXC+ 2 7 3NCN-3 100K 36
10 BIN-5V R1PWR5V

2
2NCN 1u0 59 HDMIA-RX1-

3NCA-2
11 10R N
BRXC- BRX-DDC-SDA 33 TX1 58 HDMIA-RX1+
12 DSDA1 P

47K
PCEC-HDMI BRX-DDC-SCL 34
13 DSCL1
61 HDMIA-RX0-

7
14 N
FNCC BRX-DDC-SCL BRX-DDC-SCL BRXC- 1 TX0 60 HDMIA-RX0+
15 N P
FNCD BRX-DDC-SDA BRX-DDC-SDA BRXC+ 2 R1XC
16 P
63 HDMIA-RXC-
17 N

8
FNC8 BRX0- 3 TXC 62 HDMIA-RXC+

3NCA-1
18 BIN-5V N P
19 FNCF BRX-HOTPLUG BRX0+ 4 R1X0
P

47K
FNCG 21 3NCJ RES
20 MICOM-VCC33
3NCK
23 22 BRX1- 5 55 4K7

1
N TPWR_CI2CA
BRX1+ 6 R1X1
P 4K7
FNCR
BRX2- 7 50 9NC3 PCEC-HDMI
N CEC_A
BRX2+ 8 R1X2 RES
BIN-5V P
CRX-HOTPLUG FNCY 3NCL RES
2 7 41 52 +3V3
IN44 (CBUS) HPD2 INT
HDMI CONNECTOR 1 3 3NCM-3 6 3NCN-2 100K 42
CIN-5V R2PWR5V 4K7
1P02 2NCP 1u0
10R
CRX2+ CRX-DDC-SDA 39
1 DSDA2
CRX-DDC-SCL 40
2 DSCL2
3 CRX2-
CRX1+ CRXC- 11
4 N
CRXC+ 12 R2XC 54 3NC3 47R SCL-SSB-550
5 P CSCL
CRX1- 53 3NC5 47R SDA-SSB-550
6 CIN-5V CSDA
CRX0+ CRX0- 13
7 N
CRX0+ 14 R2X0
8 P
CRX0- 10
9

RES 2NCX

RES 2NCY
15 RSVDL 28

10p

10p
10 CRXC+ CRX1- N
4

CRX1+ 16 R2X1
3NCA-4

11 P
12 CRXC-
47K

FNCJ PCEC-HDMI CRX2- 17

13 N
FNCA ARC-eHDMI+ CRX2+ 18 R2X2
5

14 P
FNCK CRX-DDC-SCL CRX-DDC-SCL DRX-HOTPLUG
15
FNCL CRX-DDC-SDA CRX-DDC-SDA 1 8 45
16 3NCM-4 IN45 (CBUS) HPD3
4 5 3NCN-1 100K 46 74
17 DIN-5V R3PWR5V
6

FNCM CIN-5V 2NCQ 1u0 75

3NCA-3

18 10R
19 FNCN CRX-HOTPLUG DRX-DDC-SDA 43 76
DSDA3
47K

21 20 DRX-DDC-SCL 44 77
FNCP DSCL3
23 22 78
3

3N23 +3V3-STANDBY 5NC2

eHDMI+ DRXC- 19 79
N
DRXC+ 20 R3XC 80
RES 22K 30R P

2NCC
81

10p
7N02 RES ARC-eHDMI+
BC847BW DRX0- 21 VIA 82
CIN-5V N
DRX0+ 22 R3X0 83
P
84
DRX1- 23 85
3NCU-2 N
7NC0 DDCA-SDA 2 7 DRX1+ 24 R3X1 86
+3V3 P
BC847BW INC6 87
3NCD 10K
PCEC-HDMI 9NC0 CEC-HDMI DRX2- 25 88
1 2 3NCU-4 N
INC4 DDCA-SCL 4 5 DRX2+ 26 R3X2 89
100R INC5 P
10K
EPAD

73
INC7
HDMI CONNECTOR SIDE
FNCW
3NCR

1P05
22K

+3V3-STANDBY DRX2+
1
2
3 DRX2-
4 DRX1+

6NC1 5 DIN-5V
6 DRX1-
+5V +5V-VGA 7 DRX0+
8
BAT54 COL 9 DRX0-

8
DRXC+

3NCT-1
10

47K
IN11 11
12 DRXC-
PCEC-HDMI

1
13
3NCG

4R7

14
FNC9 DRX-DDC-SCL DRX-DDC-SCL
15
FNCH DRX-DDC-SDA DRX-DDC-SDA 2 3NCT-2 7 DIN-5V
16
3NCF FNCZ 2NCU 17 47K
FNCQ
18 DIN-5V
19 FNCU DRX-HOTPLUG
100K 1u0
FNCV 21 20
23 22 4 2012-04-23

+5V-EDID
HDMI 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_058_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 121

10-3-29 FPGA, power & control

FPGA, power & control

B07A B07A
5J20 FJ21 6J21 DBG
+3V3 VAUX 3 3J21 DBG +3V3
30R
LTST-C190KGKT 470R
DONE 1 7J25

220n
PDTC144EU

2J24
RES 2J21

2J23

2J26

2J27
2J22

2J25
2u2
2u2

2u2
2u2

2u2
2u2
2 DBG

RES
7J20
LD1117DT12
FJ22 MISO
3 2 VCCINT
+3V3 IN OUT
+3V3
COM
FJ26
100n

220n

220n
2J29

2J32

2J34
2J28

2J30

2J31

2J33

2J35

2J36
10u

2u2

2u2

2u2
22u

22u
1

RES

2J2K

100n
3J23

4K7
7J21

3J24

10R
* M25P40-VMN6

8
5J21 FJ23
VCCO3 1J22 VCC

+3V3 FJ27 IJ22
30R CCLK MOSI 5
1 D Q
CSO-B 2
2 FJ28
220n

220n

220n
2J37

2J38

2J39

2J40

2J41
6
2u2

2u2

3 MOSI CCLK C
4 MISO FJ29
PROG-B CSO-B 1
RES

5 S
7
6 HOLD
7 8 3
W
502382-0670 GND

4
5J22 FJ20
+3V3
30R
VCCO2
PROGRAMMING FJ30 6SLX4-4MB-M25P40
6SLX9-4MB-M25P40
220n

220n

220n
2J43

2J44

2J45

2J46
2J42

ENGINEERING
2u2
2u2
RES

+3V3

5J23 FJ24
+3V3 7J22
VCCO1 3225

4
30R FPGA-LED0
3J25
2J2A

2J2B
220n

220n

220n
2J47

2J48

2J49

1 3
2u2

FPGA-SYS-CLK FPGA-LED1
2u2

VALUE 47R
FPGA-LED2
RES

2J2M

100n

2
FPGA-LED3

DBG 3J26-3

DBG 3J26-1
DBG 3J26-4

DBG 3J26-2
6 330R 3
5 330R 4

7 330R 2

8 330R 1
5J24 FJ25
+3V3 VCCO0
30R
2J2G
2J2D
2J2C

2J2H
2J2F

220n

220n

220n
2u2
2u2

+3V3 +3V3

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
LTST-C190KGKT
DBG

DBG

DBG
DBG
RES

7J23 7J24
74LVC1GU04GW 74LVC1GU04GW RES

5
2 4 2 4 3J27
1 1 RES

6J22

6J24

6J25
6J23
NC NC
47R

3
3J28 3J29
+3V3 FPGA-SYS-CLK
1M0 47R
3J30

1K0 PNX-SPI-CLK RES 4 9J21-4 5 AMBI-SPI-OUT-CCLK

1J21
3
100n

RES 3
2J50

3J31

9J21-3 6
10K

7J26 PNX-SPI-SDO AMBI-SPI-OUT-MOSI

NCP803
VCC 12M RES 2 9J21-2 7
PNX-SPI-SDI AMBI-SPI-OUT-MISO
2J2N

2J2P

2 RES 1 9J21-1 8
18p

18p

RESET PROG-B PNX-SPI-CS-BLn AMBI-SPI-OUT-CSn

2J51

GND
1n0
1

4 2012-04-23

FPGA, power & control 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_059_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 122

10-3-30 FPGA, I/O banks

FPGA, I/O banks

B07B B07B
7J01-1
XC6SLX4-2TQG144C0100
7J01-6
XC6SLX4-2TQG144C0100 BANK0
RES 9J02 144 127
IO_L1P_HSWAPEN_0 IO_L36P_GCLK15_0
20 143 126
IO_L1N_VREF_0 IO_L36N_GCLK14_0
36 142 124

VCCAUX
IO_L2P_0 IO_L37P_GCLK13_0
VAUX 53 141 123
IO_L2N_0 IO_L37N_GCLK12_0
90 140 121
IO_L3P_0 IO_L62P_0
129 139 120
IO_L3N_0 IO_L62N_VREF_0
138 119
IO_L4P_0 IO_L63P_SCP7_0
19 3 137 118
IO_L4N_0 IO_L63N_SCP6_0
28 13 134 117

VCCINT
IO_L34P_GCLK19_0 IO_L64P_SCP5_0
VCCINT 52 25 133 116
IO_L34N_GCLK18_0 IO_L64N_SCP4_0
89 49 132 115
IO_L35P_GCLK17_0 IO_L65P_SCP3_0

PWR_GND
128 54 131 114
IO_L35N_GCLK16_0 IO_L65N_SCP2_0
68 112
IO_L66P_SCP1_0

GND
122 77 111

VCCO_3 VCCO_2 VCCO_1 VCCO_0

IO_L66N_SCP0_0
VCCO0 125 91
135 96
108
76 113
VCCO1 86 130 7J01-2
103 136 XC6SLX4-2TQG144C0100

42
BANK1
VCCO2
63 105 88
IO_L1P_1 IO_L42P_GCLK7_1
104 87
IO_L1N_VREF_1 IO_L42N_GCLK6_TRDY1_1
4 102 85
IO_L32P_1 IO_L43P_GCLK5_1
VCCO3 18 101 84
IO_L32N_1 IO_L43N_GCLK4_1
31 100 83
IO_L33P_1 IO_L45P_1
99 82
IO_L33N_1 IO_L45N_1
98 81
IO_L34P_1 IO_L46P_1
97 80
IO_L34N_1 IO_L46N_1
95 79
IO_L40P_GCLK11_1 IO_L47P_1
94 78
IO_L40N_GCLK10_1 IO_L47N_1
93 75
IO_L41P_GCLK9_IRDY1_1 IO_L74P_AWAKE_1
92 74
IO_L41N_GCLK8_1 IO_L74N_DOUT_BUSY_1

7J01-3
XC6SLX4-2TQG144C0100
BANK2
72 56 FPGA-LED1
3J01 FJ01 CMPCS_B_2 IO_L30P_GCLK1_D13_2
VCCO2 DONE DONE 71 55 FPGA-LED0
DONE_2 IO_L30N_GCLK0_USERCCLK_2
CCLK 3J02 70 51
1K0 IO_L1P_CCLK_2 IO_L31P_GCLK31_D14_2
IJ01 69 50 FPGA-SYS-CLK
10R IO_L1N_M0_CMPMISO_2 IO_L31N_GCLK30_D15_2
PNX-SPI-CLK 67 48
IO_L2P_CMPCLK_2 IO_L48P_D7_2
PNX-SPI-SDO 66 47
IO_L2N_CMPMOSI_2 IO_L48N_RDWR_B_VREF_2
MISO 65 46 3D-LR-DISP
IO_L3P_D0_DIN_MISO_MISO1_2 IO_L49P_D3_2
MOSI 3J09 10R 64 45 3D-LED
IO_L3N_MOSI_CSI_B_MISO0_2 IO_L49N_D4_2
PNX-SPI-SDI 62 44 3D-VS
IO_L12P_D1_MISO2_2 IO_L62P_D5_2
PNX-SPI-CS-BLn 61 43 3D-LR
IO_L12N_D2_MISO3_2 IO_L62N_D6_2
9J01 60 41 3J03 10R SCL-SSB-550
IO_L13P_M1_2 IO_L64P_D8_2
59 40 3J04 10R SDA-SSB-550
IO_L13N_D10_2 IO_L64N_D9_2 IJ02 2J01
FPGA-LED3 58 39 100n
IO_L14P_D11_2 IO_L65P_INIT_B_2
FPGA-LED2 57 38 RES 3J05 10R CSO-B
IO_L14N_D12_2 IO_L65N_CSO_B_2
37 PROG-B
VAUX PROGRAM_B_2
FJ07

7J01-4
3J0G

3J0C

XC6SLX4-2TQG144C0100
10K

10K

BANK3
35 17 BL-DIM1
IO_L1P_3 IO_L43P_GCLK23_3
34 16 BL-DIM2
IO_L1N_VREF_3 IO_L43N_GCLK22_IRDY2_3
33 15 BL-DIM3
IO_L2P_3 IO_L44P_GCLK21_3
32 14 BL-DIM4
IO_L2N_3 IO_L44N_GCLK20_3
AMBI-SPI-OUT-CSn 3J0A 33R 30 12 BL-DIM5
IO_L36P_3 IO_L49P_3
AMBI-SPI-OUT-MISO 3J00 33R 29 11 BL-DIM6
IO_L36N_3 IO_L49N_3
AMBI-SPI-OUT-MOSI 27 10 BL-DIM7
IO_L37P_3 IO_L50P_3
AMBI-SPI-OUT-CCLK 26 9 BL-DIM8
IO_L37N_3 IO_L50N_3
24 8
IO_L41P_GCLK27_3 IO_L51P_3
23 7 BL-DIM
10p

10p

IO_L41N_GCLK26_3 IO_L51N_3
22 6
IO_L42P_GCLK25_TRDY2_3 IO_L52P_3
21 5
IO_L42N_GCLK24_3 IO_L52N_3
2
IO_L83P_3
1
2J03

2J04

IO_L83N_VREF_3

VAUX
10K

10K
3J06

3J07

7J01-5
XC6SLX4-2TQG144C0100

MISC
DBG 109
TCK
1J02 110
TDI
1 FJ02 107
TMS
2 FJ03 106
TDO
3 FJ04
4 FJ05 73
SUSPEND
5 FJ06
6
VAUX
7 8
100n DBG
2J02

4 2012-04-23

FPGA, I/O banks 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_060_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 123

10-3-31 Tuner, channel decoder

Tuner, channel decoder

B08A VCC-TUNER

3FA0 IFA1
B08A
0R1

2FA5
5FA1

2FA6
30R

22u

22u
2 3 2 3

2FA7

2FA8

100n
10p
1FA1 1 1 1FA2
U.FL-R-SMT-1(10) U.FL-R-SMT-1(10) 1F00
SUT-RE214Z

15

14
FFA9 1
3KA0 5KC8 A3.3V
IF-N-DVBT2 AFA5 2
IF1_P
IF-P-DVBT2 47R 3KA1 330n 5KC9 AFA4 3
IF1_N
330n FFA8 4
47R 2FAJ AGC1

TUNER
9FA1 9FA0 5
NC1
7FA0 10p 2FAK 6
5FA4 NC2
LD1117DT33 SOC-IF-N 3FA3 AFA2 AFA0 10p 7
IF2_P
IFA0 SOC-IF-P 47R 3FA4 AFA3 330n 5FA5 AFA1 8
5FA0 FFA0 IF2_N
+5V 3 2 VCC-TUNER 47R 330n FFA4 9
IN OUT 5FA6 FFA3 AGC2
SCL-TUNER FFA7 3FA2 2FA9 10p 10
30R I2C_SCL
330u 6.3V COM SDA-TUNER FFA6 5FA7 30R 3FA1 100R 11
I2C_SDA

2FA1
2FA0

2FA2

2FA4
100n
2FAA 10p

10u

1n0
RES 30R 100R FFA2

12

13

16
1

2FAG
2FAC

2FAH
2FAB

10p

10p

10p

10p
FFA1 1FA0 DBG FFAA
1
2
3
5 4

BM03B-SRSS-TBT
3KA3
IF-AGC
100R

3KCC
2FAF

22K
10p
3KA4 FFA5 3FA7
IF-AGC FFAB
100R 100R
SOC-IF-AGC RES

2FAD

3FAD

2FAE
3KA2

3FA8
6K8

6K8

22K
22n

10p
RES RES
IFA6

T2-AGC FFAC

3FA9

2K7
+1V2-DVBT2-C +1V2-DVBT2-P 7KA0
PDTA114EU
RES
+3V3-DVBT2-D
VCC-TUNER
2KC4
2KC7

2KC6

2KC5

2KC0

100n

6 IFA3 3
100n
100n
100n

100n
100n

7FA1-1 2 5 7FA1-2
2KC2

2KC1
2KC3

100n
100n

BC857BS(COL) BC857BS(COL)
1 4
4 9RC2-4 5 TS-INT-CLK
1 9RC2-1 8 TS-INT-VALID IFA5 IFA4
2 9RC2-2 7 TS-INT-SOP
3 9RC2-3 6 TS-INT-DATA

3FAC
3FAA

3FAB
470R

470R
10K
2KCC

2KCB
12p

12p

7KC0 RES 2KCK

10
22
28
44

19
42

32

CXD2834ER
7

41M PVDD
2
4

IKC0 CVDD DVDD 3KC1 6p8 VCC-TUNER

3 1 35 5 TS-CHDEC-CLK
XTALI TSCLK
4 47R 8 1 3KC0-1 TS-CHDEC-VALID
5KC0 1KC0 3KC4 IKC1 TSVALID
34 3 7 2 3KC0-2 47R TS-CHDEC-SOP
XTALO TSSYNC
1K0 47R
4u7 2KCD
8 6 3 3KC0-3 TS-CHDEC-DATA
2KCE IKC2 3KCA 0
IF-P-DVBT2 9KC0 10p 38 9 47R
TAINP 1
IF-N-DVBT2 9KC1 100n 2KCF 47R 3KCB 37 12
TAINM 2
100n 2KCG IKC3 13
47R 3
10p TSDATA 14
5KC1 4

T2-AGC 4u7
3KC6
41
RFAIN I2C 5
15
16
5KC5 IKC7 5KC7 IKC8
6 VCC-TUNER +3V3-DVBT2-D +1V2-FE +1V2-DVBT2-C
1K0 ADDRESS 7
17
30R 30R
2KCH

1
10n

DKC0 GPIO0
= 3KC2 5KC6

2KCR
47 20

1u0
GPIO1 SCL SCL-FE +3V3
2 21 47R 3KC3 SDA-FE
IKC4 GPIO2 0XD8 SDA
47R
30R

2KCP
50

1u0
3KC7
IF-AGC 48 51
TIFAGC
2KCJ 52
10K
100n 53
3KC8 IKC5
+3V3-DVBT2-D 46 54 IKC9
IKC6 TTUSCL 3KCE
3K3 3KC9 45 55 +1V2-DVBT2-C +1V2-DVBT2-P
TTUSDA
56
3K3 22R
57

2KCS
24 58

10u
TESTMODE
59
60
25 61
SLVADR0
VIA 62
63 Position Nr FUSION TV550-R4
26 64
DKC1 OSCEN_X
65 3FA7 - 100R
66
29 67 3FA9
RESET-FUSION-OUTn RST_X 2K7 -
68
69
3FAA 470R -
30 70
SLVADR3
71
3FAB 10K -
72
33
NC1
73
3FAC 470R -
40 74
NC2
VSS 3FAD 22K 22K
GND_HS
6
11
18
23
27
31
36
39
43

49

2FAD 100nF 22nF 4 2012-04-23

FKC1
7FA1 BC857BS _
Tuner, channel decoder 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_061_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 124

10-3-32 DVBS, FE

DVBS, FE
B08B B08B
7RA1-1
STV0903BAC
7RA1-2
STV0903BAC

+3V3-DVBS
5RA0 IRA8
+3V3-DEMOD
+1V0-DVBS
15
1
XTAL 122
XTALI MAIN VS
52 SENSE+1V0-DVBS

17 POWER_VIA 4 124 16
3RA2 FRA7
AGC
30R NC XTALO AGCRF1

RES 2RCA
22 6

2p2
1K0
I2C-ADDRESS : D0 2RC9 RES

2RCD

2RCC
2RCE
2RAY

2RA4
2RA0

2RA1

2RA2

2RA3
2RB0

100n
100n

100n
25 10 59 63

22u
22u

22u

22u

10n

10n
RES DIRCLK 0 NC
28 14 104 64 47n 47p TS-INT-DATA
GNDA CLKI 1 NC
RES 31 113 103 65 TS-INT-CLK
NC CLKI2 2 NC
33 117 100 67 TS-INT-SOP
NC CLKOUT27 3 NC
36 121 D 68 TS-INT-VALID
4 NC
39 125 QM 11 70
N 5 NC
42 QP 12 I1 71
P 6 NC
45 129 73 3RA0-3 3 6 TS-DVBS-DATA
GND_HS 7
+1V0-DVBS 48 74 3RA1 47R TS-DVBS-CLK
CLKOUT
IRA7 51 130 75 3RA0-2 2 7 47R TS-DVBS-SOP
5RA1 STROUT
+3V3-DVBS +3V3RF 53 131 IM 8 78 3RA0-1 1 8 47R TS-DVBS-VALID
N DPN

2RAA
2RA8
2RA7
2RA5

2RA6

2RA9
100n
100n

100n
57 132 IP 7 Q1 79 47R

10n
10n

10n
30R VDD1V0 P ERROR NC
61 133
2RBK
2RBL

10n 66 134 82
22u

NC

RES 2RB1
69 135 83

6p8
NC
72 136 60 84
0 NC
77 137 56 CS 86
1 NC
+1V0-DVBS 81 138 87
NC
85 139 128 89
DISEQCIN1 NC
88 140 F22-DISECQ-TX 20 90 NC
DISEQCOUT1

2RAG
2RAD
2RAC
2RAB

2RAE

2RAF
100n

100n
100n
93 141 126 91

10n

10n

22u
NC FSKRX_IN NC
99 142 NC
107 94
FSKRX_OUT NC
102 143 NC 95
3RA7 IRA0 NC
Diversity Matrix (Satellite Tuner dependant) 105
110
144
145
SCL-FE
SDA-FE 47R 47R
97
98
SCL
108
109
NC
SDA NC
112 146 111 NC
3RA8 IRA1
147 SCLT 19 115
SCLT NC
Position Nr Affected Pin Default Value STV6110 STV6111 +3V3-DEMOD 21 VIA 148 SDAT 18
SDAT
1 116 NC
38 149 119 NC

2RBY 4,5 100P - X

54 150 120 NC

2RAM
2RAH

2RAN

2RAP
2RAK

2RAL
2RAJ

100n

100n
100n

100n
76 151

10n
10n

10n
FRA0
9RB8 4,5 JUMP X - 80
92
VDD3V3 152
153
RESET-DVBS
IRA2
62
58
RESETB
COMP
0
40
41 IRA3 3RA3

2RBM 4,5 27P X - 96 154

STDBY 1
120K

3RA6
106 155 26 101

10K
FRA1 TCK 1 NC

2RCB 4,5 27P - X 2

156
157
FRA2
23
24
TDI 2
50
49
NC

2RBW 7 33N - X
+1V0-DVBS
3 VDDA1V0 158
159
+3V3-DVBS
FRA3
FRA4
FRA5
29
27
TDO
TMS
TRST
3
4
5
47
46
NC
NC
NC

-
2RAR

100n
5 160 44
9RB6 25 JUMP X 9 161
6
43
NC
GPIO 7 NC

3RA4
13 162 37

1K0
9RB7 25 JUMP X 114 163
8
35
NC

- VDDA2V5 9 NC
118 164 34 NC
2RB7 27 10U X 123 165
10
32

- FRA6 11 NC
+2V5-DVBS 127 30
2RBU 27 4N7 X 12
55
NC
NC

-
13
2RBV 27 68P X

2RAW
2RAU
2RAS

2RAV
2RAT
100n

100n

100n

100n

100n
9RB9 27 JUMP X -
3RB3 27 4R7 X 2K2

+3V3RF

IRA4 IRA9
* 9RB9 * 3RB3
4R7

2RBU

2RBV
2RB2

2RB3

2RB4

2RB6

2RB7
2RB5

100n
100n

68p
1n0

1n0

1n0

4n7

10u
* * *
7RC1
2RBE LD1117DT33
7RA0 5RC0 IRC3 FRC1
STV6110AT 6 8 11 14 22 27 28 3 2
10p 3 +5V IN OUT +3V3-DVBS
2 NC 4

LNA LT MIX DIG BB VCO SYN

NX3225GA

16V
2RB8 3RB0 30R
1RA0

30 VSS 32 COM
16M

XTAL_OUT XTAL

2RC5

2RC6
100n
XTAL_IN 100p 1K0

22u
2RBF 1 31 18 4 5 QP 1
IP
19 3 6 3RB1-4 100R
IN QM
1 3RB1-3 100R
10p XTAL_CMD
2RC7 RES SATELLITE 21 1 8 IP
QP
SCLT 10p 12 TUNER 20 2 7 3RB1-1 100R IM
SCL QN
SDAT 13 3RB1-2 100R
SDA
2RC8 RES I2C-ADDRESS : C6 RF_OUT
7
10p

10p

10p

10p

10p

10p

10p

10p
AGC 10p 2
AGC
34
2RBW
2RBD

9RB0 16 35
10p

33n

2RBC

2RBN

2RBR
2RBA

2RBB

2RBP

2RBS
2RB9

AS IRC0
RES 36 +3V3
23 37
+3V3RF
24 NC VIA 38 *

2RC0
39

1u0
1R01 7RC0
40

6 2
1 * 2RBM
4
RF_IN
41
42
RT9193-25GB

27p FRC0
7 3 1 5 +2V5-DVBS
IN OUT
2RBY

GND
100p

8 4 3RC1 IRC1
IRC2
9 5 RF LNA LT MIX DIG BB VCO SYN HS 3 4
+3V3-DVBS EN BP
5RA2

2RC1

2RC2
5 3 9 10 15 17 25 26 29 33
27n

1u0

1u0
10
* 10K
COM

2RC3

3RC2

2RC4
100n

10K

10n
2
FRA8
* 2RCB
RES 2RBG

9RB6

9RB7
0p56

+V-LNB
27p
* *
SM15T

2RBH
RES 2RBT

6RA0

9RB8
2RBJ

100p
47p

1n0

+3V3RF
*
+3V3-DVBS 7RC2
BC847BW

4 2012-04-23

DVBS, FE 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_062_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 125

10-3-33 Video out - LVDS

Video out - LVDS

B09A B09A
+3V3

RESERVED FOR 100HZ PANEL LGD 50HZ

* 3D TM100
OTHERS

3G41 -- x

10K
10K

10K

10K

10K

10K

10K

10K

10K

10K
+VDISP

100p
-- x

47p

47p

47p

47p
3G42

10p

10p

47p

47p

47p
3G43 -- x
3G44 -- x TO DISPLAY
3G45 -- x
3G46 -- -- 1G51

RES 2G7C

RES 2G7D
RES 2G7B

RES 2G7A
2G7F
RES 3G34

RES 3G38

RES 2G77

2G75

2G76

RES 2G26

RES 3G40

RES 2G79
RES 3G39
RES 3G46

3G43

3G44

SAMSUNG 3G35

3G47
RES 3G33
3G47 x -- 20519-051E

5
6
7
8
3G48 x --

9G0K-4
9G0K-3
9G0K-2
9G0K-1
x --
2G7F
* * * * 60 61
58 59
56 57
TO DISPLAY *

4
3
2
1
54 55
1G50 SAMSUNG 3G32
2G92 100n *20519-041E CTRL-DISP3
SDA-DISP 3G2W
100R
10R
FG34
FG2H
52 53
51
50
50 51 SCL-DISP 3G2Y 10R FG2G
2G93 100n 49
48 49
48
46 47 CTRL-DISP3 RES 3G37 100R FG2R
2G94 100n FG2J 47
44 45 68R

2G95 100n
42 43
BL-PWM
3D-LR-DISP ** 3G48
3G45 100R
46
45
3G41 100R
FG30 41 CTRL-DISP1
* 3G42 100R FG2L
44
FG31
FG32
40
39
CTRL-DISP2
3D-LR * 3G31
RES 100R FG2M
43
42
FG33 38 41
2G96 47p TX3-A- FG2U
2G99 47p 37 40
TX3-A+ FG2F
2G97 47p 36 39
TX3-B- FG1Y
2G98 47p 35 38
34 TX3-B+ FG1Z 37
TX3-C- FG20
FG1C 33 36
TX1-A- 32 TX3-C+ FG21 35
TX1-A+ FG1D
31 34
TX1-B- FG2T TX3-CLK- FG22
30 33
TX1-B+ FG1F 29 TX3-CLK+ FG23 32
TX1-C- FG1G
28 31
TX1-C+ FG1H TX3-D- FG24
27 30
TX3-D+ FG25
FG11 26 29
TX1-CLK- TX3-E- FG26
25 28
TX1-CLK+ FG1J TX3-E+ FG27
24 27
RES 2G28 47p
23 26
TX1-D- FG1K RES 2G29 47p
22 25
TX1-D+ FG1L TX4-A- FG28
21 24
TX1-E- FG1M TX4-A+ FG29
20 23
TX1-E+ FG1N TX4-B- FG2A
19 22
TX4-B+ FG2B
18 21
TX4-C- FG2C
17 20
TX2-A- FG12 TX4-C+ FG2D
16 19
TX2-A+ FG13 15 18
TX2-B- FG14 TX4-CLK- FG1R
14 17
TX2-B+ FG15 13 TX4-CLK+ FG1S 16
TX2-C- FG16 12 15
TX2-C+ FG17 TX4-D- FG1T
11 14
TX4-D+ FG1U
FG18 10 13
TX2-CLK- TX4-E- FG1W
9 12
TX2-CLK+ FG19 TX4-E+ FG1V
8 11
7 10
TX2-D- FG1A
6 FG2P 9
TX2-D+ FG1B
5 8
TX2-E- FG1Q
4 7

2G91

100n
TX2-E+ FG1P
3 6
RES 9G0G FG2N
2 5
1 +VDISP 4
3
1X03 2
EMC HOLE 1

RES 2G9C

RES 2G9D
RES 2G9E
RES 2G9F

EMC 100n

100n
EMC 100n

EMC 100n
EMC
3 2011-12-29

Video out - LVDS 2 2011-09-29

3139 123 6531

19220_076_120229.eps
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 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 126

10-3-34 FPGA, I/O banks

FPGA, I/O banks

B10A B10A

7K00-3
7K00-6 7K00-1 XC6SLX25-2FTG256C0100
XC6SLX25-2FTG256C0100 XC6SLX25-2FTG256C0100
BANK2
POWER RES 9K01
BANK0 CCLK-LX25 3K06 10R R11 P8 TX1-D+
IO_L1P_CCLK_2 IO_L30P_GCLK1_D13_2
G7 C4 E7 BL-DIM7 T11 T8 TX1-D-
LCD-PWR-ON-FPGAn IO_L1P_HSWAPEN_0 IO_L36P_GCLK15_0 IK00 IO_L1N_M0_CMPMISO_2 IO_L30N_GCLK0_USERCCLK_2
G9 A4 E8 BL-DIM3
IO_L1N_VREF_0 IO_L36N_GCLK14_0
H10 TX1-A+ M12 P7 TX2-B+
IO_L2P_CMPCLK_2 IO_L31P_GCLK31_D14_2
+1V2-LX25 H8 TX3-B+ B5 E10 AMBI-SPI-OUT-MOSI TX1-A- M11 M7 TX2-B-
IO_L2P_0 IO_L37P_GCLK13_0 IO_L2N_CMPMOSI_2 IO_L31N_GCLK30_D15_2
J7 VCCINT TX3-B- A5 C10 AMBI-SPI-OUT-CCLK
IO_L2N_0 IO_L37N_GCLK12_0
J9 MISO-LX25 P10 R7 TX1-E+
IO_L3P_D0_DIN_MISO_MISO1_2 IO_L32P_GCLK29_2
K10 TX3-A+ D5 D8 BL-DIM4 MOSI-LX25 3K12 10R T10 T7 TX1-E-
IO_L3P_0 IO_L38P_0 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L32N_GCLK28_2
K8 A1 TX3-A- C5 C8 BL-DIM5
IO_L3N_0 IO_L38N_VREF_0 FK08
A16 FPGA-RESET-SYSn RES 3K08 1K0 N12 P6 FPGA-RESET-SYSn
IO_L12P_D1_MISO2_2 IO_L47P_2
E5 B11 TX3-CLK+ B6 C11 TX4-C+ 3D-LR-DISP P12 T6
IO_L4P_0 IO_L39P_0 IO_L12N_D2_MISO3_2 IO_L47N_2
F11 B7 TX3-CLK- A6 A11 TX4-C-
IO_L4N_0 IO_L39N_0 FK09
F8 D13 9K02 N11 R5 TX2-CLK+
IO_L13P_M1_2 IO_L48P_D7_2
VAUX-LX25 G10 D4 BL-DIM6 F7 F9 BL-DIM1 BL-DIM P11 T5 TX2-CLK-
IO_L5P_0 IO_L40P_0 IO_L13N_D10_2 IO_L48N_RDWR_B_VREF_2
H6 VCCAUX E9 BL-DIM8 E6 D9 BL-DIM2
IO_L5N_0 IO_L40N_0
J10 G15 TX1-CLK+ N9 N5 TX2-D+
IO_L14P_D11_2 IO_L49P_D3_2
L6 G2 TX3-D+ C7 B12 TX4-CLK+ TX1-CLK- P9 P5 TX2-D-
IO_L6P_0 IO_L62P_0 IO_L14N_D12_2 IO_L49N_D4_2
L9 G8 TX3-D- A7 A12 TX4-CLK-
IO_L6N_0 IO_L62N_VREF_0
H12 TX1-C+ R9 L8 TX2-A+
IO_L23P_2 IO_L62P_D5_2
B13 H7 TX3-C+ D6 C13 TX4-D+ TX1-C- T9 L7 TX2-A-
IO_L7P_0 IO_L63P_SCP7_0 IO_L23N_2 IO_L62N_D6_2
B4 H9 TX3-C- C6 A13 TX4-D-
IO_L7N_0 IO_L63N_SCP6_0
VCCO0-LX25 B9 GND J5 TX1-B+ L10 P4 TX2-E+
VCCO_0 IO_L16P_2 IO_L63P_2
D10 J8 TX3-E+ B8 F10 PNX-SPI-CS-BLn TX1-B- M10 T4 TX2-E-
IO_L33P_0 IO_L64P_SCP5_0 IO_L16N_VREF_2 IO_L63N_2
D7 K7 TX3-E- A8 E11 PNX-SPI-SDI
IO_L33N_0 IO_L64N_SCP4_0
K9 FPGA-SYS-CLK-LX25 M9 M6 TX2-C+
IO_L29P_GCLK3_2 IO_L64P_D8_2
D15 L15 TX4-A+ C9 B14 TX4-E+ CTRL-DISP3 RES 3K14 100R N8 N6 TX2-C-
IO_L34P_GCLK19_0 IO_L65P_SCP3_0 IO_L29N_GCLK2_2 IO_L64N_D9_2
G13 L2 TX4-A- A9 A14 TX4-E-
IO_L34N_GCLK18_0 IO_L65N_SCP2_0
VCCO1-LX25 J15 M8 R3 IK01 RES 2K01 100n
IO_L65P_INIT_B_2
K13 VCCO_1 N13 TX4-B+ B10 D11 PNX-SPI-CLK T3 3K07 10R CSO-B-LX25
IO_L35P_GCLK17_0 IO_L66P_SCP1_0 IO_L65N_CSO_B_2
N15 P3 TX4-B- A10 D12 PNX-SPI-SDO
IO_L35N_GCLK16_0 IO_L66N_SCP0_0 FK07
R13 R10 T2 PROG-B-LX25
PROGRAM_B_2 3K05
R6 L11 DONE-LX25
CMPCS_B_2 VCCO2-LX25
N10 T1 P13 DONE-LX25
DONE_2 1K0
VCCO2-LX25 N7 T16
FK06
R4 VCCO_2
R8

D2
G4
VCCO3-LX25 J2
VCCO_3
K4
N2

7K00-4
7K00-2 XC6SLX25-2FTG256C0100
XC6SLX25-2FTG256C0100
BANK3
BANK1 1% IK02
RES 3K04 100R M4 J6
IO_L1P_3 IO_L43P_GCLK23_M3RASN_3
PX4B+ E13 J11 PX2CLK+ M3 H5
IO_L1P_A25_1 IO_L40P_GCLK11_M1A5_1 IO_L1N_VREF_3 IO_L43N_GCLK22_IRDY2_M3CASN_3
PX4B- E12 J12 PX2CLK- RES 2K00 100n
IO_L1N_A24_VREF_1 IO_L40N_GCLK10_M1A6_1
M5 H4
IO_L2P_3 IO_L44P_GCLK21_M3A5_3
PX4D+ B15 J13 PX4CLK+ N4 H3
VAUX-LX25 IO_L29P_A23_M1A13_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L2N_3 IO_L44N_GCLK20_M3A6_3
PX4D- B16 K14 PX4CLK-
IO_L29N_A22_M1A14_1 IO_L41N_GCLK8_M1CASN_1
R2 L4
IO_L32P_M3DQ14_3 IO_L45P_M3A3_3
3D-LR F12 K12 PX1CLK+ R1 L5
IO_L30P_A21_M1RESET_1 IO_L42P_GCLK7_M1UDM_1 IO_L32N_M3DQ15_3 IO_L45N_M3ODT_3
G11 K11 PX1CLK-
IO_L30N_A20_M1A11_1 IO_L42N_GCLK6_TRDY1_M1LDM_1
P2 E2
IO_L33P_M3DQ12_3 IO_L46P_M3CLK_3
PX4C+ D14 J14 PX3CLK+ P1 E1
IO_L31P_A19_M1CKE_1 IO_L43P_GCLK5_M1DQ4_1 IO_L33N_M3DQ13_3 IO_L46N_M3CLKN_3
10K

10K

PX4C- D16 J16 PX3CLK-

IO_L31N_A18_M1A12_1 IO_L43N_GCLK4_M1DQ5_1
N3 K5
IO_L34P_M3UDQS_3 IO_L47P_M3A0_3
7K00-5 PX3D+ F13 K15 PX2E+ N1 K6
IO_L32P_A17_M1A8_1 IO_L44P_A3_M1DQ6_1 IO_L34N_M3UDQSN_3 IO_L47N_M3A1_3
3K10

3K11

XC6SLX25-2FTG256C0100 PX3D- F14 K16 PX2E-

IO_L32N_A16_M1A9_1 IO_L44N_A2_M1DQ7_1
M2 C3
JTAG PX4E+ C15 N14 PX1E+ M1
IO_L35P_M3DQ10_3 IO_L48P_M3BA0_3
C2
IO_L33P_A15_M1A10_1 IO_L45P_A1_M1LDQS_1 IO_L35N_M3DQ11_3 IO_L48N_M3BA1_3
C14 PX4E- C16 N16 PX1E-
TCK IO_L33N_A14_M1A4_1 IO_L45N_A0_M1LDQSN_1
L3 D3
IO_L36P_M3DQ8_3 IO_L49P_M3A7_3
DBG C12 PX4A+ E15 M15 PX2B+ L1 D1
TDI IO_L34P_A13_M1WE_1 IO_L46P_FCS_B_M1DQ2_1 IO_L36N_M3DQ9_3 IO_L49N_M3A2_3
1K01 PX4A- E16 M16 PX2B-
IO_L34N_A12_M1BA2_1 IO_L46N_FOE_B_M1DQ3_1
1 FK01 A15 K2 C1
TMS IO_L37P_M3DQ0_3 IO_L50P_M3WE_3
2 FK02 PX3E+ F15 L14 PX2D+ K1 B1
IO_L35P_A11_M1A7_1 IO_L47P_FWE_B_M1DQ0_1 IO_L37N_M3DQ1_3 IO_L50N_M3BA2_3
3 FK03 E14 PX3E- F16 L16 PX2D-
TDO IO_L35N_A10_M1A2_1 IO_L47N_LDC_M1DQ1_1
4 FK04 J3 G6
IO_L38P_M3DQ2_3 IO_L51P_M3A10_3
5 FK00 P14 PX3C+ G14 P15 PX1D+ J1 G5
SUSPEND IO_L36P_A9_M1BA0_1 IO_L48P_HDC_M1DQ8_1 IO_L38N_M3DQ3_3 IO_L51N_M3A4_3
6 PX3C- G16 P16 PX1D-
VAUX-LX25 IO_L36N_A8_M1BA1_1 IO_L48N_M1DQ9_1
7 8 H2 B2
100n DBG

IO_L39P_M3LDQS_3 IO_L52P_M3A8_3
PX3A+ H15 R15 PX1C+ H1 A2
IO_L37P_A7_M1A0_1 IO_L49P_M1DQ10_1 IO_L39N_M3LDQSN_3 IO_L52N_M3A9_3
2K02

PX3A- H16 R16 PX1C-

IO_L37N_A6_M1A1_1 IO_L49N_M1DQ11_1
G3 F4
IO_L40P_M3DQ6_3 IO_L53P_M3CKE_3
3D-VS G12 R14 PX1B+ G1 F3
IO_L38P_A5_M1CLK_1 IO_L50P_M1UDQS_1 IO_L40N_M3DQ7_3 IO_L53N_M3A12_3
3D-LED H11 T15 PX1B-
IO_L38N_A4_M1CLKN_1 IO_L50N_M1UDQSN_1
F2 E4
IO_L41P_GCLK27_M3DQ4_3 IO_L54P_M3RESET_3
PX3B+ H13 T14 PX1A+ F1 E3
IO_L39P_M1A3_1 IO_L51P_M1DQ12_1 IO_L41N_GCLK26_M3DQ5_3 IO_L54N_M3A11_3
PX3B- H14 T13 PX1A-
IO_L39N_M1ODT_1 IO_L51N_M1DQ13_1
K3 F6
IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L55P_M3A13_3
R12 3K13 47R SCL-SSB-550 J4 F5
IO_L52P_M1DQ14_1 IO_L42N_GCLK24_M3LDM_3 IO_L55N_M3A14_3
T12 3K03 47R SDA-SSB-550
IO_L52N_M1DQ15_1
B3
IO_L83P_3
L12 PX2C+ A3
IO_L53P_1 IO_L83N_VREF_3
L13 PX2C-

100n
IO_L53N_VREF_1
M13 PX2A+
IO_L74P_AWAKE_1
M14 PX2A-

RES 2K03
IO_L74N_DOUT_BUSY_1

3 2011-12-29

FPGA, I/O banks 2 2011-09-29

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2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 127

10-3-35 FPGA, supply & control

FPGA, supply & control

B10B B10B
5K20 FK20
+3V3 VAUX-LX25
30R

RES 2K20

2K21

2K24
2K22

2K23

2K25

2K26

2K27

2K28
100n

100n
100n

100n

100n

100n

100n

100n
1u0 +3V3
5K21 FK22
+3V3 VCCO3-LX25
7K20
30R 3225

4
2K37

2K38

2K39

2K40

2K41

2K42
100n

100n

100n

100n

100n
1u0

IK20 3K20 IK21

1 3 FPGA-SYS-CLK-LX25
VALUE 47R

2K2T

100n

2
5K22 FK23
+3V3 VCCO2-LX25
30R
2K45

2K48
2K43

2K44

2K46

2K47
100n

100n
100n

100n
1u0
1u0

3 6K20 DBG 3K21 DBG +3V3

LTST-C190KGKT 470R
DONE-LX25 1 7K21
PDTC144EU
5K23 FK24
+3V3 VCCO1-LX25 2 DBG
30R
2K2G
2K2C

2K2D

2K2H
2K2A

2K2B

2K2F

2K2J
100n
100n

100n

100n
100n

100n
1604
1u0
1u0

1 CCLK-LX25
CSO-B-LX25
2
3 MOSI-LX25
4 MISO-LX25 MISO-LX25
PROG-B-LX25
5
+3V3
6
7 8
5K24 FK25 FK26
+3V3 VCCO0-LX25
502382-0670
30R
2K2M

2K2Q
2K2N

2K2R
2K2K

2K2P

2K2V
RES 3K22
2K2L

100n

100n

100n
100n

100n
100n
1u0
1u0

4K7

3K23

10R
7K22
*
M25P40-VMN6TP

8
VCC
FK27
MOSI-LX25 5
D Q
IK22
2
FK21 FK28
+1V2-LX25 +1V2-LX25 CCLK-LX25 6
C
FK29
CSO-B-LX25 1
S
2K30

RES 2K31

2K34

2K35

2K36
2K29

RES 2K32

2K33

100n
100n

100n
100n

7
1u0

1u0
1u0

1u0

HOLD
3
W
GND

4
FK30

+5V

2K3A +3V3

1u0 RES

8
7K24 7K23
RT9025-12GSP M25P32-VMW6TG
4

VDD VCC
+1V8 3
VIN VOUT
6 +1V2-LX25 5
D Q
2
32M
2 7 6
EN ADJ C FLASH
2K3C

2K3D
2K3B

1n0
10u

10u

1 1
PGOOD S
cK3A

10 5 3
VIA NC W
GND
GND HS FK3A 7
3K3A HOLD
6SLX9-4MB-M25P40
8

SENSE+1V2-LX25
VSS
4K7 1%
10K 1%

6SLX16-4MB-M25P40
3K3C
3K3B

68K

4
6SLX25-8MB-M25P80 ---16MB-M25P16

3 2011-12-29

FPGA, supply & control 2 2011-09-29

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2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 128

10-3-36 Layout top

1A05 1A04
1M95 1M99 1J22 1M54
1T71 9C08
1C03 1C86

2C95
1C04

2C7K
9C07

5C57
2C7G

2C96
9C09

2C7L
3C7G
2C7N

5C53
3C98
2C85 2C84 2C83 2C7M

3C70

2C94
2C7F

5C56
3C7H
3C99

3C83

3C81
5C55

1C85 2C71

2U85

2U86

2U87

2U88
2U81

2U82

2U83

2U84
9C06
2C70

5C54

3C7F
3U71

2U54

2U47

2U68

6J25 6J24
6J22 6J23
1D02
3U85 3U84

1D52
2D70
2UD4

7U40
7J21
3U64 2U8D

2U45

3U42

3U45

2U46
1J02

6U40

2UD3
3UD1

1U40
7UD0

3U81
2U53

3U65

2UD6
2UD7

3U43

2U44
2D98
1D50

2UD2
2UD1
2UD0
2U55 5UD0

3U63
3U72 3U60 3UD3

3UD5

3J06
3J07
1D51
3U73
3J26
3UD4 2J02 2J2K
3U62 6J21

7U41
2U71

2D87

3U83
3U80
7U48

2UDD

2UDC
2UDA

2UDB
3U61

5UD1
3U82

6UU1 3UU4

2UDH

2UDF
1UU0 2UU3
2UU2

2U20
5U02

5U03

2U24
2U23
2U25
7J01
2U19

3U23
2U17

2U18

2UD9
2UD8
2UF0
5UD3
2UF1

2UF4

7UD1

1K01 2UB6
7U01 7U04 7U02

5UD2

2UF3
3UF2

3UF5

3UF4
3UF6

6U00
2U11

2U09

5U01

5U00
3U24

2UF7
2UF6
2UF8
2UF9
1P00

3J0C

3J0A
2J04
3J00

2J03
9U43

3J0G
9U44 3C96

2G91

2G9E

2UFA 2UFB
2G9F 3K10

2G9D 3K11

2G9C
9G0G

1G51
2K02

7K20
7K00

2K2T
3G47

3G45
3G31
3G46

2G7A

2G79 3G48

2G7F
2G7D
3G34
3G41
3G40
3G44
3G33
2G26
3G39
2G7B
2G7C
2G76
3G37
2G75
3G2Y

9K02
2G77

3K12

3K06
3G2W
3G38

2TPF
2TPG
3G32
3G35

2F01
3K21
1604
6K20

6TP4
7K21

1TP1
3B11

2TPH
2TPK

3S95

3S96
3B26

6TP6
7B01 3B18

2B47
3B19

5TP5

2NN6
2TPC

7TP2

2TPD
2TPL
2TPJ

3S97

3S98
2S4P

3S93

3S94
7S00

1F52
3S91

3S92
7S0A

3B10

3NN0
3TPD
3TPB

3TPF

3NN1
7NN2

2NN7
3B08

1NN8
2NN8
6NN8
7B00
3B25

1NN2
3B16

2B46

2T10
3B17

6NN9
1G50

3B07

2NN9
2D60
2D57

1NN9
7T00
9S00
2S09

2T00
2T01
3S3Y

2T02
3S04

7S02

3S1R

3S1U

3S1S

3S1T
3S31

5T00
3F60

3N9C
3S02 3S01
7F58
9S01

3S23

3S29

3S24

3S28
2G98
3F59

2FLF

3S03
3S62 2T05

3F58
3S3Q
2G97

2N73
3B02
2F58

5T01
3S21
2G99

7B02

2T15
2T12
3S3S

2D5A 2D5C
FF28

1N10
2G96
3S1K

6N53
2S4C

3FLL

2FL2
2G92 3B23
3S1J

2FLG

3FLD
3FLK

3FLB
3S1B

2S3M
2S3Q
2S3L 3S6M 3S25

3S3R

3S2A
2G93 3B12 3S3T
2B44

2S4D

3S1L
2G94 3S3N
2F49 3F52 2F52

7S09
3S11
3B13

1N80
2N77
2G95

FF04
3D79 3D78 3D81 3D80 3S1C
3B00

3S3L

3FLN
7F52 7FL5

3NCU

3S6K
2D5B 2D5D
3B05

5D78
3S81
1D53 3S6N 3S19
1C30 1D01

3B24 3S80
2D78

1F10
2S4F 3S52

7B03
DS50
5D83 5D80

3S37

3S39
3B15 3S54
5D81

2B45
2D99

2S4G

3S3F
3B14 3S50

1FL5

2FL6
3S32

3S38
1D54

3S35

3S34
DBS8
1S02
3S3M
3S43
2D73
1D55

3S42

3S44
2S38

2S35
1P08
2D81

5D77 2D83 2FL7

3B04

3S36
3S00

3S2M
2D76

2S2W
2D91

9S06

1D56 5D72 5D71

2S33
2S30
3S3W

3S27 IS13 3N17

3KC3
2S2V
BS10
2S34
3S26

2S2T

3KC2

2S32
2S31
4S14

7RC2
2FA0

2KCR
2S7M
2S7L
3S6J

2S7K

2S7H

2S7P
2S77 3S4V

3S4U
5D75

7S08

7KC0
2S87
3S4J 2S7J
2S78 3S4W

3S4P

2S7N
2D55

3S4L

3S4K

3S4T
5D01 3S13

3S59
2RC6
3S4R 3F65
2D56

2KCK
5D74

5D76

3F64 3KC1

3S53 3S12

3KC0
1F01

3KC4
2D89

5D00

1KC0
2S41 2S4M

2KCC
2D71
1N87
2N07

3N28

2RB1
5D79

3RA0
6N47

5N08 2N62 3RA1

3KC7
3KCB

3KCA
3KC9
5N02

2T20
2KCB
2N57
5D70

3KC8

2KCG
5N0C

2KCD

2KCJ
1F51
3N22 3N25

2KCE
2KCF
3N51

1FA0
1P07
5N01
2N56

1FA2

5KC1

5KC0
3D74 3D75 3N80

1N88

9KC1

9KC0
9N42
2D94

2D95

2D80 2D82
7N10 3N64
2N05

3N27

3KA0

3KA1

3KA3

5FA6

5FA7
3N82
2D75 3FA3 3FA4
3D73

2N71

9FA1 9FA0
3N81
1FA1
3N39

2N09 2N72
3D72
2D88

3FA2

3FA1
2D61

2NCN 2NCM 5KC8 5KC9 5FA4 5FA5

5N04

3N97

3N90

3N89

3N87

3N67
3N96
2N59
7D60
2D64

6N43 2FAH 2FAG 2FAC 2FAB 2FA9 2FAA

7RA1
3N66
6N06

6N38

6N52

6N51

6N40

6N44
2D79

3NCM

3NCN
2N39

2N40

2N68

2N67

2N27
2D85

3N65

1N70
3N72

3N35

3N34
5N03
2N58

3N53
3N68
3N29

2D67
2D54

9D51

IN45 2NCQ 2NCP

1N86

2D5F 2N08 3N30

2N54

2N55

3S83

3S84

2D77
3D54
2D53

1N09

1VA4

1VA8

2D69 1N85

5RA1
1N28

3D52
2D52
7D50 1N29
1C22

1N38
1N43
3C72

3NCK

3NC3

3NC5

3D57
3D51
1C20

2D50

3D50
1C21

2D51
2NCX

2NCY
1N37

3NCJ

6D60

1N06
2C97
2RC9

1N00
1N42

2C78 3C77 3FA0

2NCZ

2C82 3C79
6D61

3D83

6C05
7D80

1N39

2C90
2D86

2D72
2D68

3D58

9D54

3D71

2D74

9D52

9D53

3D55

3D56

2C77 3C76 2C93

2RBP 2RBS 2RC7 2RBK

2RC8
2RCA
2C99

2C91

3D76
INC8 2RBN 3RB1 2RBR

3C97
3D84 2D39
3D77

2RBV
1P05
2RBA 2RBC
2NCW

2RB5
9RB6
5D84

2RBL

3FL7
3NCA

3RB0

2RB7
5NC3
2C86 3C94
2NC8

2RB9 2RBB
9RB7
2FA5
2FA6

2NC3
5D85

3RB3
2C87 3C95 2N37 2N36
3FL8
6N20

7NC1
6N19

2C72 3C71 3N20 3N21 9RB9 9RB0

2RBU
2C7B 3C73 2N38 2N35 2FLC
5NC2

2RB6

6RA0
IC75

1RA0
2NC2

2RB4
3NCH

2NC1
2C7C 3C7A 3U68 2C81

7RA0
1F00

2RBE
3FC5

2NCC

2C80 3C78 3U41 9FC2

2RB3
3FC4

6FC1
6FC5
7U42

9U41 9FC1

6C07 IN43
6FC3

6FC4
3FC7

2N04

2N06
2N80

5N73
6FC6
3U59
3U74

3FC6

6N09

6N03

2RBF
2RB8
6N23

9FC6 9FC5
3N44

2N24

3N31

3N32
6FC2

3N62

2N45

2N76

3N43

3N42
6FC8
3FC1

3FC2

9FC3
6FC7

6N32

6N30

6N29

7N03
3N75

3N74

2N79

3FC3
3N03

3N02

2FC5

2RBD
IC74 9FC4
6N22
1N23

1N22

2RBW
2RBY 9RB8
5N77

2RB2
2N44

2N75

2FC3 2FC4 2FC2 2FC8 2RBT

2FC1 2FC6 2FC7

2RBM

2RCB
1FC6 1N55 2N18
1N12 2N15
1N25

1FC3 1FC4 1FC2 1FC1

1N19 1N18 2N91

2N88
1N54

1N31

1P06
2RBG
5RA2

1P04 1P03 1P02

2RBH

2RBJ
1R01
1FC5

1N05 1VA1

3 2011-12-29

Layout top 2 2011-09-29

3139 123 6531

19220_079_120229.eps
120229

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 129

10-3-37 Layout bottom

FC77 IC7A
IC7G IC7D

FC98
IC79
FC72
FC9L FC9K

FC99
FC96 FC97 FJ27
FC75

FC73 IC78 FJ26 FJ29

FC71

2J50 3J31 2J51

FC9F
FU7A FU7B FU7C FU7D FU7F FU7G FU7H FU7J FU7K
FC74

7J26
2U89 FU58
IUDC IUD3 2U50
FU59 FU60 FU63 FU75
2U49 FU66 FU51 FU52 FU55

3J24 2U56 IUD0

3UD0 IUD7

IJ22 FJ30

FJ21
FC76 FU48
FU77

IUDH
2UD5

3UD2 IUDA
FU76 1U40 IU56 FU67

FU53
IU55

3J23
IU48
2UDG IU49
IU51 2UU4

IUU3
FUU0
IUD6 FU72

7UU3
2UU0 IUU0
FJ06
3J21 FJ04

9UU1 9UU0

7UU2
IUU5

5J23
FC85 3UU3

7UU0
FC86

2J2B
2J49
FJ02
IUU4 IUU2

2J2A
2J32
2J22
2J21
5J20
2J48
2J47
7J25

7UU1
2UU1

3UU2
FUU1
FJ24

FUD3
FJ28
IUU1

2UU5

3UU6
FJ05 FUU2

2F05
3J02

9UU2
FJ01

2F04

3UU1
FJ03
IJ01

3UU9

3UU7
3UU8

3UU5
3J01 2J46

7F03
7F04

2U06
IU03 9UU3

5J24
2J45 2J33 IU22 7U00 2U03 3U10 3U19
3U00

7UU5 7UU4
FJ25
9J01 FU01 3U22 2U07 2U08

3J09
FU73
3U01

7J20
2U01 IU24 3U08 3U09 3U18 3U17

2J2C
2J2F

3U04
7J24
2J2M FJ22
IU05
FJ07 IU20 IU06
IU04 FU05
IU15

2U21
2J29

2J34 2J23
2U02 IU07

1J21
IUDG

3J28 3J30
IU23

2J2N 2J2P
IU08

3U27

3U05
2J2G IU13
3J27
7J22 IU16

7UC0

2U22
3J25 IU11 3U14

7U03
IUD2

3U11

3U28

IU12
2J24 IUD1
3J29

IUDF
2J2H

7J23

IUD8
3F66 IF04 3UF1 IU10

3F53 3F67

3J03
3J04
2J44
2J43
2J42
5J22
2J2D IU17

3S72
IUD4
3F54 3F08
7F53 IF55
2UF2

FU02
FU06

2J28

7F54
3UF3

2J37
2J41

9J02
FJ20
2J26
2J01

7F05

2UA4
IUD5
FF58 9F51 IJ02 2UF5 IUD9 IU09 IU14 IU19 IU18

2F06
FU04

7F00
2F00
3F11
2J27

2J31
2J30
3J05
2F53
3F69
IF57

3U20

2U10

3U21
2J35
3F68 FJ23 5J21

IU25
IF56 IU01

2J36
2J40
2J25
2J39
2J38
IU02

2U05

2U00
FU00
9J21 2U29

3U02
2U04
3U03
FU09 FG2P

6UA0

3F14
3F13
IU21

3USG
9USA

9USB
FUD2

2UB1

9UA0
FU08
3UB0

3USD

9USC
2USA

3USF
FUA4
FG2N

2U16
2U15
IF08

2U12
IUSA IUSB

3F01
2U14 2U13

7USA

3F02
IUSC FG1V FG1W
3F03
2UB0

2F02
3F09 3F10 FK01
FG1U FG1T
FUA0 FF62 FK02
FK04

FU03
FG1S FG1R

7F01

2K2K
5K24

2K2L
FK00

7UA4
2K03

FG2D

FG2C
2K2N
2K31

FK3A
FK25
FK03

2K2M
2K2R
2K30

6USA
3USC
3USB
2K2Q
3K3C 3K3A

2K28

2K20
FK24 2K29 FG2A FG2B
5K23 FK21
3K3B 2K3D 2K3C

2K2H
2K2B

2K2A
3USA

5K20
FK20

9K01

2K40
FK22 FG28 FG29

2K37

5K21
2K24

7K24
2K21
2K2C 2G29

2K2P
2K36
2K34 2G28

2K27
2K38 FG27 FG26

7F02
IF05
IF07
IK20
3F04 3F05 2K2G 2K33 2K22
2K42
2K32

2K35
FUA3 IK21 3K20 FG25 FG24
IF06

2K41
2K26

2K00
2UB3

3UB2

3UB3
IK02
2UB2 2K2D 2K25

2K3B
FG23 FG22

2K39
2K2J
2K23

2K3A
3K04

3UB1

2F03
FG21 FG20

2K48

2K47
FK28 FK27
FUA5 3G42 FG2M

FG1Y

FG1Z
7K23

2K46

FG2L
IK01
2K01
2K2F FK08

3G43
3K08
FG2R

3K13

3K03
3K07 FK07 FG2U FG2F
FG2G
2K45 FK09

FG2H
2K43

5K22
2K44 FG34

FK29

7K22

3K23
2K2V

3K22
IK22 FK23
FK26

3K05
3K14
FK30

ITPG
6TP5
FK06

2B43
ITPJ

2B39
3TP3
IK00
FTPA 2B32

2B27
FB00 2B34

2B33

2B35
6TP1

ITP4

FS2Y
FS2W
INN6
3F07

2B29
3S66

3S68

2B28
FS31
ITPF
2NN2

2NN5
IS08 3B09
FF63 2B30

3S0B
3S0F

7S01
2B31

3F63

2S12
9S11

3F62
FF61
7NN1

3S0D

9S10
3S65
IS0A IS0C
2S0A

9S13
3S67
ITP2
3F12

3S0C
2S0B
9S12
2NN4
2NN3

2B42

FG2J
3NN6

INN5

IS09 3B27

3S0A
IS0B

3S0G
3S6B 2S89 3S58 2B22 FG1P FG1Q
2NN0

2B23

2B38
3S6C 3S5W

2B25

3B21
2NN1
2B24 FG1B FG1A
IS00

3S06
9S08
INN7 3NN2 INN8 FS01
2S4N

2B26
3S61
2S66 FG19 FG18
3T00
3T04
2T13
2T14
3T06
3T05

3S07

2S17
FT07
3S6G

2S25
FNN2 3S1V 2B20

3B20
FNN1 2S61
3NN5

2B19
3B06

3S15
3S60

2B21
FG17 FG16
2T03 IT24 3T01 2B18

2S26
3S6L
3S6F
3T02 2T04

2S67
3S5Z
3S6D IS26 FG15 FG14

2S63
IT04
3S5Y

5S88
IT01
IS25 2S62
IS3K
IS17 3S57 2S5M FG13 FG12

2S6P

2S4S
3S2F FF56 FF55

2S5H
3S2G 3S56 5S94
3S1W
2S57

2S5P
2S4W

FG1M
FG1N
2S64
3S69
3S6A 3S6W 3S6V

2S5J

3S6Q
FNN7 2S4Y

3F06 2S21

2S60
3S1X

2S6F
5S85 IS3Q 5S83
3S1A FG1K FG1L
5S80 3B22

3S6P
2S5G

5S93
IS58

5S89
5S92
3S30 ID55 ID54

2S5A
IT00 2S27 FG11 FG1J

5S87
3S33
FF57

5S81
2S6R

2S23
2S5D
2S5K

2S6M

2S59
5S82
IS3S
2B10 FG1G FG1H
IT02 IT18 3S82

2S58
2S28
2S6L 2S6D 3S0V

2B16

2B14
IS42

2S5C
IF59 2S43

2S6K
IS04 2S65

2S6H
5S95
2B37 FG2T
2B15 5D51 5D50 FG1F

IS10

2S68
FS54

5S90
5S04

2S53
2S55

2S56

3S20
2B17

2S24
2S52
2S5B FG33 FG32

2S2A
FN5H FF29 FS64 2S20
FG1C FG1D

2S6A
FT06 IS1L FS02
IS1K

3S0W
3S64

9G0K
2S4V
2S6N

2S37
2S6B 2B13
IS01 3S22
FG31

2S11
2SHW

2B12

2B11
FN55 2S6C 2S51 2S6G
2S4T
3B01 2B09

3S45
IF54 IS05 9S09 2S4U
3C74 2S46 FG30

2S50
FF03

2S4Z
2S15
IS3L

3S40
IS16

2B40
FL32 3S1F 3S2K

2S45
3S41

3S4A
3S1P

3S2V 3S55 IS4Z

IS1C
3S2H IS5F
2S4R

2S29
2S4L
3N73 IS5E

2S13

2S3G
2FL8

5S84
7S20
2FLH

IS1A

IS4W
IN51 2S10
IFLA 2FL9 FS0Z
IS3B 3S5S
2S4Q
2S4K

2S3H
2S75
3FLC

2S36
3FLP

FD92

3S09
3FLM
FS57

FS15
3FLF

3S6H
2FL4
2FL5

3B28

3S5V
FS51 IS19 2B01

2B03
2FL1

2B02
3S75

2S2L

2B04

2B08

2B36
FS10 3S1G IS5D
FS11

2S3N
FS49 FS50 FS52 FS53 IS1B IS50

2S18
IS44 2S14
2S85 3S1H 3S2L

IS3D
3S10
IFLG FS44 FS0Y FD30
2S86
IS5H
2S3F

2S40

3S08
IS1M
3S46 IS2Z
2S84

2S19
3S2S FS08
3S5T

IS5J IS4V

2B07

2B05
2B06
FL37

IS3F
3B03 2B00

2S8A

3S5B
2S16

2S22

3S05
IS20

FL36
IFL4
IS3G

IS5G 2B41 FD95 FD33

7RC1

5FA0
7FA0

2S2R
IN05
IRC3

3S51
2RC5

2RC0
5RC0

2FA2 FFA1
IRC0 2RC2 IFA0
7RC0

IS12
FRC0

2FA1

5KC6 FD31
2KCP

2S2S
FF66

FD32
2RC3
DKC1 3S16 3S17
3F32

2RC1

FKC1
3S47

2KC2 IKC8 2KC6

3S85
3RC1 IRC2 IS1P
IFLK FF65 IS1J
2KC7
5KC5

FRC1
3RC2

2KC5

2RC4 IRC1
FL43
5KC7

2S42
3F34

FN5C
IS1R IS1Q
3KCE

3S86
2FA4 IS1H 2FLD

3S5F
2KC3
2FLA

FS13
2KC0

FFA0 FL39
FL38
9RC2

IKC9 IS0R
3S3P IN10
5N80

2N98
IN59

3FLJ
IKC1
2KCS

FL30
3S49

3S1D

FF64
IKC4

3S87
2N97 2N99

3NB3
DKC0 IN60 IN09
2KC4 2KC1 IKC7
2N81 IN70
FL31

3N98

3N26

2N60
7N05
2KCH

3KC6

7N06
3N19 FN30
3NB1
FFAC IN91
IKC5
3N18
IKC0 IN92 ID51

FL42
IKC6
IKC2 IN89 3N06 IN96 3NB6 FN60
FFAB FN28
3RA7
7KA0

3N33

2N70
IKC3 ID52
IN13
3N48

3NA2
2NB3
IFA5

IN63 IN26
3RA8 3N45

2N66
IRA1 FN61
2NB1

3NA1
9N01
2N74

2RCE

3N95 3N99
FFA5 IFA6
2RAN

FL41 3FAA IN90 FN27 ID62 ID82

2T18 FRA0
IFA3
3FAB
AFA3
2RAP FFA6
7FA1 IN61
3KA4

3KA2
3FA7

3FA8

3FA9

3N71
FFA7

IRA0
3RA6

3FAC
FL47 FT09
2RAG

FN54 FN31
2RA8

3N69 ID94 ID93

2RAB

2FAD IFA4
2RAM
2RAA
2RA9

2RAL

FN5A FN5B
2RAC

2FLB IRA2 FN5G 3N70

FFA8 AFA0 AFA2
2RA7 FFA2 FFA3
2RAK

ID92
3FL2

7T03

2RAD
FL33

FN29
5RA0

2N48
2N49
FFAA
FN5D

2RAE ID95

IRA8
2RAY IN42
FN34
IN39 3N40 FN01

AFA1 AFA5 IN38

FN56

ID50
3FL4

IN44 ID53
2RA6 FN49 FN50 2N63 IN07

2N53

2N52
FN02 FN03
2RCD 2RA5
2RAF IN64 IN32 IN33

FN33 FN32
IFLJ

IRA3 FRA6

3N0A
2RAV AFA4 ID63
2RA4

2N0L ID81 ID70

3RA3

IN0A
3RA4

ID75
2RAJ

FRA2

2RAW ID80
FRA5

2RCC IN0B ID69

2RAR

FC89
2RA3 2RAU
5T03

2T16

ID66
2T17

FRA1

ID77
ID56 ID65
2RA2

FC9D
3RA2
2RB0

2RAS
2RAT
2RA1

2RA0

FRA4
FC88
ID87 ID61
2RAH 2C76
FD50 FC87

7D61
FRA3 3C75 FC91
3D82

ID78
6C03

ID79
FD67
FD66 FC94
2FAF 2FA7 FD34
2FAE 2FAK 2FAJ
ID84 2C79
FFA4 3FAD 3KCC 2FA8 FFA9 5FA1
6C02 FC90

IC7H FC9A

IFA1
IRA9

IC73
FC95
IFLH FC9B
IU43
FC92
IRA4 IU45

3U53

9U42
3U70
FNC9 FNCH FL46 FL40
2NCV

FC9G
2NC0

5NC0

5NC4

3NCT FN57 FNC3 FN51 FN42 FN48 FFC6

IRA7 2NC7 IU47
3NCP 7U43
7NC2

3U69
9NC0

FNCU FNCQ FNCV FFC4 FFC8 FFC1 FFC2 FFC7 FC9H

FFC5 FFC3
INC6 INC5 INC7 FNC0 FNCS
3NC6 3U75
FNA1
2NC6

FC9J
2NC4

FNA2 FN83
7N02
FNCY

9NC2 3NCR FNA3

FC93
2N84
IU44
6NC2

FNA8
FNA4
3NCL 7NC0 3N23 FNCT
3NC7
IN18
FNA7

FNA6
5N76

6N26
3NCD
9NC3

FNCR
INC4
5N74 2N86

6N28
6NC1

3NCF FFC9
FRA7 FNA5
FN43 FNCG 2N85

3N78

3N79
3NC1
3NCG

2N14
FN73
2NCU
2N83

3N76

3N77
FRA8 FN84
FNCZ FNC5 FNC6 2N12
IN11 FNC4
FNC1 FNC2
FNCP FNCB FNCJ
FN58 FN74
FNCW FN75
FN85 FN71 FN80
1N18 1N19 FN81
FN82
FL45 FL44
FNCM

FNCF

FNCK
FNC8
FNCL

FNCA FNCN FNCC

FNCD

3 2011-12-29

Layout bottom 2 2011-09-29

3139 123 6531

19220_080_120229.eps
120229

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 130

10.4 B 313912365333 - 313912365334 SSB

10-4-1 Power connectors

Power connectors
B01A B01A
* 1M54 FU7A
1 +3V3 +3V3-STANDBY
FU7B 3U84-1 1 8 100R BL-DIM1 ** To be connect directly to 1A04 with 3mm Track width
2
FU7C 3U84-2 2 7 100R BL-DIM2 ** 1M99
3
FU7D 3U84-3 3 6 100R **
4 BL-DIM3 1 GND-AL LED-2

RES 10K

RES 10K
FU7F 3U84-4 4 5 100R BL-DIM4 FU48
5 2

3U74

3U75
FU7G 3U85-1 1 8 100R BL-DIM5 **
6
FU7H
3 GND-AL ** +5V +3V3-STANDBY
3U85-2 2 7 100R BL-DIM6 +12V-AL
7 4
FU7J 3U85-3 3 6 100R BL-DIM7 IU43
8 5 9U41
FU7K 3U85-4 4 5 100R BL-DIM8
9 6

* AL 2U89

* AL 2U56
10n

10u

RES 10K
7

3U68

3U69
2041145-9

10K
1n0
1n0
1n0

1n0
1n0
1n0

1n0
1n0

8
IU44 3U41 3U59
2041145-8 IU45 LED2 LED2
LED-1 9U42 10K RES 10K RES
2U81
2U82
2U83
2U84
2U85
2U86
2U87
2U88

4 Pin stuffing variant 1M11 RES

GND-AL 7U42 RES +3V3
RES
RES
RES
RES
RES
RES
RES
RES

6 Pin stuffing variant 1M1B +12VIN BC847BW

IU47 3U70 3U53
7U43 LED1 LED1

RES 2U8D
BC847BW

10n
10K 10K

+3V3-STANDBY
2U47

2U68
10n

1u0

STANDBY-1 3U71
STANDBY
3U82
100R
2U54

10n

1K0 RES
7U48-1
BC857BS(COL) FU77
1 3U83-1 8 ENABLE-3V3-5V

6
100K

4 3U83-4 5
100K
2
2U71

100n
cU40 +12VD
+12VIN 1U40 +12V

T 3.0A 32V +3V3-STANDBY

2U50

10n

3
1M95
FU58 100HZ 3D 100HZ 2D LGD 50HZ
1
2
FU59
FU60
* with LX4 & LX25 3D TM100 7U48-2
BC857BS(COL)

5
3
3U42 x x --

6
4 7U40-2 3U83-3

3U62-3
9U43 x -- -- 2 3U83-2 7 6 3

10K
FU63 BC847BPN(COL)
5
FU75 9U44 -- x x 4
100K 100K
6 FU66 IU48

3
7 +12V-AUDIO
FU67 5
8

4
3

3U62-4
9
1 3U60-1 8
2U49

FU73 ENABLE-1V8

10K
10n

10
BL-ON-1

PDZ6.2B(COL)
11 IU56 22K

RES 10K
2

3U61
BL-DIM-1 3U81 10K BL-ON
+3V3

5
12

3U62-2
6U40
BL-I-CTRL-1

10K
13 IU49
POWER-OK-1 BL-PWM
14 6

2
7U40-1

7
3U60-2
IU51
1-2041145-4 FU51 3U45 100R
* 9U43 FU72

22K
BL-DIM1 BC847BPN(COL) DETECT2
2

* * 9U44
3U72
FU52 3U42 100R 1

1K0
BL-DIM 7U41-2

7
1u0 RES
3 BC847BS(COL)

6
2U55
FU53 3U43 100R BL-I-CTRL

3U60-3
FU76
5 3U60-4 4 ENABLE-3V3n

3U80
5

4K7

22K
IU55 3U73 3U62-1 22K
FU55 3U64 POWER-OK 4

3
+3V3-STANDBY
1 8
10K 6
1K0 3K3

3U63

RES 10K
7U41-1
100p

1n0

10n

BC847BS(COL) 2
2U53

3U65

100K

1
1n0

2U45
2U44

2U46
RES

4 2012-04-23

Power connectors 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_031_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 131

10-4-2 Interface connectors

Interface connectors
B01B B01B
+3V3

3C74

100K
RES
5C56 IC79 1C04 FC9F 2C76
+3V3 V-AMBI
30R T 1.0A63V FC87 3C75 100p
LIGHT-SENSOR
2C93 100R 2C77
V-AMBI V-AMBI
RESERVED
+3V3 47n RES 3C76 100p
RES 2C7G

2C7F
To sensor & control
1u0

1u0
RC

PDZ5.6B(COL)
IC73 100R 2C78
**

6C02
1C22

RES
FC88
RES IC74 100p 1
3C77

3C7F
LED-2

RES
1A05 1A04

10K
FC89 2
1 100R FC90
1 IC7A RES 9C08 FC71 3
RES 5C57 30R 2 9C06 FC91
2 3C7G 4
3 FC72 33R AMBI-SPI-OUT-MOSI +3V3-STANDBY FC92
3 5
4 2C7M 10p 2C79 FC93
4 6
5 FC73 3C7H 33R AMBI-SPI-OUT-CCLK FC94
5 IC7D 7
6 FC74 5C55 30R 2C7N 10p IC75 +5V
6 LED-1 3C78 100p 8

PDZ5.6B(COL)
7 FC75 AMBI-TEMP 3C70 100R AV2-STATUS
7
8 2041145-8

RES 6C07
8 100R 2C80

2C71

2C70

2C81
100n

100n
9

1u0
9 GND-AL
10
10 RES 2C94 100p
11 FC76
11 FC95 3C79
12 GND-AL KEYBOARD
12 IC7G RES 9C09 100n
13 9C07

RES
13 1C86 10R 2C82

6C03 RES
14 FC77 RES
**

PDZ5.6B(COL)

PDZ5.6B(COL)
14 +12V-AL
15 1C20 1C21
15 T 2.0A 63V 100p
FH52-18S-0.5SH

6C05
16 FH52-11S-0.5SH
16
RES 2C7K

RES 2C7L

2C95

2C96
17 1
10u

10n

10u

10n
17 1
18 2
18 2
19

19

20 20 3
3
4
4
FH34SRJ-18S-0.5SH(50) FH34SRJ-18S-0.5SH(50) 5
5
GND-AL GND-AL +3V3-STANDBY 6
6
7
7

2C90
IC7H 8

1u0
8
9
+3V3 9
10
10

**

** 2C91
2C99

100p
11

1u0
11
RES

* HOTEL TV * 1C03 12 13
12

**
**+T3C97 13

3C96
100R FC9L
* RES 3C98 1

4K7
RXD1-MIPS +5V 14
RES 3C99 100R FC9K 2
TXD1-MIPS
* 3 RES
0R3
FC9A
15
16
+5V 4 SCL-SET 3C94 47R
17
+12V 5 RES
FC9B 18
AMP1 6 SDA-SET 3C95 47R
AMP2 7 19 20
3C72 FC9D
8 3D-LED
9 10 100R

RES 2C86

RES 2C87

2C97

100p
502386-0870

10p

10p
RES 3C71 FC9G
1T71 TACHO cC01 IRQ-CRP
FC85 3C81 100R FC96
SCL-BL 1 RES 100R FC9H
TXD2-MIPS 3C73 47R
FC86 3C83 FC97 2
SDA-BL FC98 RES
3 3C7A FC9J
100R RXD2-MIPS 47R
4
5 6
2C84
2C83

10p
10p

502386-0470
TEMPERATURE

RES 2C7C
RES 2C7B

RES 2C72

100p
10p

10p
SENSOR

FC99

5C54
2C85

1u0

+3V3
30R
T 1.0A 63V
RES
1C85

RES 5C53 4 2012-04-23

+12V IC78
30R Interface connectors 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_032_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 132

10-4-3 DC/DC

DC/DC
B02A B02A
5U03 RES

30R
FU05 5U02 IU22
+12V
0R

7U02-1

2U24

2U23

2U20
2U25

2U19
10u

1u0
10u

10u

10u
SI4952DY
7 8
IU10
2
12V/1V8 CONVERSION

1
3U11

3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6

22u
3U23-4

3U23-3

3U23-2

3U23-1

2U15

2U16
47R

47R

47R

47R

47u
7U02-2
SI4952DY

1
5 6
IU09
4 IU23

2U17

1n0
IU15
7U01
SI4778DY-GE3

2U18

1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3
2U00

3U14
10u

3R3
3R3

3U04
2U22
IU06 2U02 IU07
IU05 IU13 220p

3U28

10R
100n
2U01

100n

3R3
7U04
7U03 3U05 SI4778DY-GE3
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
3 1
12V/1V1 CONVERSION
1 1
ENABLE-1V8 10 EN DRVH 12
2 2
1n0 RES

5U01 FU01
FU06
2U03

+1V1 4 24 +1V1
1 1

STPS2L30A
+1V8 9 VO SW 13

RES 100u 2.0V

2 2 2u0

6U00

2U14
5 22

3U24-4

3U24-3

3U24-2
1 1

3U24-1

RES
3U20

2U12

2U13
8 VFB PGND 15

22u
47R

47R

47R

47R

10R

47u
RES RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 IU02
GND-SIG 12K GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5

2U11
RES

1n0
+3V3-STANDBY 3U00 RES 2U06
+1V1 GND
2U04

2U05
6

10u

1u0

10K 100n
3U01

IU18
10K
RES

GND-SIG

2U09

2U10
1n0

1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%

3U17

1% 330R

2U29

100n
RES
IU20

100p RES

3U19
2U08

3U18
5K6

1% 1K0
3U08 3U22 FU09 FU08
IU04 CU00
+1V8
330R 1% 1K0 1% IU21
RES 100p

CU01
1K0 1%
3U09

3U10

2U07

CU02
22K

CU03
GND-SIG GND-SIG GND-SIG
CU04
CU05

GND-SIG GND-SIG GND-SIG

GND-SIG

4 2012-04-23

DC/DC 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_033_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 133

10-4-4 DC/DC, 1.8 V to 1.2 V conversion

DC/DC
B02B 1.8 V to 1.2 V conversion B02B

+12V +5V

+3V3 7UC0
LF25ABDT
FUA4

1 3UB0-1 8

2 3UB0-2 7

3 3UB0-3 6

4 3UB0-4 5

RES 9UA0
1 3 +2V5
IN OUT

4K7

4K7

4K7

4K7
COM

22u 16V
2UA4

2UB6
CUA0

1u0
+2V5-LVDS
FUA0

2
PDZ5.1B(COL)
6UA0

2UB1

1u0
7UA4-1

4
VDD RT9025-12GSP
FUA3
+1V8 3 6 +1V2
VIN VOUT
2 7
EN ADJ
2UB0

2UB2

2UB3
10u

10u

1n0
1
PGOOD
5
NC
GND
GND HS FUA5
3UB1
8

SENSE+1V2
3K9
1%

1%
22
23
24
25
26

3UB2

3UB3
10K

82K
7UA4-2
RT9025-12GSP
VIA

18 10
19 11
20 VIA VIA 12
21 13

VIA
14
15
16
17

4 2012-04-23

DC/DC 3 2011-12-12

3139 123 6533 2 2011-05-25

1.8 V to 1.2 V conversion

19220_034_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 134

10-4-5 DC/DC, 12 V to 5 V/3.3 V conversion

DC/DC
B02C 12 V to 5 V/3.3 V conversion B02C

12V/5V CONVERSION
7UD0
RT8293AHGSP
5UD0 IUD3 3UD0 IUD7 2UD5
IUD0 2 1
+12V VIN BOOT
0R 1R0 100n 5UD1 FUD3
7 3 +5V
EN SW
2UD0

2UD1

2UD2
10u
10u

10u

10u
2UD4 IUDC IUD6
8 5

100u 16V

100u 16V
10K 1%
SS FB

2UDD

2UDC

RES 2UDH
3UD5

RES 2UDF
2UDB
2UDA
22u

22u

22u
22u
100n 10 6
IUDH
VIA COMP
GND
GND HS
SS2_GND

2UD6

3UD2
4

RES

10R
3n3
ENABLE-3V3-5V
RES 1n0

IUDA
2UD3

cUD1

2UDG
3UD1

RES 2UD7

470p
RES
15K

10n
SS2_GND

2K2 1%
3UD4
3UD3

12K
SS2_GND
SS2_GND
SS2_GND
SS2_GND
12V/3V3 CONVERSION
7UD1
RT8293AHGSP
5UD3 IUD2 3UF1 IUD8 2UF2
IUD1 2 1
+12V VIN BOOT
0R IUDF 1R0 100n 5UD2 FUD2
7 3
EN SW +3V3
2UD8

2UD9

2UF0
10u

10u

10u

2UF1 IUDG IUD5 10u

8 5

4K7 1%

100u 16V

100u 16V
SS FB

RES 2UFA

RES 2UFB
3UF4

RES 2UF8

RES 2UF9
2UF7
2UF6

22u

22u

22u

22u
100n IUD4
10 6
VIA COMP
GND
GND HS

2UF3

3UF3
4

RES

10R
3n3
ENABLE-3V3-5V SS1_GND

1K5 1%
3UF5

3UF6
100K
IUD9
cUD2
3UF2

RES 2UF4

2UF5
RES

470p
12K

10n
SS1_GND SS1_GND SS1_GND

SS1_GND SS1_GND

4 2012-04-23

DC/DC 3 2011-12-12

3139 123 6533 2 2011-05-25

12 V to 5 V/3.3 V conversion

19220_035_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 135

10-4-6 DVBS supply

DVBS supply
B03A B03A

5T00 IT00
+12V-DVBS
30R
7T00

2T00

2T01

2T02

100n
TPS54227DDA

10u

10u

8
VIN

STEP DOWN IT02 2T05
2 7
VFB VBST 5T01 FT06
100n +1V0-DVBS
4 6 IT18
SS SW 3u0

RES 2T15

2T12
1

22u

22u
+2V5-DVBS EN
3 IT24
VREG5
IT01 3T00 RES
VIA

2T10
GND_HS GND

1u0
68K

10
11
3T04 RES

1n0
8K2 1%

RES 2T03

2T04

10n
IT04 2T13

1n0

1%
RES 2T14 FT07

470K

3T01
RES 3T02

22K
GND-1V0 GND-1V0 22p
3T05
SENSE+1V0-DVBS
8K2 1%
GND-1V0 GND-1V0 3T06

68K

cT01

GND-1V0

22
23
24
25
26
+5V 7T03-2
+3V3 RT9025-12GSP
2T16
5T03 VIA
+1V8 7T03-1 1u0
RT9025-12GSP 18 10
4

30R
VDD 19 11
3 6 FT09 20 VIA VIA 12
VIN VOUT +1V2-FE
21 13
220u 6.3V

2 7
EN ADJ
2T17

2T18

RES 2T20
10u

10u

VIA
1
PGOOD

14
15
16
17
5
NC
GND
GND HS
8

4 2012-04-23

DVBS supply 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_036_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 136

10-4-7 Core voltage supply for DVBS demodulator

Core voltage supply for DVBS demodulator

B03B B03B

+12V +12V-DVBS
1TP1

T 3.0A 32V

+12V-DVBS

ITPJ

2TPD

2TPC
2TPL

100n
10u

10u
+12V-DVBS +V-LNB

5TP5
10u
7TP2

17
LNBH25PQ
VCC
ITP4
LX
3
ITPF 2TPJ

B230LA-M3
16
VBYP

RS1D
6TP6

6TP5
470n
21
VUP
6 +V-LNB
ADDR FTPA
20 ITPG
VOUT
SCL-SSB-550 3TPB 47R 7
SCL

B230LA-M3
1

2TPK

6TP4
220n
SDA-SSB-550 3TPD 47R 8 DSQ 5

47u 35V

47u 35V
SDA

2TPG
2TPH
2TPF

470n
10
19 11
DETIN
NC 12
F22-DISECQ-TX 22 13
DEBUG IN
DEBUG 23 14
6TP1 OUT
+5V 3TP3 24
2 26
FLT
27
1K0 LTST-C190KGKT 18 28
BPSW
ITP2 29
3TPF 9 VIA 30
ISEL
22K 31
32
GND_HS

33
PGND
GND
15

25

4 2012-04-23

Core voltage supply for 3 2011-12-12

3139 123 6533 2 2011-05-25

DVBS demodulator

19220_037_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 137

10-4-8 DDR

DDR
B04A +1V8 DDR2-VREF-DDR +1V8 DDR2-VREF-DDR B04A

2B08
100p

100n
2B36
2B04

2B05

2B06

2B07
2B00

2B01

2B02

2B03
2B40

100n

100n

100n

100n
100n

100n

100n

100n
47u

2B37
2B17

100p
100n
2B41

2B09

2B10

2B11

2B12

2B13

2B14

2B15

2B16
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B02

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
EDE1108AGBG-1J-F 7B03

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF
AT T-POINT DDR2-A1 H3
0
DDR2-A0 H8
VDD VDDQ

3B22
DDR2-A2 H7
1
2 SDRAM 0
C8 2
3B00-2
7 DDR2-D16 DDR2-A1 H3
0
1 3B04-2
DDR2-CLK_P DDR2-A3 J2 C2 3 6 3B02-3 33R DDR2-D17 DDR2-A2 H7 SDRAM C8 2 7 DDR2-D24
3 1 2 0
DDR2-A4 J8 D7 33R 3 6 3B00-3 DDR2-D18 DDR2-A3 J2 3B05-3
C2 3 6 33R DDR2-D25
240R 4 2 3 1
DDR2-CLK_N DDR2-A5 J3 D3 1 8 3B02-1 33R DDR2-D19 DDR2-A4 J8 3B04-3
D7 3 6 33R DDR2-D26
5 3 4 2
DDR2-A6 J7 DQ D1 33R 2
3B02-2 7 DDR2-D20 DDR2-A5 J3 D3 33R 33R 2 7 3B05-2 DDR2-D27
3B27 6 A 4 5 3
DDR2-CLK_P DDR2-A7 K2 D9 3B00-4 4 5 33R DDR2-D21 DDR2-A6 J7 DQ D1 1 8 3B05-1 DDR2-D28
7 5 6 A 4
DDR2-A8 K8 B1 3B02-4
33R 4 5 DDR2-D22 DDR2-A7 K2 D93B04-4 4 5 33R DDR2-D29
240R 8 6 7 5
DDR2-CLK_N DDR2-A9 K3 B9 3B00-1 1 8 33R DDR2-D23 DDR2-A8 K8 B1 33R 4 5 3B05-4 DDR2-D30
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B04-1 1 8 33R DDR2-D31
3B28 10 9 7
DDR2-CLK_P DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B12 DDR2-DQS2_P DDR2-A11 K7
240R 12 11
DDR2-CLK_N DDR2-A13 L8 DQS A8 3B13 33R DDR2-DQS2_N DDR2-A12 L2 B7 3B14 DDR2-DQS3_P
13 12
2B44 DDR2-A13 L8 DQS A8 3B15 33R DDR2-DQS3_N
33R 13
DDR2-BA0 G2 RES 2p2 2B45
0 33R
DDR2-BA1 G3 A2 DDR2-BA0 G2 RES 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
RES 3B01 F9 DDR2-ODT
ODT
DDR2-CLK_P 240R E8 RES 3B03 F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM2 3B23 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM3 3B24 B3
33R VSS VSSQ DM|RDQS
VSSDL
33R VSS VSSQ

J1
K9

E7

A7
B2
B8
D2
D8
A3
E3
VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
+1V8
+1V8
DDR2-VREF-DDR

DDR2-VREF-DDR

2B26

2B38
100p
100n
2B42

2B18

2B19

2B20

2B21

2B22

2B23

2B24

2B25
100n

100n

100n

100n

100n

100n

100n

100n

2B39
47u

2B35

100p
100n
2B43

2B27

2B28

2B29

2B30

2B31

2B32

2B33

2B34
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B00
H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1

EDE1108AGBG-1J-F 7B01

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF

0 VDD VDDQ
DDR2-A1 H3 DDR2-A0 H8
DDR2-A2 H7
J2
1
2 SDRAM 0
C8
C23B08-4 4 5
2
3B07-2
7
33R
DDR2-D0 DDR2-A1 H3
H7
0
1 C8 2
3B10-2
7
DDR2-A3 3 1
33R
DDR2-D1 DDR2-A2 2 SDRAM 0 DDR2-D8
DDR2-A4 J8 D7 3 6 3B07-3 DDR2-D3 DDR2-A3 J2 C2
3B11-3 3 6 33R DDR2-D14
4 2 3 1
DDR2-A5 J3 D3 3B08-2 2 7 33R DDR2-D2 DDR2-A4 J8 3B10-3 33R 3
D7 6 33R DDR2-D10
5 3 4 2
DDR2-A6 J7 DQ D1 33R 1 8 3B08-1 DDR2-D4 DDR2-A5 J3 D3 2 7 3B11-2 DDR2-D11
6 A 4 5 3
DDR2-A7 K2 D9 3B07-4 4 5 33R DDR2-D5 DDR2-A6 J7 DQ D1 1 8 33R DDR2-D12
7 5 6 A 4
DDR2-A8 K8 B1 33R 3 6 3B08-3 DDR2-D6 DDR2-A7 K2 D93B10-4 4 5 3B11-1 33R DDR2-D13
8 6 7 5
DDR2-A9 K3 B9 3B07-1 1 8 33R DDR2-D7 DDR2-A8 K8 B1 33R 4 5 3B11-4 DDR2-D9
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B10-1 1 8 33R DDR2-D15
10 9 7
DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B16 DDR2-DQS0_P DDR2-A11 K7
12 11
DDR2-A13 L8 DQS A8 3B17 33R DDR2-DQS0_N DDR2-A12 L2 B7 3B18 DDR2-DQS1_P
13 12
2B46 DDR2-A13 L8 DQS A8 3B19 33R DDR2-DQS1_N
+1V8 33R 13
DDR2-BA0 G2 RES 2p2 2B47
0 33R
DDR2-BA1 G3 A2 DDR2-BA0 G2 RES 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
RES 3B06 F9 DDR2-ODT
ODT
180R 1%

DDR2-CLK_P 240R E8 3B09 RES F9

ODT
3B20

DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8

DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
FB00 RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
DDR2-VREF-DDR CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM0 3B25 B3 DDR2-WE F3
DM|RDQS WE
180R 1%

DDR2-DQM1 3B26 B3
33R VSS VSSQ DM|RDQS
3B21

VSSDL
33R VSS VSSQ
B8
D2
D8
A3
E3
J1
K9

E7

A7
B2

VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
1X20 1X21 1X22 1X23 1X24
HOOK1 HOOK1 HOOK1 HOOK1 HOOK1

4 2012-04-23

DDR 3 2011-12-12

3139 123 6533 2 2011-05-25

19220_038_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 138

10-4-9 PNX 85500: Power

PNX 85500: Power

B05A IS3Q 5S80

30R
+1V1 B05A

10u
2S5A
2S6A

100n
1
5S81
+2V5

2
30R

10u
2S6B

2S5B
100n
1
+1V8
IS3S 5S82

2S26

2S61
2S60

2S62

2S63

2S66

2S67

2S68
2S64

2S65
100u

100n
100n

100n

100n

100n

100n

100n
100n

100n
+3V3
30R

10u
2S5C

2S5D
100n
SENSE+1V1 c001
5S93
7S00-10

G6

G7
R6
R7
U7

C6
D6
A5
A6
B5
B6

E6
F6

F7
L6
L7
PNX85500 +2V5
30R

2S6R 2

220u 6.3V
VDD_1V8

2S4M
2S6D

100n
100n
+1V1 AF1 V20

7
AE2 HDMI_VDDA_1V1 V21

5
AD3

1
2S5G-1

2S5G-2

2S5G-3

2S5G-4

2S5H-1

2S5H-2

2S5H-3

2S5H-4
2S4Q

2S4R
2S28
2S43

2S27

2S23
100n

100n
100n

100n

100n

100n

100n

100n

100n

100n

100n

100u
AC4 VDD U20

22u

22u

1
AB5 HDMI_VDDA_2V5 U21
H20

4
F11 U22 +2V5-LVDS

2
HDMI_VDDA_3V3_TERM
G11
F13 N6

2S4N

2S4P
100n
G13 VDD_2V5 N7

10u
F15

8
8

5
G15 C7

2S5K-1

2S5K-2

2S5K-3

2S5K-4

2S5J-3

2S5J-1

2S5J-2

2S5J-4
100n

100n

100n

100n

100n

100n

100n

100n
F17 C9

220u 2V0
2S29
G17 C11
5S85
F19 VDD_2V5_LVDS C14

4
+3V3

2
2

1 2S6G 2
G19 C16

1
30R

2S6N

2S6C

2S6P
2S6F

100n

100n

100n
100n
J9 C18

10u
J11
AA16
AA8
Y11
Y14

J13 W20
Y16
Y9

7S00-12

1
1
PNX85500 J15 P20
J17 M20
VSSA
A1 M7 L9 VDD_3V3 K20
+3V3-STANDBY
A10 N2 L11 V7

2S4U
2S4V

100n
A12 N20 L13 Y8

10u
A15 P10 L15
VDD_1V1
A17 P12 L17 Y19
A19 P14 N9 VDD_3V3_SBY Y18
A26 VSS P16 N11 IS3K 5S83
A3 P18 N13 B13
VDDA_1V1_LVDS_PLL +1V1
A8 P4 N15
IS3L 30R

2S4W
2S4Y

100n
B1 P6 N17 AA15

1u0
B20 P7 R9 Y15
VDDA_1V2
C20 T10 R11 AA13
C4 T12 R13
5S95 +2V5
D2 VSS T14 R15 Y12
VSS VDDA_2V5 5S84
D20 T16 R17
30R

6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R

2S4Z
2S51

2S52

2S50
100n
100n
E20 T2 U11

10u
E4 T6 U13 AA7 c000 SENSE+1V2

10u
VDDA_2V5_ADAC
F10 T7 U15
F12 U4 U17 Y17
VDDA_2V5_DCS
F14 V10 J6
F16 V12 AA6 D13
VDDA_2V5_LVDS_BG
F18 V14 Y7
F20 V16 W7 T20

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG
VDDA_2V5_USB
F8 V18 F9
G10 V2 G9 Y13
VDDA_2V5_VADC +2V5-AUDIO
G12 Y20

HDMI_AGND
5S94

2S46

100n
J7 Y10

VSSA_USB
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC
30R
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

R21
VDDA_3V3_USB
2S4S

2S5P

2S21
100n
10u

1u0

U24
V24

A13

C13

R20
1

+2V5-AUDIO

2S45

100n
5S87
+2V5
30R

2S55

2S56
100n

1u0
5S88
+2V5-LVDS
30R

2S5M

2S57
100n

10u
5S89
+2V5

2
30R

2S6H

2S6K
100n

100n
2S58

10u
1

1
5S90
+2V5
30R

2S4T

2S53
100n

10u
2SHW

100n
IS58 5S92
+3V3

2
30R

2S6M

2S6L

2S59
100n

100n

1u0
1

1
4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Power

19220_039_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 139

10-4-10 PNX 85500: Standby controller

PNX 85500: Standby controller

B05B B05B

+1V1
IS3B

5S04
RES

30R

2S13

2S10

100n
1u0
2S37

1u0

2S11 IS20

100n

POL
DS50 2S4G
3
1 10p

AC17
AA17

AF26
2

1S02

54M
7S00-9
PNX85500 4
2S4F
1

VDDA_1V1_DCS

VDDA_ADC2V5

VDD_XTAL
+3V3-STANDBY 2S4D AE17 +3V3-STANDBY
3S1B XTAL_IN 10p
1n0 RC RC AD19
3S1C 0
RES 10K TACHO TACHO AE19 AF17
1 XTAL_OUT
10K 3S1D CEC-HDMI CEC-HDMI AF19
2 P1
3S1A RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20 AA26 RESET-STBYn
3 RESET_IN
10K 3S1F SDM SDM AB20 IS3F
7 3S44
+3V3-STANDBY 10K STANDBY EA
AB24 EA EA
3S3L RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3G 10K 3S43
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
1 ALE
10K 3S3N RES BL-ON BL-ON AE20
2 IS3D 10K
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN 10K 3S42
3 PSEN
10K 3S3Q RES CTRL-DISP1 CTRL-DISP1 AA21 P2
4 RES 3S6V
RES 3S3S 10K CTRL-DISP2 CTRL-DISP2 AB21 AC23 3S2F 100R SDA-UP-MIPS SDA-UP-MIPS
5 SDA
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
6 SCL
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21 4K7 RES
7 LED1 RES 3S1P
+3V3-STANDBY 10K AD26 3S2H 100R LED1
3S1G 0
RXD-UP RXD-UP AE21 PWM AC25 3S2K 100R LED2 LED2 10K 3S41
0 1
3S1H 10K TXD-UP TXD-UP AF21
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO
3S2A 2 SDO
DETECT2 AB22 P3 AF25 PNX-SPI-SDI
3 SDI
AC22 SPI AF24 PNX-SPI-CLK
10K 4 CLK
RES AD22 AF23 PNX-SPI-CSBn
5 CSB
3S1K FS0Y
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 3S4A 100R CTRL-DISP3 CTRL-DISP3 RES 3S2L 10K
0 0
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS RES 3S46 10K
10K 1 1
RES AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J 2 2 +3V3-STANDBY
KEYBOARD KEYBOARD AE24 AE18 RESET-ETHERNETn RESET-ETHERNETn RES 3S47 10K
3 3
LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC RES 3S2S 10K
100K 2S4C 4
RES AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP RES 3S2M 10K
4 5

VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 3S49 10K
7

AD17
3S1L
SPI-PROG SPI-PROG
10K PNX-SPI-WPn

+3V3-STANDBY

3S2V

10K
3
2S4K

100n

7S20
NCP803
VCC
FS0Z
2 RESET-STBYn
RESET

RES 2S4L
GND

1n0
1

4 2012-04-23

PNX 85500 3 2011-12-12

3139 123 6533 2 2011-05-25

Standby controller

19220_040_120228.eps
120509

2012-Jun-29 back to
div. table
 Circuit Diagrams and PWB Layouts Q552.4E LA 10. EN 140

10-4-11 PNX 85500: MIPS

PNX 85500: MIPS

B05C B05C
+3V3
* 3D ACTIVE 7S00-3
PNX85500
CONTROL C25 1
3S56
2
3S69
IS05 SDA-UP-MIPS SDA-UP-MIPS
3S45 SDA 2 3S57
BOOTMODE 1 C26 100R 1 SCL-UP-MIPS SCL-UP-MIPS 3S6A 4K7 4K7
+3V3 SCL
100R
10K 3S58
BOOTMODE Y21 B26 1 2 SDA-SET SDA-SET 3S6B 2K2
GPIO_0
+3V3 * 3S40 FS54 3D-LR 3D-LR
RXD1-MIPS
IS17
* 9S09 IS16 Y22
Y23
GPIO_1
2
SDA
SCL
A25 100R 1
100R
2 3S5W SCL-SET SCL-SET 3S6C 2K2
10K GPIO_2 3S5Y
TXD1-MIPS Y24 B25 1 2 SDA-SSB-550 SDA-SSB-550 3S6D 2K2
3S82 GPIO_3 SDA
BL-I-CTRL-PNX RXD2-MIPS W21 3 A24 100R 1 2 3S5Z SCL-SSB-550 SCL-SSB-550 3S6L 2K2
+3V3 GPIO_4 SCL
TXD2-MIPS W22 100R
10K GPIO_5 3S60
3S80 FS10 TXD2-MIPS GPIO6 W23 B24 1 2 SDA-TUNER SDA-TUNER 3S6F 2K2
+3V3 GPIO_6 SDA
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 2K2
+3V3 GPIO_7 SCL
10K BL-I-CTRL-PNX V23 100R
RES 3S21 IS04 GPIO_10
GPIO6 SELECT-SAW U23 AA25 EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K
+3V3 GPIO_11
TRSTN
10K AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K
TMS +3V3-STANDBY
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
RES 3S62 PNX-SPI-CS-BLn DN TCK
USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
+3V3 DP USB TDO
IS4Z R24 AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4
10K RREF TDI
10K
3S00 RES
AE4 RESET-SYSTEMn
RESET_SYS 1F10

3S55

5K6
RES 3S64 33R FS44
SELECT-SAW AD5 BL-DIM EJTAG-TRSTn-PNX85500
+3V3 BL_PWM 1
FS64 EJTAG-TMS-PNX85500 FS49
10K 2
AC5 SDA-SSB-550 cS51 SDA-FE EJTAG-TDO-PNX85500 FS50
CLK_54_OUT 3 FOR FACTORY

3S26