The Ohio State University

Electrical and Computer Engineering Dept

RFICs, ECE-5022

TITLE: Final Project 16-QAM Modulator and Receiver

NAME: Stephen Watt

DATE DUE: December 11, 2014

DATE RECEIVED:
Section A: 16-QAM Modulator and Receiver
[Question 1.1] A random bit stream is used to model the data of interest. The bits are split into two channels,
using every other bit, to form parallel bit streams. Each channel is then converted to a two bit waveform,
represented by an amplitude modulated signal with four levels. A quadrature modulator is implemented by
using two mixers and two LO signals (at the carrier frequency) with a 90 phase difference. The two data
waveforms are then up-converted and combined in quadrature. The quadrature amplitude modulated (QAM)
signal is then passed to the transmission channel. A QAM demodulator will use the reverse process to recover
the data.

Figure 1 16-QAM Modulator diagram

[Question 1.2] As shown in Figure 2, the necessary ratio of the bit energy to the noise spectral density (Eb/No)
to achieve a bit error rate of 10-5 is determined to be 13.7 dB. Using the expression

13.7
= = 10 log (10 10 (4)),

where R is the symbol bit rate and B is the bandwidth (or 1/T for digital systems) the corresponding SNR
necessary to maintain the desired bit error rate is calculated to be 19.7 dB.

Figure 2 16-QAM Eb/No vs. BER (www.dsplog.com)

[Question 1.3] The bit period, TB, is equal to the inverse of the bit stream frequency of 1 Mbps, so the bit
period is equal to 1 s (shown in Figure 3).

Figure 3 Random data stream input for modulator

[Question 1.4] Since each symbol requires four bits, the symbol period is TS = 4*TB = 4 s. In Figure 4 we see
the symbol rate of 4 s as expected. As shown in Figure 5, the main lobe bandwidth noticeably decreases from
0.25 MHz to 0.17 MHz from the input to the output of the filter. The unfiltered bandwidth is one sided in the
baseband and is 1/4 of the data rate as expected. This is expected since the bandwidth efficiency of 16QAM is
four. The side lobes are also significantly suppressed by the RRC filter.

Higher roll-off factor of the RRC filter will reduce the side lobe levels. The bandwidth of the spectrum after the
filter can be calculated by using BW = RS(1+R), where RS is the symbol rate (1 Mbps), R is the root raised
cosine filter roll-off factor ( = 0.35):

= (1 + ) = 0.25 106 (1 + 0.35) = 0.3375

It is apparent from the equation above that increasing the RRC filter roll-off increases the channel bandwidth in
the time domain, however as shown in Figure 5, the bandwidth in the frequency domain is decreased.

Figure 4 Even and odd bit waveforms for 16-QAM, 1Mbps data rate

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 Figure 5 RRC filter input (blue) and output (red) spectra

[Question 1.5] The roll-off of the RRC pulse shaping filter was chosen as 0.35 to provide a reasonable tradeoff
between side-lobe reduction and bandwidth for the filtered pulses. Figure 5 shows the reduction in the side-lobe
levels of the data signal.

Since the LO frequency is 850 MHz, the mixers output should appear very close to 850 MHz. Consequently
the BPF center frequency is set to 850 MHz and the bandwidth is set to cover the bandwidth of the data signal
after the RRC filtering. In order to maintain a Q-factor between 20 and 30, the bandwidth of the BPF was
chosen to be 40 MHz. The 40 MHz bandwidth was centered around 850 MHz.

The loss of the BPF is chosen to provide an output signal strength of 0dBm. Two filter reactances are used to
control the filter roll-off. More reactances in the filter mean a sharper roll-off in the stop band.

[Question 1.6] The spectrum of the transmitted signal (output of the PGA) is shown in Figure 6. The loss of the
BPF and gain of the transmitter PGA was adjusted such that the transmitted signal power is approximately 0
dBm.

Figure 6 Tx signal at the PGA output (before AWGN and loss)

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[Question 1.7] The constructed receiver demodulates the signal using commercial off-the-shelf (COTS)
components. The SKY67101-396LF LNA was chosen for its low noise figure of 0.57 dB and operating
frequency from 0.4 1.2 GHz. This LNA operating frequency must be in the range of the image reject BPF
used in the receiver. An ideal image reject BPF with 2 dB of loss and a 2 MHz bandwidth was used after the
LNA component to remove the image, which has an offset of twice the intermediate frequency (IF) from the
desired channel signal. The ADL5801 RF mixer was used to down-convert the signal to baseband. The local
oscillator (LO) was modelled using and ideal tone source. Finally, a HMC960LP4E power amplifier was used
to amplify the IF signal for detection. See attached Appendix for component datasheets. From the received
signal spectrum it is apparent that the commercial components functioned well, yielding an SNR of 47 dB
which meets the EVM and BER requirement.

Figure 7 Received signal at PGA output showing SNR of 47 dB

[Question 1.8] Figure 8 shows the 16-QAM receiver constellation with 16 distinct constellation points. Since
the constellation points are well defined, we can infer the BER is low and the SNR is high. The transmitted
signal constellation maintains the 16 constellation points, however the magnitude is significantly reduced, as
expected from the channel loss of 90 dB. Nonetheless, the constellation points are still relatively well defined,
indicating the chosen receiver components are functioning well. The received signal SNR of 47 dB meets the
SNR requirement calculated in Question 1.2, and consequently the BER requirement of less than 10-5 is met. It
is noted that increasing the isolation on the mixer improves the receive signal BER. Specifically, better isolation
of the LO from the output has most impact on BER.

Figure 8 Modulated signal constellation before transmit channel (left) and after PGA (right)
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[Question 1.9] See the attached pages for the full system schematic for the Part A simulations.

Section B: Designing with Imperfections

[Question 2.1] To examine the effect of IQ amplitude and phase mismatch of the transmitted signal, an IQ
imbalance sub circuit was implemented in the modulator. As shown in Figure 9, the 0.5 dB IQ amplitude
mismatch slightly compressed the constellation diagram. Even with the slight compression, the SNR, and
consequently the EVM and BER is still acceptable, as pictured in the received signal spectrum of Fig. 9. To
exaggerate the effect of IQ amplitude mismatch, a 5 dB mismatch was introduced to the transmission circuit and
the constellation diagram is plotted in Figure 10. It is apparent that the amplitude mismatch compresses the Q-
axis of the constellation proportional to the level of mismatch.

Figure 9 Constellation diagram w/ 0.5 dB amplitude mismatch (left) and resulting SNR

Figure 10 5 dB IQ amplitude mismatch shown to illustrate effect of amplitude mismatch

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[Question 2.2] Next a 1 IQ phase mismatch was introduced to the transmission system to examine the resulting
BER and EVM. As shown in Figure 11, the effect of the 1 IQ imbalance is minimal and the BER, EVM, and
SNR specifications are still met.

To exaggerate the effect of IQ phase mismatch, a 20 mismatch was introduced to the transmission circuit and
the constellation diagram is plotted in Figure 12. It is apparent that the phase mismatch introduces a rotational
distortion to the constellation that is proportional to the level of mismatch.

Figure 11 Constellation diagram w/ 1 phase mismatch (left) and resulting SNR

Figure 12 20 IQ phase mismatch shown to illustrate effect of phase mismatch

[Question 3.1] After introducing phase noise to the LO in the receiver, the received signal constellation is
significantly distorted as shown in Figure 16. Consequently, the BER of the received data significantly
increased. The addition of phase noise in the LO signal causes symbol rotation and results in shifting of
adjacent constellation points. This results in the observed increase in the BER that does not meet the 10-5
specification.

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 Figure 13 Configuring phase noise in the receiver LO source (left) resulting signal constellation

[Question 4.1] The system is shown to tolerate up to a 1.4 dB IQ amplitude mismatch while still meeting the
BER/SNR specification, as shown in Figure 14.

BER
ID=BER5
VARNAME="AMPLITUDE"
VALUES=stepped(0,6,0.5)
OUTFL=""

BER

Figure 14 Varying the IQ amplitude mismatch and measuring BER (< 1.4 dB meets spec)

[Question 4.2] The system is shown to tolerate up to a 2.75 IQ phase mismatch while still meeting the
BER/SNR specification, as shown in Figure 15.

[Question 4.3] Next the IQ amplitude and phase mismatch were set to zero and an 850 MHz jamming signal
was introduced at the receiver input. The receiver system is shown to tolerate up to a -59.42 dBm jamming
signal while still meeting the BER/SNR specification, as shown in Figure 16.

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 BER
ID=BER5
VARNAME="PHASE"
VALUES=stepped(0,20,2)
OUTFL=""

BER

Figure 15 Varying the IQ phase mismatch and measuring BER (< 2.75 meets spec)

BER
ID=BER5
VARNAME="JAM_POWER"
VALUES=stepped(-80,-30,5)
OUTFL=""

BER

Figure 16 Varying the 850 MHz jamming signal power and measuring BER (< -59.42 dBm meets spec)

[Question 5.1] See attached.

[Question 5.2] See attached.

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ECE-5022 Final Project
16 QAM Modulator and Receiver System Design
The Ohio State University, AU 2014
By: Stephen Watt
Date Submitted: December 11, 2014
 - IQ Imbalance
- AGWN
- Path Loss
- Jamming Signal

From 16-QAM IQ
Modulator
 From Rx PGA

From IQ Modulator
DATA SHEET
SKY67101-396LF: 0.4 to 1.2 GHz High Linearity, Active Bias
Low-Noise Amplifier
Applications
GSM, CDMA, WCDMA, and TD-SCDMA cellular infrastructure
Ultra low-noise systems
Features
Ultra-low-noise figure: 0.57 dB @ 0.9 GHz
Input and output return loss > 18 dB @ 0.9 GHz
High OIP3 performance: +33.8 dBm @ 0.9 GHz
Adjustable supply current and gain
Temperature and process-stable active bias
Miniature DFN (8-pin, 2 x 2 mm) package (MSL1 @ 260 C per
JEDEC J-STD-020)
Skyworks Green products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Denition of Green, document number
SQ04-0074.
N/C 1 8
RFIN 2 7
RFGND 3 6
VIN 4 5
Figure 2. SKY67101-396LF Pinout 8-Pin DFN
(Top View)
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
201266I Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 10, 2014
RF_IN RF_OUT/VDD
FEEDBACK
Active
RFGND Bias
VIN S1942
Figure 1. SKY67101-396LF Block Diagram
Description
The SKY67101-396LF is GaAs, pHEMT low-noise amplifier (LNA)
with an active bias and high linearity performance. The advanced
GaAs pHEMT enhancement mode process provides excellent
return loss, low noise, and high linearity performance.
The internal active bias circuitry provides stable performance over
temperature and process variation. The device offers the ability to
externally adjust supply current and gain. Supply voltage is
applied to the RFOUT/VDD pin through an RF choke inductor.
Pin 4 (VIN) should be connected to RFOUT/VDD through an
N/C external resistor to control the supply current. The RFIN and
RFOUT/VDD pins should be DC blocked to ensure proper
RFOUT/VDD operation. Pin 5 (FEEDBACK) is connected through an RC network
to externally adjust the gain of the device without affecting the
noise figure (NF) of the LNA.
N/C
The SKY67101-396LF operates in the frequency range of 0.4 to
1.2 GHz with proper tuning. For higher frequency operation, the
FEEDBACK pin-compatible SKY67100-396LF or SKY67102-396LF should be
used.
S1943 The LNA is manufactured in a compact, 2 x 2 mm, 8-pin Dual Flat
No-Lead (DFN) package. A functional block diagram is shown in
Figure 1. The pin configuration and package are shown in Figure
2. Signal pin assignments and functional pin descriptions are
provided in Table 1.
1
 High IP3,
10 MHz to 6 GHz, Active Mixer
Data Sheet ADL5801
FEATURES FUNCTIONAL BLOCK DIAGRAM
VPLO GND NC IFON IFOP GND
Broadband upconverter/downconverter 24 23 22 21 20 19
Power conversion gain of 1.8 dB
Broadband RF, LO, and IF ports
GND 1 18 VPRF
SSB noise figure (NF) of 9.75 dB ADL5801
Input IP3: 28.5 dBm GND 2 17 GND

Input P1dB: 13.3 dBm LOIP 3 16 RFIP

Typical LO drive: 0 dBm V2I
LOIN 4 RFIN
Single-supply operation: 5 V at 130 mA 15

Adjustable bias for low power operation GND 5 14 GND

Exposed paddle, 4 mm 4 mm, 24-lead LFCSP package
GND 6 13 VPDT
BIAS DET
APPLICATIONS
Cellular base station receivers

08079-001
7 8 9 10 11 12
VPLO GND ENBL VSET DETO GND
Radio link downconverters
Broadband block conversion Figure 1.
Instrumentation

GENERAL DESCRIPTION
The ADL5801 uses a high linearity, doubly balanced, active
mixer core with integrated LO buffer amplifier to provide high
dynamic range frequency conversion from 10 MHz to 6 GHz.
The mixer benefits from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. An optional input power detector is provided for
adaptive bias control. The high input linearity allows the device
to be used in demanding cellular applications where in-band
blocking signals may otherwise result in degradation in dynamic
performance. The adaptive bias feature allows the part to provide
high input IP3 performance when presented with large blocking
signals. When blockers are removed, the ADL5801 can auto-
matically bias down to provide low noise figure and low power
consumption.
The balanced active mixer arrangement provides superb LO-to-
RF and LO-to-IF leakage, typically better than 40 dBm. The IF
outputs are designed to provide a typical voltage conversion
gain of 7.8 dB when loaded into a 200 load. The broad
frequency range of the open-collector IF outputs allows the
ADL5801 to be applied as an upconverter for various transmit
applications.
The ADL5801 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm 4 mm,
24-lead LFCSP package and operates over a 40C to +85C
temperature range. An evaluation board is also available.

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 20102014 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
 v01.1212
HMC960LP4E
DC - 100 MHz DUAL Digital
Variable Gain AmplifieR with Driver

Typical Applications Features

The HMC960LP4E is suitable for: Low Noise: 6 dB NF
Baseband I/Q Transceivers High Linearity: Output IP3 +30 dBm
Direct Conversion & Low IF Transceivers Variable Gain: 0 to 40 dB
Diversity Receivers High Bandwidth: DC to 100 MHz
ADC Drivers Precise Gain Accuracy: 0.5 dB Gain Step
Adaptive Gain Control Excellent Magnitude and Phase Response
Externally Controlled Common Mode Output Level
Parallel or Serial Gain Control
Read/Write Serial Port Interface (SPI)
24 Lead 4x4 mm SMT Package 16 mm2
Programmable Input Impedance
(400 Differential or 100 Differential)
IF/BASEBAND PROCESSING - SMT

Functional Diagram General Description

The HMC960LP4E is a digitally programmable dual
channel variable gain amplifier. It supports discrete
gain steps from 0 to 40 dB in precise 0.5 dB steps.
It features a glitch free architecture to provide
exceptionally smooth gain transitions. The device
has matched gain paths which provide excellent
quadrature balance over a wide signal bandwidth.
The HMC960LP4E provides an SPI programmable
input impedance of 100 differential or 400
differential (default).
Externally controlled common mode output feature
enables the HMC960LP4E to provide a flexible output
interface to other parts in the signal path.
Gain can be controlled via either a parallel interface
(GC[6:0]) or via the read/write serial port (SPI).
Housed in a compact 4x4mm (LP4) SMT QFN
package, the HMC960LP4E requires minimal external
components and provides a low cost alternative to
more complicated switched amplifier architectures.

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
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Application Support: apps@hittite.com