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3rd ISSE National Conference on Complex Engineering Systems of National

Importance:Current Trends & Future Perspective (INAC-03), October 12-13, 2017 Advanced Materials

AM-0007 Fabrication of Nanotransistors

Gangadhar Purohit1,2#+, Monica Katiyar1,2, Deepak 1,2
Department of Materials Science and Engineering, Indian Institute of Technology Kanpur, India,
National Centre for Flexible Electronics, Indian Institute of Technology Kanpur, India
Corresponding author: ganga@iitk.ac.in +Presenter

AbstractIn this paper, using a cost-effective and was realized in bottom contact top gate
simple technique for the formation of nano- architecture, with IGZO as sputtered active channel
separation of metal electrodes over a large layer, and PVPh dielectric and PEDOT:PSS as
substrate/wafer using conventional optical inkjet printed layers (Figure 1).
lithography and thermal stresses,a thin film transistor
with indium-gallium-zinc oxide (IGZO)
semiconductor is fabricated. Gate electrode is made PEDOT:PSS
by inkjet printing of polyvinylphenol dielectric and PVPh dielectric
PEDOT:PSS. The threshold voltage is 6.4 V and
estimated linear mobility is 0.1 cm2/Vs. Combination IGZO channel material
of the techniques for forming of nano-separation of S/D electrodes
metal electrodes and printing is a viable low cost Glass
hybrid process for making TFT arrays.

I. INTRODUCTION Fig.1.Schematic side-view of TFT device architecture

fabricated on nanogap containing Au electrodes.
High throughput and low cost processing is of
paramount importance for nanomanufacturing II. EXPERIMENTAL DETAILS
when miniaturization of electronics devices is (a) Patterned substrate: Thick transparent glass,
required [1]. But, the scaling down the device basically used in electronics industry for device
components results in increase of complexity of fabrications, was taken as substrate material. First
nanolithography equipment as well as their process they were cleaned by soap solution, then rinsed
steps. Hence, the development of low cost and with de-ionized (DI) water, followed by RCA
unconventional routes for nanolithography is protocol for removing organic and metal
essential. Although the present-day contaminations. After cleaning, the multilayer thin
nanolithography instruments are used for producing films of Ti (10 nm)/ Au (50 nm)/SiOx (300 nm)
large area nanostructure geometries, still they have were deposited using e-beam evaporator, without
daunting tasks such as long fabrication time and breaking vacuum in between these deposition steps.
expensive process cost. Hence unconventional Here the SiOx layer was deposited at 200oC. In
way/approach of top-down nanofabrication (or addition, an ultrathin layer of Ti was made to
bottom-up approach by chemical self-assembly) promote adhesion of Au film on glass surface.
will be a replacement of many expensive, Next, the sequential patterning of multilayer thin
conventional lithography techniques used in films from SiOx, Au and then Ti were made using
miniaturization of semiconductor technology. We conventional optical lithography, as show in Figure
have demonstrated here a technique for 2a. The so-formed substrate was taken for heat
nanofabrication by applying thermal stress on treatment ranging from 300-500oC.
multilayered thin films patterned over a large
substrate/wafer [2]. The strength of this invention (a (b
is that scalable fabrication of large number of ) )
nanogaps in electrodes in a single thermal
annealing step. This thermal stress based nanogap
fabrication involves very minimum number steps to
get final geometry, which is unlikely in existing
nanolithography techniques, such as e-beam
lithography [3], focused ion beam (FIB)
lithography [4] and scanning probe lithography [5]. Fig. 2. (a) The optical imaging of a notched electrode
bridge consisting of stacking layer of SiO x/Au/Ti on
glass by using optical lithography, (b) Crack assisted
Here Au/Ti thin films were taken as a test structure
nano-separation notched electrode bridge after thermal
because of its use as electrode contacts in may annealing at 350oC for 1 hr.
electronics devices. Furthermore, we have
visualized the nanochannel thin film transistors The crack was formed on SiOx layer due to thermal
(TFTs) by using the thermal stress defined stress mismatch between SiOx and metal (Au) thin
nanogaps in electrodes as the source and drain films, and also because of brittle nature of SiOx thin
electrodes of the devices. The IGZO based TFT film. In order to localize the crack, a notch was

3rd ISSE National Conference on Complex Engineering Systems of National
Importance:Current Trends & Future Perspective (INAC-03), October 12-13, 2017 Advanced Materials

included at the mid length of electrode bridge. As we know, apart from the inherent resistance on
When a crack opening generated on SiOx layer, the active semiconductor layer, the other resistances
Au and Ti films just underneath to SiOx layer were created due to overlap of S/D electrodes with
etched out using their respective chemical etchants. semiconductor layer, between junction/interface of
Finally, the entire SiOx layer was stripped out from semiconductor molecule with Au atoms, and also
the substrate, leaving the nano-separation Au due to thin film nature of gate oxide causes current
nanogap electrodes. Using this technique, leakage to gate electrode.
nanogaps in electrodes with around ~ 200-300 nm (d) Ink Formulations:Conducting gate electrode
length scale were generated (Figure 2b). by using PEDOT:PSS was purchased from Heraeus
industrial semiconductor processing, this thermal (CleviosTM P Jet HC) and mixed with additives of
stress technique can be a viable process for dimethyl sulfoxide (DMSO), Titron X and de-
commercial nanomanufacturing. The I-V electrical ionized (DI) water to make inks for printing. Here
characterization of the nanogap separated electrode the ink solution was prepared using solvent of
bridges was taken to check whether the electrodes PEDOT:PSS and DI-water as a ratio of (1:1) , then
were electrically isolated or not. After that, these mixing with 5 wt% of DMSO and 1 wt% of
nanogaps in electrodes were used as source and Triton as a binding agent.After drying printed layer
drain electrodes in thin film transistors, its of PVPh dielectric, the PEDOT:PSS electrode
fabrication process is described in the following contact was deposited by using inkjet printing.
sections (Figure 1). Then the films were dried for 30minutes at 120 oC.
Here the film thickness was observed around 25-35
(b) Fabrication of other device components: The nm, which confirmed using stylus profilometer.
RF sputtering evaporator was employed for Here the ink-jet printed PEDOT:PSS acts as the top
depositing IGZO semiconductor of 20 nm gate electrode of TFTs.
thickness, also confirmed by stylus profilometer.
The transparent nature of IGZO thin film was an III. RESULTS AND DISCUSSION
advantage while printing of gate dielectric and gate The concept behind the proposed method/technique
electrode above it. It was also useful during for forming nano-separation in electrodes involves
electrical probing. the differential thermal expansion co-efficient
The drop-on-demand inkjet printer [Fujifilm between the ceramic film (SiOx) and Au metal film
Dimatix Materials Printer DMP-2831] was used for beneath it. Tensile stress are induced in SiOx film
depositing polymer dielectrics (PVPh) and gate during heating from a specific temperature. As the
electrodes (PEDOT:PSS) at desired location. thermal expansion co-efficient of SiOx film
Precise dropping of inks was possible using inkjet (deposited by e-beam evaporator) is lower than Au
printing technology. Inkjet printer does not require thin film, then upon heating crack propagation only
masks for production of different layers. takes place on SiOx layer. Here a notch shaped
Furthermore, it is a non-contact technique with electrode bridge was patterned and it led to stress
advantage of reduced contamination and risk of concentration at the notch tip during heating of the
substrate damage.Other than printing techniques, substrate, so the crack at first was initiated at the
no easy process was found to make multilayers of notch tip of electrode bridge of SiOx layer. The
films with exact alignments. Advanced lithography crack propagated across the electrode bridge only
techniques will require multiple steps to get same in SiOx film. Then a metal etching step was made
final configuration, for example mask alignment, to remove Au and Ti film at the location of crack,,
multi-steppatterning. Hence, inkjet printer helps to while the ceramic oxide acts as protecting layer (or
make drop-on-demand fabrication of layers within hard mask) to other area of metal films. At the end,
short time. stripping out of SiOx layer causes nanogap at the
notched electrode bridge having the dimension in
(c) Ink Formulations:Polymer dielectric nanometer range. The nanogaps in electrodes were
PVPh inks were formulated by mixing additives of measured of dimensions ranging between 150-300
propylene glycol methyl ether acetate (PGMEA) nm by taking number of substrates. The crack
and cross-linking agent (CLA ). The ink for drop- defined nanogaps in electrodes is independent of
on-demand printing is formulated as 96.25 wt % substrate used. Here the glass substrate was
PGMEA + 2.5 wt% PVPh + 1.25 wt% CLA. After replaced by, silicon substrate with thermally grown
inkjet printing, the dielectric ink droplets were SiO2 (Figure 3).
dried for 1 hour at 180oC. The thickness of PVPh (a) (b)
dielectric was measured using stylus profilometer,
which was around 10-15 nm of thickness.
The droplets of PVPh were precisely jetted on the
desired location of the S/D electrodes, as shown in
the Figure 4.In order to reduce resistances created
due to overlap of various layers, drop-on-demand
printing was followed to deposit polymer dielectric Fig. 3. (a) FE-SEM image of nanogap separated Au
and gate contact electrode with best possible way. electrodes on SiO2/Si-substrate, (b) Its enlarged nanogap
~300nm was achieved in one of electrode bridges.

3rd ISSE National Conference on Complex Engineering Systems of National
Importance:Current Trends & Future Perspective (INAC-03), October 12-13, 2017 Advanced Materials

Due to thermal annealing, the cracks were only made at

VD = 10 V
the notched electrode bridge of patterned multilayer thin -8
films. The advantage of the process is that no observation
of any crack formation on as-purchased SiO2/Si -9

Drain current (A)

To localize the crack defined nanogap at the 6.0x10
electrode bridge, we have used rf-sputtering and
ink-jet printer for depositing other TFT 4.0x10
components. All ink-jet printing layers of TFTs can
be made on the thermal stress defined nanogap -9
electrodes, but we have made only two top layers,
such as polymer dielectric and gate contact by ink- 0.0
jet printing process. In Figure 4, a droplet of PVPh -10 -5 0 5 10
was ink-jet printed over IGZO film deposited on Gate voltage (V)
nanogap separated Au/Ti source and drain contacts.
Fig. 5.(a) Output characteristics of an IGZO based TFT
having channel length of 700 nm. (b) Transfer
characteristics of the TFT at 10 V. Channel width is 4
m, capacitance of PVPh is 20 x 10-9 F/cm2.

In our lab, we obtained nanogap features with
thermal annealing, without steppers, on entire
substrate simultaneously. The so-obtained nanogap
in electrodes is around ~ 200 nm, which is difficult
to achieve only using traditional photolithography.
Hence, it is a cost-efficient and simplistic technique
for formation of nano-separation in between metal
electrodes. Its eminent use is in semiconductor
Fig.4. Droplet of PVPh on nanogap containing Au device manufacturing. Control of notch, with
electrode. sharper features (industrial processing conditions)
can further reduce the gap dimension much below
IV. DEVICE CHARACTERIZATION optical lithography limits.
The current vs voltage measurement of the device IGZO based TFT was also realized in bottom
was measured using Kiethley 2640 source-meter contact top gate device architecture on nanogap of
unit. Figure 5(a) and (b) show output and transfer Au electrodes, with IGZO as the sputtered active
characteristics of the device. The threshold voltage channel layer, and PVPh dielectric and PEDOT:
is 6.4 V and estimated linear mobility is 0.1 PSS as printer layers. Further optimization of
cm2/V.s. processes is required to improve performance.
-8 VG=0.0 V
VG=5.0 V [1] J. A. Liddle and G. M. Gallatin,
6.0x10 VG=7.5 V "Nanomanufacturing: A Perspective," ACS Nano,
Drain current (A)

VG=10 V vol. 10, pp. 2995-3014, 2016/03/22 2016.

-8 [2] G. Purohit, Deepak, M. Katiyar, "Thermal stress
induced nanometer scale separation between
electrodes: method for their preparation and use,"
2.0x10 Provisional patent application number-
[3] J. B. Lee, P. C. Chang, J. A. Liddle, and V.
Subramanian, "10-nm channel length pentacene
transistors," IEEE Transactions on Electron Devices,
-2.0x10 vol. 52, pp. 1874-1879, 2005.
[4] T. Nagase, T. Kubota, and S. Mashiko, "Fabrication
0 2 4 6 8 10 of nano-gap electrodes for measuring electrical
Drain voltage (V) properties of organic molecules using a focused ion
beam," Thin Solid Films, vol. 438, pp. 374-377,
2003/08/22/ 2003.
[5] C. F. Quate, "Scanning probes as a lithography tool
for nanostructures," Surface Science, vol. 386, pp.
259-264, 1997/10/01/ 1997.