NATIONAL INSTITUTE OF TECHNOLOGY

TIRUCHCHIRAPPALLI

INDIA

SANJAY GHANASHAM TALEKAR

Male, Indian, 25 years

Permanent Address : S/O Mr. GHANASHAM M. TALEKAR

Tisk-Dharbandora,
Piliem-Bhumikanagar,
Goa – 403406

Temporary Address: C/O Mr. B. VENKATARAMANI

ECE Department,
NIT Tiruchchirappalli,
Tamil Nadu - 620015

Email: sanjay_talekar2005@yahoo.co.in, sanjaytalekar.ece@gmail.com.

Mobile No: +919894564980

PERSONAL DETAILS
Father’s Name: GHANASHAM MANJANATH TALEKAR
Date of Birth: 7th December 1984
Linguistic Proficiency: English, Hindi, Marathi and Konkani

EDUCATION

Course College/School Year of passing CGPA/Marks

M. S.(by Research) NIT Tiruchchirappalli 2009 9.0
(VLSI Systems)
B.E.(ECE) Goa Engineering college, 2006 66%
Goa
Class XII G. V. M’s Higher 2002 82.2%
(Goa State Board) secondary school, Ponda
Class XII Gomantak Vidyalaya 2000 82%
(Goa State Board) school, Tisk

WORK EXPERIENCE
A) College : NIT Tiruchirappalli (Research associate)
• Experience : October 2009 to till date
 • Working domain : Verilog based design/ FPGA

B) Company: Bristlecone India limited, Bangalore (Software engineer)

• Years of experience: July 2006 – July 2007
• Working domain: Java

PROJECT WORK / TRAINING

A)Main Projects
M.S. (by research): 1)500MSPS 6-b SAR ADC for UWB Application
Guide: Dr. B. Venkataramani and Dr. G. Lakshminarayanan, Dept of ECE.
500MS/s 6-bit SAR ADC is designed using time interleaved approach. A novel DAC
architecture has been proposed for the DAC to be used in SAR ADC designed. The main
blocks were sample and hold, DAC, comparator and SAR logic. A low offset comparator
has been proposed to get the required 6- bit accuracy.

2) Low power 700MSPS 4-bit 2bit/step time interleaved SAR ADC

Guide: Dr. B. Venkataramani and Dr. G. Lakshminarayanan, Dept of ECE.
700MS/s 4-bit time interleaved SAR ADC has been designed by detecting 2 bits per
clock cycle. Architecture proposed in work uses only two differential DAC’s instead of
three DACs reported in literature. Hence it reduces the power of time-interleaved SAR
ADC by 33%. The main blocks were DAC, comparator and SAR logic.

B.E.(ECE): Designing of voice prompts for D’links DPH70’s IP phone(software

implementation)
Guide: Miss Ameeta Chimulkar, ECE Dept.
Recorded the voice prompts in .wav format. These voice prompts in .wav format were
compressed using the G.729a encoder (it compresses by 16 times) to .dat format and then
stored in memory. While playing the particular voice prompt, the corresponding voice
prompt is taken, decompressed and played.

B) Mini Project:4-bit processor with 4-bit registered ALU and 16x4 RAM model
4-bit processor design consists of 4-bit adder, an arithmetic and logic unit (ALU), 16x4
RAM and instruction decoder. ALU can perform 8 operation including. 16x4 RAM was
modeled using the block RAM feature of XILINX. An instruction decoder was modeled
as a finite state machine (FSM) taking 3-bit op-code and two 4-bit operands. Bus function
model (BFM) was used to test each module independently of the other modules’
performance. Also the overall processor ALU is verified using vector waveforms.

PROJECTS WORKED DURING WORKING PERIOD

1) Digital implementation of UWB transmitter and receiver
UWB digital packet transmission consists of preamble, PLCP header and payload. The
important block of the transmitter side is 128 point fft block.
2)AMAT (Applied Materials)
This project is meant for developing a site for the sale of the products online. All the
features were included in the site so that the site is most user-friendly. Site was developed
fully JAVA/J2EE platform. Design of site required use of servlets, JSPs, java scripts, etc.

ADEMIC ACHIEVEMENTS
• GATE score of 492( 97.25 percentile) in GATE-2006
• Topper in the class till 10th standard
• Got 98% marks in mathematics in XIIth board exam

PAPERS ACCEPTED FOR PUBLICATION IN CONFERENCES

• Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan and B. Venkataramani
“500MS/s 4-b time interleaved SAR ADC using novel DAC architecture” IEEE
VLSI symposium ASQED 2009, Malaysia
• Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan and B. Venkataramani
“Low power 700MSPS 4-bit 2bit/step time interleaved SAR ADC in 0.18µm
CMOS”,EDAS IEEE-RSM 2009 conference, Malaysia
• Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan and B. Venkataramani
“A Low power 700MSPS 4-bit time interleaved SAR ADC in 0.18µm
CMOS”,TENCON 2009 conference, Malaysia

AREAS OF INTEREST
• FPGA Based Design
• Analog circuit design
• JAVA/J2EE

COMPUTER SKILL SETS

• Languages: C, C++, JAVA, Verilog, VHDL, SPICE Modeling,
Assembly Language Programming in 8085/86.
• Operating System: Windows XP, Red Hat Enterprise LINUX 4.0, SUN Solaris.

ECAD SKILL SET

• FPGA Programming Tools: Quartus II, Xilinx ISE 8.1i
• ASIC Design Tools: Cadence front end and backend design flow for analog
design Cadence encounter flow, Synopsys Front End Flow Tools, Mentor Front
End & Back End Tools