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ATPG Flow Documentation

Issue 1 November, 2013

2013 PMC-Sierra, Inc. All rights reserved.


PMC-Sierra
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Burnaby, BC Canada V5A 4V7
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This document is confidential and proprietary and is for the use of PMC-Sierra Inc. personnel only, except
to the extent that permission is expressly granted elsewhere. In any event, no part of this document may
be reproduced in any form without the express written consent of PMC-Sierra, Inc.

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Table of Contents
1 Purpose...................................................................................................4
2 PMC DFT Flow........................................................................................5
3 TSB Level Flow.......................................................................................7
3.1 Pre-requisite Training....................................................................7
3.1.1 Introduction to DFT Rule Checks and Fault models..........7
3.1.2 Memory Fault Models and Introduction to Memory-BIST. .7
3.2 TSB Level ATPG Flow.....................................................................7
3.2.1 TSB Level SCAN Architecture............................................9
3.2.2 Multi-pass Flow for Automatic Test Pattern Generation. 10
3.2.3 ATPG Coverage Analysis for DC and AC Faults................11
3.2.4 Optimum Vector to Gate Ratio (VGR)...............................11
3.2.5 Verification of ATPG Patterns through Simulation..........11
3.2.6 Simulation Failure Debugging Techniques.......................12
3.2.7 PMC RAMBIST Architecture and Algorithms....................12
3.2.8 RAMBIST WGL Generation and Simulation......................12
3.2.9 Macro Mapping for Timing Simulation..............................13
3.2.10 TSB Level DCP Checklist..................................................13
3.2.11 Miscellaneous Documents................................................13
4 Top Level Flow......................................................................................15
4.1 Pre-requisite Training..................................................................16
4.1.1 Basics of TAP Controller and General Boundary Scan....16
4.1.2 Top level DFT Architecture in PMC...................................16
4.2 BSDL Generation Flow for Boundary Scan Verification.............16
4.3 Top-mapping of TSB Level WGLs.................................................17
4.3.1 DCSU configuration to Generate AC Capture Pulse........18
4.4 ICTEST Flow to Test Glue Logic..................................................18
4.4.1 ICTEST Deliverables.........................................................20
4.5 Top-RAMBIST WGL Generation Flow...........................................20
4.6 Top Level DCP Checklist..............................................................21
4.7 Simulation Based Vector Verification Flow................................21

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5 DFT Pattern Simulation Signoff at Tape-Out.......................................22
6 PE Handoff and Deliverables...............................................................23
7 Documentation.....................................................................................24
7.1 DCP Checklists............................................................................24
7.1.1 Dry Run..............................................................................24
7.1.2 Tape In...............................................................................24
7.1.3 Tape Out............................................................................24
7.2 TVDN Update...............................................................................24
7.3 ATPG Status Sheet......................................................................24
7.4 ATPG Archival..............................................................................24
7.4.1 TSB level archival.............................................................24
7.4.2 ICTEST archival.................................................................25
7.4.3 Top RAMBIST archival.......................................................25
8 Revision History...................................................................................26

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1 Purpose
This ATPG flow document will serve as first reference source to understand PMC DFT work flow and
provide the pointer to training & application notes for detailed understanding. The document is
primarily organized into two sections:
Macro level (TSB level)
Top level DFT activity (Chip level)
These two sections are explained in detail further based on below points, to understand the concept,
execution and deliverables.
Pre-requisite Trainings
Flow
DCP Checklists
Handoff

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2 PMC DFT Flow

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3 TSB Level Flow
Large SOC design is partitioned into DFT regions which may be several hundred Kgates up to a few
million gates, for ease of execution and management. The key goals in partitioning a device into DFT
regions are:
Size of each partition
Macro replication strategy for the partition
Quantity of I/Os and proximity to neighboring partitions and their sizes.

Then the DFT region is exercised for all DFT activities, such as DFT structures insertion, pattern
generation and verification.
This section identifies the necessary documents/trainings related to TSB level, for successful
execution of DFT activity and pattern delivery to Product Engineering.

3.1 Pre-requisite Training


Prior to study DFT flows in PMC, an engineer must have basic knowledge of DFT architectures, and
methodologies to access these DFT structures.

3.1.1 Introduction to DFT Rule Checks and Fault models


Design for testability is a structured approach to make the internal logic controllable and observable
by replacing the every state element (D flip-flop) into a scan cell. This greatly simplifies the testing
of an IC by accessing combinational logic between scan cells. There are specific DFT rule checks to
be verified and fixed for successful scan replacement and ATPG. Below CAD components discuss
these rule checks and basics of DFT.
TSB Design for Testability Rules (cad_dd_00542)
Introduction to DFT (cad_dd_00275)

3.1.2 Memory Fault Models and Introduction to Memory-BIST


Memories may have varied faulty behavior due to their dense structure. To detect faulty cells in the
memory a specific Sequence of read and write operations need to be applied. An additional Built-In-
Self-Test logic has to be inserted into chip to apply required sequence of read/write of operation.
Refer to following documents to understand the memory fault models, algorithm to detect these
faults and BIST logic.
RAM_fault_models.pptx
RAM BIST lecture (cad_dd_00273)

3.2 TSB Level ATPG Flow


With the knowledge of basic architectures/elements of DFT obtained through the documents
mentioned above, its time to look into PMC specific DFT design methodology for a TSB or macro.
Below flow chart indicate the overview of DFT activities for a TSB and expected deliverables.

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As shown in the flow chart, the DFT inserted netlist released by IG team after synthesizing the
functional and DFT logic with scan structures inserted. Upon receiving this netlist ATPG team
performs three primary activities:
ATPG pattern generation and simulation
ATPG debug and analysis for AC & DC coverage improvements
MBIST pattern generation and simulation

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3.2.1 TSB Level SCAN Architecture
As a first step in the ATPG process TSB owner must have the knowledge of DFT-005 architecture by
referring to cad component cad_dd_00796. Thorough understanding of this DFT architecture help
the TSB owner to debug any issues pertaining to scan chain failure, low AC/DC coverage and
simulation failures.
The flow chart above indicate the TSB level ATPG process followed in PMC from pattern generation to
simulation and recording the results through DCP checklist.
Prior to begin ATPG process, obtaining following information from the netlist release (IPR by IG
team) would help the TSB owner to anticipate forthcoming issues.
Device Test Clock Matrix spreadsheet for test clock mapping and clock frequencies
o To define proper clock correlation in accordance with top level source
Clock diagram from Implementation Document
Number of scan reset ports and their top level reset port
o To define proper reset correlation in accordance with top level source
Gate count of the design
o Required to calculate the Vector to Gate Ratio (VGR)
Number of Input and Output ports of a TSB
o How many of these input and output ports registered by IO wrapper cells
Scan Compression ratio for a TSB
o Maximum compress scan chain length and uncompressed scan chain length
o Average chain length across all the scan chains
Total memories in a TSB
o Are et_libs available for all memories?
o Shadow logic (memory bypass) added to each of these memories?
SDC constraints
o To understand false paths and multi cycle paths in the TSB and their impacts on AC
coverage
Understanding of specific exceptions defined for this macro beyond the SDC file like if clock
rates are reduced or merged for higher AC coverage
Is the TSB 100% stitched?
Does the TSB contain special PADs? Are the ATPG models available?

Update all these information into ATPG prep to give state of the TSB that help cross-functional team
to expect the possible outcome of ATPG results.

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3.2.2 Multi-pass Flow for Automatic Test Pattern Generation
The reason why we have a multi-pass flow is because DFTv5 control circuitry blocks ATPG generation
from exercising all faults directly. This is achieved by enabling portion of logic for test through
various test modes by programming DFT registers, hence the name Multi-pass flow. These test
modes generate patterns for both stuck-at faults (DC) and Transition faults (AC). The standardized
Multi-pass flow has been developed to avoid manual errors, while generating patterns. Refer and
populate the below CAD component to execute multi-pass ATPG flow
Multiple Pass ATPG for DFT regions (cad_dd_00954)
At the completion of ATPG run, the log file must be reviewed thoroughly, to check for warnings,
errors and results. Make sure no module is read with black-box during build_model. Check for TSV
warnings related to:
X sources in the design (TSV-102)
o May lead to Low ATPG coverage for stuck-at and Transition fault models. Need to fix as
many as possible for ATPG results.
Hard and soft contentions (TSV-093 and TSV-193)
o If ignored, may lead to short between VDD and GND. Ok to ignore if these violations are
on the analog logic cone. Any contentions on digital logic cone must be root caused and
fixed
Combinational feedback loops (TSV-001)
o This may cause long ATPG runs and may lead to infinite loops during pattern simulation.
Break all the combinational feedback loops in test mode.
Clock-Data race violations (TSV-054)
o Will lead to mismatches during pattern simulation. Hence these flops must be masked
for pattern generation.
Scan chain tracing violations (TSV-385 and TSV-384)
o Not accepted to have these in the ATPG runs as they lead poor test coverage. Any
broken scan chains must be debugged and fixed
o With the help of debug_broken_scan_chain.pdf debug the broken scan chains
If the test structure verification results are satisfactory, check for coverage and pattern count results
to meet PE requirement on device quality and test cost. Each DFT macro or partition will have a
Discussion PREP created with following title:
PM80XX_A: ATPG Coverage Analysis for <mnemonic>
For each revision of the partition, ATPG Coverage Analysis prep has to be updated with coverage
numbers, pattern count and detailed fault analysis. Details of low coverage analysis have to be
updated if the TSB is not meeting the AC and DC coverage goals.

Note : Please use the appropriate PM number & revision for each prep.

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3.2.3 ATPG Coverage Analysis for DC and AC Faults
PMC requires each partition to achieve greater than 99% DC stuck-at and minimum 80% AC
(transition) coverage for each TSB and fixed during the Dry-Run phase of the partition. Any TSB
falling short of these targeted goals has to be root caused and fixed during the Dry-run phase of the
TSB. ATPG engineer must have thorough knowledge of design structure and good usage of EDA tool
to understand, debug low coverage issues. Refer to below document for debugging low coverage
issues.
Structured Coverage Analysis for PMC designs
Due to large combinatorial logic or complex structure of the logic ATPG tool may not generate
patterns and mark the faults as Aborted Faults. These Aborted faults are tedious to debug.
Experiment the Deterministic Fault analysis (DFA) method, if the DC coverage largely affected due to
aborted faults. But, DFA experimenting requires interaction with PD or IG and is not a standard flow.
Refer to below document and consult the DFT lead to improve the coverage on aborted faults.
Test point insertion using Deterministic Fault Analysis (DFA)

3.2.4 Optimum Vector to Gate Ratio (VGR)


Due to large and complex logic cloud, ATPG tool may have to generate more patterns to detect all
faults in that cloud. VGR is a metric to evaluate testability of design in terms of pattern count.
During the dry run phase, patterns are generated without any limit. With the historical knowledge of
design size and pattern count, the VGR (Vector to Gate Ratio) is expected to following range
depending on size of the design.
Large Design size (More than 3Mgates): VGR = 0.5
Medium Design size (750Kgates-3Mgates): VGR = 1
Small Design size (less than 750Kgates): VGR = 2
If the pattern count is large and VGR (Vector to Gate Ratio) is exceeding the limits mentioned above,
review the DFT implementation details such as,
Compression ratio: Past ATPG result shows that, the optimum pattern count is obtained by
keeping compression scan chain lengths in the range of 100-150. Consult the Implementation
team for change in compression ratio and fix the appropriate number during dry run phase.
Scan chain balancing: Improper balancing of chain length across scan chains will lead to
higher vector count. Ensure to keep the length of longest chain close to average scan chain
length.
If the above parameters are found to be optimum and yet the VGR is exceeding the limits, try test
point insertion using Random Resistant Fault Analysis (RRFA). But, RRFA TPI requires interaction
with PD or IG, is not a standard flow, causes significant schedule delays and must be approved by
the PD Project Manager. Refer to following application note to execute RRFA test point insertion flow
Test point insertion using Random Resistant Fault Analysis (RRFA)

3.2.5 Verification of ATPG Patterns through Simulation


To ensure the integrity of design flow, both type of ATPG patterns (DC and AC) must be simulated
during dry run phase with appropriate simulation models. All patterns of all modes are expected to
be simulated (no-timing) by tape-in phase.

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Post tape-in, all patterns must be simulated with Slow corner timing clean SPEF. When ECOs happen
during tape-out phase, the ATPG patterns need to be regenerated. So all patterns may not be able to
complete timing sims prior to tape-out. Coordination with PD and PE must be done to provide status
regarding which patterns and how many have completed timing sims prior to tape-out. Finally all
patterns of all modes must be timing simulated before delivery to PE. Refer to below document for
simulation steps.
WGL Verification Application Note (cad_dd_00529)
Note: Based on the DFT-TMT (25th June, 2014) discussion, SDF annotated simulations are to be
done using Parallel Verilog Testbenches (generated from Encounter Test).

3.2.6 Simulation Failure Debugging Techniques


Due to various reasons the ATPG patterns may fail during simulation, in both timing and no-timing
simulations. It is important to debug and resolve these simulation failures immediately when they
appear; for a successful timely execution and delivery of DFT patterns. Refer to following document
for any assistance in debugging simulation failures.
Debugging_atpg_sim_failure.doc
Simulation debugging using ET GUI

3.2.7 PMC RAMBIST Architecture and Algorithms


Memory defects are identified using Built-In-Self-Test (BIST) methodology. The memories are highly
dense register array, and hence prone to various kinds of faults, unlike logic gate faults, which are
largely due to stuck-at and transition faults. So, memory faults are modeled differently and need
more iteration through the memory to detect those faults. Refer below documents and home page
to understand the PMC RAMBIST architecture and methodology.
RAMBIST lecture (cad_dd_00292)
RAMBIST home page (cad_dd_00378)

3.2.8 RAMBIST WGL Generation and Simulation


Prior to Memory BIST pattern generation and simulation, obtain the following information from
Implementation team.
Number of BIST wrappers
BIST Clocks and Resets
Maximum depth of the logical memory
Does TSB contain DPRs?
TSB contains ROMs? If yes from where to obtain ROM content file (hex file)
Constraints in the TSB to propagate BIST clock or reset

Knowledge of these Memory BIST information help to execute the RAMBIST in right manner and
prevent the false simulation failures. Apart from these details, also note if the TSB contain non-PMC
standard RAMBIST architecture, such as MIPS and ARM.
ARM RAMBIST Architecture

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MIPS RAMBIST Architecture

Refer and populate below CAD component to understand the procedure to execute RAMBIST flow in
PMC.
PMC SV RAMBIST application note (cad_dd_00938)

This CAD component consists of reference manual to describe the PMC RAMBIST structure and flow
to generate RAMBIST wgl. Fill up the jtag_bist_vector_setup.gt.tcl to generate jtag_info.txt and
RAMBIST WGL. During the dry run phase, perform no-timing simulation of all RAMBIST structures in
a TSB. Make sure side-B of DPRs are also exercised without fail. Upon availability of timing clean
SPEF (in RAMBIST mode), the timing simulation must be completed by tape-in phase.

3.2.9 Macro Mapping for Timing Simulation


To avoid routing congestion and better area utilization, the design may be partitioned as layout
region. This layout region not necessarily DFT region due to large gate count. So, a layout region
can have two or more DFT regions within. In such scenario, placement and routing is done at layout
level, so the SPEF and SDF is generated for layout level. Hence the ATPG patterns generated at DFT
region must be timing simulated at layout region level. This is accomplished by mapping all DFT
region test ports to layout region test ports and generating macro mapped WGL. Refer to following
document to understand the macro mapping flow
Macro Mapping Flow
Note: Cases where connectivity dependencies are identified between DFT partitions should be
reported in PREP during the dry-run phase so they can be corrected. These dependencies may
significantly complicate the macro mapping process. These dependencies may include: DFT register
programming of more DFT partitions than the one being tested, concatenated DFT UDR partitions,
partitions which require another partition to connect scan control signals. All these cases required
top-level design modifications during the dry-run phase.

3.2.10 TSB Level DCP Checklist


After completing the ATPG and RAMBIST activity, archive all the input files, output files and log files
into SVN vault and create archive tags for reference in the future. The archival of the results must be
completed for final Tape-in release. As per the PMC design process, the below mentioned DCP
checklist has to be filled for TSB after the archival of final tape-in release. The ATPG Quality
checklist, in which final tape-in and tape-out results must be recorded in the DCP.
ATPG Quality Checklist (Pre-tapein)
ATPG Quality Checklist (Pre-tapeout)

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3.2.11 Miscellaneous Documents
The TSB is a functional block designed within a chip that is large enough to be DFT layout/DFT
region for ease of design verification. Usually TSB core is a RTL design of specific functional entity,
which can be re-used while designing other chip. To make this TSB Test friendly, hierarchies are
created around TSB core. The immediate hierarchy is a TSB core wrapper which contains IO wrapper
cells, which are inserted to control and observe the PI/PO of the functional core. Another DFT
wrapper is added above the core wrapper, to insert DFT setup register, compression logic and
routing logic for scan ports. The CAD components which describe these elements of the TSB are:
DFT Wrapper Insertion Lecture (cad_dd_00276)
IO Wrapper Cell Application Note (cad_dd_00960)

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4 Top Level Flow
As said earlier, large SOC design is partitioned into small regions for ease of execution in DFT,
Placement & Routing, and verification. But, DFT vectors generated and verified are further applied
from the Top level to ensure the integrity of the scan structure from TSB to Top. Following picture
shows the flow diagram of all top level DFT activities.

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As shown in the flow chart, all Top level DFT hookup happens in the RTL level, such as:
IOLM insertion for each IO Pad
Scan daisy chain stitching of all TSBs
Interconnect Test (ICTEST) scan chain stitching

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PAD control register insertion
JTAG macro insertion and hooking up all Instruction Decode signals
Top level DFT UDR insertion and its hook up
Then IG team synthesizes the top level RTL and release the netlist for further activities. Upon
receiving this netlist ATPG team needed to perform following activities:
BSDL generation and simulation to verify UDRs and Boundary scan
Top level RAMBIST WGL generation and simulation (REDECC_ENABLE & REDECC_DISABLE)
Top-mapping of TSB level ATPG patterns and simulation
Interconnect Test (ICTEST) pattern generation and simulation

4.1 Pre-requisite Training


The top-level DFT engineer should have an understanding of PMCs top-level DFT structures,
boundary scan and Memory BIST. This section identifies and lists the documents to be undergone
prior to top level DFT execution.

4.1.1 Basics of TAP Controller and General Boundary Scan


The TAP controller was designed to detect manufacturing faults in circuit boards. Later, TAP
controller was extended to setup design (chip) into required mode, functional and DFT mode, due to
its ease of access. Detailed descriptions are provided in documents:
JTAG Tutorial (cad_dd_00400)
RTL Test Access Port (TAP) controller

4.1.2 Top level DFT Architecture in PMC


Following documents describes the guidelines and architecture of Top level DFT used in PMC. This
explains the details of top level DFT UDR and top level Scan DFT methodology.
Top level DFT Flow 04
Though this document is not updated for DFT-005 architecture, it is a good reference point for Top-
level DFT architecture. There is a CAD PREP# 74357, to update this document as per new DFT
methodology.

4.2 BSDL Generation Flow for Boundary Scan Verification


Boundary scan is a methodology allowing complete controllability and observability of the boundary
pins of a JTAG compliant (IEEE 1149.1/1149.6) device. This capability enables in-circuit testing
without the need of bed-of-nail in-circuit test equipment.
Following document explains how to generate Boundary Scan Description Language (BSDL) files for
PMC devices. More specifically, this flow generates two types of BSDL files for each device:
1. The internal BSDL file which is used only internally at PMC in order to generate JTAG test
vectors; this file contains the engineering pin names i.e. die pin names. An internal BSDL file
should never be released to any customers.

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2. The external BSDL file which is the post-processed version of its associating internal BSDL
file. The external BSDL file is used externally for use of our customers; this file contains the
marketing pin names i.e. package pin names. The external BSDL file reclassifies certain
internal registers as private to preclude customers from modifying them.
In general, a BSDL file describes the key aspects of the JTAG boundary-scan logic implemented
within a particular design; the features described by BSDL include the length and the structure of the
boundary-scan register, the instruction binary codes and the physical location of the Test Access Port
(TAP). The BSDL files generated by this flow are compliant with IEEE Std. 1149.1-2001 and IEEE
Std. 1149.6-2003 if it has been implemented in the given device.
40n Padring Generation Application Note
IOLM BSDL File Generation flow
Refer following documents to generate JTAG Production vectors with Internal BSDL as an input,
generated from above steps. This document provides the steps to generate BSDL WGL file and steps
to re-simulate it.
JTAG Vector Generation for BSDL
JTAG Production Test Vectors
Use below documents as a reference guide to debug any BSDL simulation failures or Tester debug.
JTAG Vector Debug

Other top DFT activities begins only after confirming that BSDL verification is passing for at least UDR
chain integrity test.

4.3 Top-mapping of TSB Level WGLs


As per the PMC methodology SOC is partitioned into small regions (TSB) to aid DFT execution. Each
DFT region is independently executed for ATPG and patterns are simulated at TSB level. But, these
TSB level patterns must be applied from the device level through daisy chain architecture discussed
in previous sections of this document. So, to generate the Top-mapped TSB level WGLs, PMC has
developed a top-mapping methodology through a Top-mapping xlsx.
Following documents describes the flow and guidelines to create Top-mapping excel sheet. It also
explains the steps to simulate mapped patterns using Top-map excel sheet.
ATPG WGL Mapping flow Wiki page
Top-mapping Flow using Excel Sheet

These Top-mapped WGLs (all modes of all instances) are expected to be simulated (no-timing) prior
to tape-out date. ATPG team is advised to align with PE and PD on number of patterns to be
simulated, in case of any deviation from this milestone, which can happen due to functional ECOs
close to tape-out date.

The Top-mapping flow currently generates 83k resim testbench, whereas actual production test
program is 93k. So, to ensure no translation errors from 83k to 93k, ATPG team expected to
simulate at least 5 patterns from 93k production test program resim testbench obtained from PE.
This activity is expected to be completed prior to silicon bring-up.

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4.3.1 DCSU configuration to Generate AC Capture Pulse
Device level CLK pads support only certain frequency range (Max of 400Mhz for 40n devices and 200
Mhz for 28n devices) to drive. At times, AC scan frequencies are beyond the frequency range
supported by PADs, hence internally generated (PLL) at-speed frequency is chopped to obtain two AC
pulses required for Launch-on-Capture (LOC) based transition fault testing.
In this case we can use the in-built DCSU (present in all the devices) logic to generate the at-speed
double pulses. Please refer to following DCSU engineering documents for detailed functional
understanding of DCSU:
DCSU_28N Engineering documents
Following document describes how DCSU can be configured using Top-map XLS to lock the DCSU for
required frequency and steps to obtain the at-speed double pulse (by chopping) which is used during
the capture phase of AC scan Testing.
DCSU Based AC Scan Testing
DCSU based at-speed simulation (timing) must be completed prior to tape-out for any TSB which
requires PLL source to generate double pulse for transition fault testing.

4.4 ICTEST Flow to Test Glue Logic


As per the PMC methodology SOC is partitioned into small regions (TSB) to aid DFT execution. Each
DFT region is independently executed for ATPG and make sure PMC mandated DC/AC coverage is
met. Though the maximum logic is made part of some TSB, yet some glue logic sit outside the
TSBs, which is called glue logic. The standard DFT architecture is defined by PMC to test this glue
logic in the device level ATPG called ICTEST (Inter-connect Test). Prior to ICTEST pattern
generation, each DFT region fault status is read into Encounter Test through Prepare Detected Faults
(PDF) list file. So the ATPG tool is waived to target these faults (tested at TSB level) during ICTEST.
Hence, DFT region faults are targeted by TSB level ATPG and glue logic is tested by ICTEST level
ATPG. Finally the device level coverage is calculated by Encounter Test with the aggregation of each
PDFs (of each DFT region instance) and ICTEST level ATPG.
As shown in the following picture IB (Input Boundary) and OB (Output Boundary) chains, highlighted
in Red, are stitched independently from Core chains at TSB level.

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Then at the Top level these IB/OB chains are stitched together to form ICTEST chains and connected
to top level scan ports, as shown in below picture.

During ICTEST only these IB/OB chains of each TSB are made active (for shift and capture), through
scan_en_i & scan_en_o signals as discussed in TSB DFT-005 architecture. Core chains of each
TSB are disconnected and turned off (no shift), through scan_en_c UDR bit.
Following document describes the flow to execute Inter-connect Test (ICTEST) by reading all the TSB
level PDFs.
ICTEST Flow using PDFs (Prepare Detected Faults)

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At the end of ICTEST pattern generation, each TSB instance must be reported for DC coverage and is
expected to meet the PMC corporate goal of greater than 99% stuck-at coverage. Thorough
coverage analysis should be completed and recorded in the PREP. If any design is short of 99% DC
coverage and cant be achieved prior to tape-in, recommended design modifications for a TSB
revision should be PREPd against the RTL vault and marked as enhancement. PE must review
coverage and the reasons why a design is below required limits so a waiver can be approved.

4.4.1 ICTEST Deliverables


All ICTEST patterns are expected to be simulated (timing) prior to tape-out date. To complete the
timing sims before tape-out, the patterns can be split into separate simulations to complete more
patterns in parallel. ATPG team is advised to align with PE and PD on number of patterns to be
simulated, in case of any deviation from this milestone, which can happen due to functional or Timing
ECOs close to tape-out date. Post tape-out, ATPG team should obtain ICTEST resim testbench from
the production test program and simulate at least 5 patterns (5 scan loads) to ensure no errors while
building test program.
As per the PMC methodology two types of ICTEST patterns must be generated, simulated and
delivered to PE.
ICTEST Patterns without PI/PO toggle (boundary=internal in the MODEDEF file)
ICTEST Patterns with PI/PO toggle (boundary=no in the MODEDEF file)
But for FCA (Day-1 silicon bring-up) only ICTEST patterns without PI/PO toggle are applied on ATE.

4.5 Top-RAMBIST WGL Generation Flow


Each TSB is verified for RAMBIST at TSB level, yet verifying the RAMBIST from the device level is
necessary to ensure integrity of the RAMBIST clocks/resets and UDRs from the device level. The
following document describe the flow to create device level RAMBIST jtag_info.txt which in turn used
to generate the top level RAMBIST WGL, so that all the memories in the device are tested in parallel.
The jtag_info.txt and WGL for PMC standard RAMBIST and vendor RAMBIST is independently
generated due to architectural limitations.
Top RAMBIST Flow
In case of PMC RAMBIST structure, following two bist_jtag_info.txt files and respective WGL must be
delivered.
redecc_enable_bist_jtag_info.txt
redecc_disable_bist_jtag_info.txt
In case of redecc_enable the BIST failure is asserted only if two or more bits failed, as the single bit
failure is corrected through ECC logic. Refer to cad_dd_00938 CAD component for detailed
architectural understanding of redecc_enable and redecc_disable RAMBIST structures.
RAMBIST WGL files are generated using these bist_jtag_info.txt files and should be simulated without
annotation prior to tape-out. Deliver bist_jtag_info.txt and WGL file to PE after successful completion
of no-timing simulation.
The RAMBIST WGL files delivered by ATPG team will be converted to production Test program by PE
team. Post-tapeout & pre-silicon, ATPG is expected to obtain the RAMBIST resim testbench from the
production test program and simulate (no-timing) to ensure no errors while building test program.

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4.6 Top Level DCP Checklist
After completing the ATPG (Top-mapping and ICTEST), BSDL and RAMBIST activity, archive all the
input files, output files and log files into SVN vault and create archive tags for reference in the future.
The archival of the results must be completed for final Tape-out releases. As per the PMC design
process, the below mentioned DCP checklists have to be filled for Top level device after the archival
of final tape-out release.
DFT Pre Tape-out Verification Checklist
Test Pattern Handoff Checklist
IG Archive Checklist

4.7 Simulation Based Vector Verification Flow


Simulation based Vector Verification is a method of verifying the final (RTP) tester program
correctness for multiple instance TSBs and RAM instances in RAMBIST vectors. This verification has
to be done so as to make sure that none of the instance of a TSB or no RAM instance is escaped
from the Tester Program during its build up.
This is simulation based methodology which is done by ATPG team on the resim testbench provided
by PE (Product Engineering) team from the final tester program which is going for RTP.
If the device ready for RTP, then Vector Verification is exercised for Scan Vectors of multiple instance
TSBs and RAMBIST Vectors for RAM instances. Below document describe the Vector Verification
flow.
Simulation based Vector Verification Methodology
Please refer to following document for detailed information about Vector Verification Methodology
applied on ATE by Product Engineering team:
Vector Verification Methodology on ATE

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5 DFT Pattern Simulation Signoff at Tape-Out
Below table summarizes the simulation signoff criterion for all DFT patterns.

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6 PE Handoff and Deliverables
Below table summarizes the patterns to be delivered to PE.

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7 Documentation
Following section will provide the summary of all the documentation & records created by ATPG
team.

7.1 DCP Checklists


Below section indicate the DCP checklists to be filled at different milestones of design execution.

7.1.1 Dry Run


ATPG Quality Checklist (Pre-tapein)

7.1.2 Tape In
ATPG Quality Checklist (Pre-tapeout)
DFT Pre Tape-out Verification Checklist

7.1.3 Tape Out


IG Archive Checklist
Test Pattern Handoff Checklist

7.2 TVDN Update


The DFT/ATPG related sections of the TVDN would be updated by DFT team

7.3 ATPG Status Sheet


DFT team owns & updates the ATPG status sheet for each project on weekly basis. The template for
the standard ATPG status sheet can be accessed from following PDOX link.
PMxxxx_A_ATPG_Status.xlsx

7.4 ATPG Archival


Upon successful completion of the ATPG and final annotated simulation, all the files must be archived
for future reference.

7.4.1 TSB level archival


Following files must be archived for each TSB by the respective owner.
Input source files used for ATPG and RAMBIST generation
o Modedef & seqdef file, netlist, sdc, multi-pass flow source tcl file
Output files from ATPG and simulation
o ATPG log file, tbdata & testresults directories, WGL files, cycle map files, scan chain
report; DC & AC fault files and Prepare Detected fault file from final testmode.

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o Annotated Simulation log files for each wgl, rambist simulation logfile, hdl.var and
cdslib files and SDF file.

7.4.2 ICTEST archival


Following files must be archived for the final ICTEST database
Input source files used for ATPG
o Modedef & seqdef file, top level netlist, TSB level netlist, SDC, PDF files used for each
TSB, ATPG dofile and faultrule file.
Output files from ATPG and simulation
o ATPG log file, tbdata & testresults directory, WGL files, cycle map files, scan chain
report; DC fault files
o Annotated simulation log files for each wgl, hdl.var and cdslib files and SDF file.

7.4.3 Top RAMBIST archival


Following files must be archived for the final top level RAMBIST database.
Input source files used for RAMBIST generation
o RAMBIST jtag_info.txt files for both redecc_enable and redecc_disable rambist.
Output files
o RAMBIST wgl for both redecc_enable and redecc_disable, SDF file and annotated
simulation log files.

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8 Revision History

Iss Issue Author Reviewer Approver Details of Change


No. Date

1 30th Sep Hanumanthar Steven NG, Steven NG, Document created.


2013 aya Jon Jon
Haldorson, Haldorson,
Ken Ken
Ferguson Ferguson
2 17th Oct Hanumanthar Steven NG, Steven NG, Refined TSB level ATPG flow as per
aya Jon Jon DCP process
2013
Haldorson, Haldorson,
Ken Ken
Ferguson Ferguson
3 13th Nov Hanumanthar Steven NG, Steven NG, Added TOP level ATPG flow as per
aya Jon Jon DCP process
2013
Haldorson, Haldorson,
Ken Ken
Ferguson Ferguson
4 3rd Dec Hanumanthar Steven NG, Steven NG, Updated as per Ken Wagners review
aya Jon Jon comments
2013
Haldorson, Haldorson,
Ken Ken
Ferguson Ferguson
5 19th Feb Hanumanthar Steven NG, Steven NG, Summary sections added for tape-
aya Jon Jon out signoff and PE handoff
2014
Haldorson, Haldorson,
Ken Ken
Ferguson Ferguson

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