FABRICATION OF

MICROELECTRONIC
DEVICES
PRESENTED BY:
ALISHA RAJBANSHI (ROLL: 1)
BHUWAN KARKI (ROLL: 6)
MANOJ ADHIKARI (ROLL: 11)
SMARIKA BHAILA (ROLL:16)
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 INTRODUCTION
Modern days inventions such as: calculators, wrist
watches, controls for home appliances and
automobiles, information systems, robotics,
telecommunications, space travel, weaponry, and
personal computers requires printed circuit board,
micro-controller or integrated Circuits (ICs).

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 INTRODUCTION CONT.

The major advantages of todays ICs are their very small size and low cost.
As their fabrication technology has become more advanced, the size and cost of
such devices as transistors, diodes, resistors, and capacitors continue to decrease,
and the global market has become highly competitive.
More and more components can now be put onto a chip, a very small piece of
semiconducting material on which the circuit is fabricated.
Typical chips produced today have sizes that are as small as 0.5 mm 0.5 mm and,
in rare cases, can be more than 50mm50 mm, if not an entire wafer.

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 INTRODUCTION CONT.

MICROELECTRONICS:
Subfield of electronics.
Relates to the study andmanufacture of very small electronic designs and
components. These devices are typically made from semiconductor materials.
Include transistors, capacitors, inductors, resistors, diodes and(naturally) insu
lators and conductors can all be found in microelectronic devices.
In Digital IC: transisters
In Analog IC; resistors and capacitors

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TERMINOLOGY USED IN MICROELECTRONICS
Substrate : substance onto which a layer of another substance is applied, and to which that second substance adheres. And
also known as wafer
thin slice of material such as silicon, silicon dioxide, aluminum oxide, germanium, gallium arsenide(GaAs
arsenide(GaAs),), an alloy of
silicon and germanium. These serve as the foundation upon which electronic devices such as transistors, diodes, and
especially integrated circuits(ICs) are deposited.
Wire bonding : method of making interconnections between an integrated circuit(IC) or other semiconductor device and
its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC to
other electronics or to connect from one printed circuit board(PCB) to another.
Doping: intentional introduction of impurities into an intrinsic semiconductor for the purpose of modulating its electrical
properties
Ion implantation: process by which ions of a material are accelerated in an electrical field and impacted into a solid. This
process is used to change the physical, chemical, or electrical properties of the solid. Ion implantation is used in semiconduct
semiconductor
or
device fabrication and in metal finishing, as well as various applications.
Thin film: layer of material ranging from fractions of a nanometer to several micrometers in thickness
Photolithography: also termed optical lithography or UV lithography,
lithography, is a process used in microfabrication to pattern parts
of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light
light--sensitive
chemical "photoresist
"photoresist,
, or simply "resist," on the substrate. A series of chemical treatments then either engraves the exposure 5
pattern into, or enables deposition of a new material in the desired pattern upon, the material underneath the photo resist.
 INTRODUCTION CONT.

New technologies now allow densities in the range of 10 million devices per chip, a
magnitude that has been termed very large scale integration (VLSI). Some of the
advanced ICs may contain more than 100 million devices, termed ultra-large-scale
integration (ULSI).
Among more recent advances is wafer-scale integration (WSI), in which an entire
silicon wafer is used to build a single device. This approach has been of greatest
interest in the design of massively parallel supercomputers, which use multiple layers
of active circuits, maintaining connections both horizontally and vertically.

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 INTRODUCTION CONT.
Components of these micro devices HOW IS IT POSSIBLE?
are too small.
If they are too small to be seen with
our naked eyes then how is it possible
to manufacture and fabricate them?

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OUTLINE/FLOWCHART OF GENERAL FABRICATION
SEQUENCE FOR INTEGRATED CIRCUITS (ICS)

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 SINGLE CRYSTAL GROWTH
High-purity, semiconductor-grade silicon (only a few parts per million of
impurities) is melted in a crucible at 1425 degrees Celsius, usually made of quartz.
Dopant impurity atoms such as boron or phosphorus can be added to the molten
silicon in precise amounts to dope the silicon, thus changing it into p-type or n-type
silicon, with different electronic properties.
A precisely oriented rod-mounted seed crystal is dipped into the molten silicon. The
seed crystal's rod is slowly pulled upwards and rotated simultaneously.

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 SINGLE CRYSTAL GROWTH CONTD.
By precisely controlling the temperature gradients, rate of pulling and speed of rotation, it
is possible to extract a large, single-crystal, cylindrical ingot from the melt. Occurrence of
unwanted instabilities in the melt can be avoided by investigating and visualizing the
temperature and velocity fields during the crystal growth process.
Performed in an inert atmosphere, such as argon, in an inert chamber, such as quartz.
Above mentioned process is Czochralski or CZ process and the result obtained is a
cylindrical single-crystal ingots of 100-300mm diameter and over 1m (14 in) long.

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 SILICON WAFERS PREPARATION
Silicon ingots are produced from silicon ingots
by sequence of machining and finishing operation
as illustrated in fig.
Crystal are sliced into individual wafers by using
inner-diameter diamond-encrusted blade whereby
a rotating, ring-shaped blade with its cutting edge
on the inner diameter of the ring is utilized.
The wafer is then ground along its edges using a
diamond wheel. This operation gives the wafer a
rounded prole, which is more resistant to
chipping.
Finally, the wafers must be polished and cleaned,
to remove surface damage caused by the sawing
process. This operation is commonly performed
by chemicalmechanical polishing

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 FILM DEPOSITION
Films can be deposited by several techniques:
Vacuum deposition
Sputtering
Chemical-vapor deposition
Plasma-enhanced chemical-vapor deposition

Why Film Deposition is required?

include fewer impurities, especially carbon and oxygen, improved device performance, and the tailoring
of material properties (which cannot be done on the wafers themselves).
Some of the major functions of deposited lms are masking and protecting the semiconductor surface. In
masking applications, the lm must both inhibit the passage of dopants and concurrently display an
ability to be etched into patterns of high resolution.
Upon completion of device fabrication, lms are applied to protect the underlying circuitry. Films used
for masking and protecting include silicon dioxide, phosphor-silicate glass (PSG), and silicon nitride.
Each of these materials has distinct advantages, and they often are used in combination.

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 OXIDATION
The growth of an oxide layer as a result of the reaction of oxygen with the substrate material.
Dry oxidation:
accomplished by elevating the substrate temperature to about7501100C in an oxygen-rich environment.
As a layer of oxide forms, the oxidizing agents must be able to pass through the oxide and reach the silicon surface,
where the actual reaction takes place. Thus, an oxide layer does not continue to grow on top of itself, but rather, it
grows from the silicon surface outward. Some of the silicon substrate is consumed in the oxidation process.
The ratio of oxide thickness to the amount of silicon consumed is found to be 1:0.44; to obtain an oxide layer 1000
thick, approximately 440 of silicon will be consumed.
Wet oxidation:
utilizes a water-vapor atmosphere as the agent.
results in a considerably higher growth rate than that of dry oxidation, but it suffers from a lower oxide density and,
therefore, a lower dielectric strength.
The common practice in industry is to combine both dry and wet oxidation methods to combine the
advantages of wet oxidations much higher growth rate and dry oxidations high quality by growing an
oxide in a three-part layer : drywetdry.

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 PHOTOLITHOGRAPHY
the desired reticle(photomask) patterns is generated, the wafer is cleaned and coated
with a photoresist.
A photoresist consists of three principal components:
1. A polymer that changes its structure when exposed to radiation
2. A sensitizer that controls the reactions in the polymer
3. A solvent, to deliver the polymer in liquid form

Photoresist layers of 0.52.5 m thick are produced by applying the photoresist to the
substrate and then spinning it, at 1200-4800 rpm, for 30 or 60 s to give uniform
coverage.

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 PHOTOLITHOGRAPHY CONTD.
Prebaking the wafer, which remove the solvent from the photoresist and
harden it. It is carried out on a hot plate, heated to around 100C.
The wafer must be aligned carefully under the desired reticle. Once the
reticle is aligned, it is subjected to ultraviolet (UV) radiation. Upon
development and removal of the exposed photoresist.
In positive photoresist UV exposed region becomes soluble when chemical
is treated and is washed away but in negative photoresist the unexposed
region becomes soluble and they are washed away.

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 PHOTOLITHOGRAPHY CONTD
Pictorial representation of the photolithography

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 PHOTOLITHOGRAPHY CONTD.
The underlying film not covered with photoresist is then etched away.
The developed photoresist must be removed, in a process called stripping.
wet stripping: the photoresist is dissolved by acetone or strong acids.
Dry stripping: involves exposing the photoresist to an oxygen plasma.
The pattern resolution in photolithography is ultimately limited by light diffraction
of shorter wavelengths.
The process is repeated to obtain different geometry many time necessary to
complete the chip circuit design.

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 ETCHING
Process by which entire lms or particular sections of lms are removed.
For many etch steps, part of the wafer is protected from the etchant by a
"masking" material which resists etching. the masking material is a photo-
resist which has been patterned using photolithography.
One of the key criteria in this process is selectivity, that is, the ability to etch
one material without etching another. In silicon technology, an etching
process must etch the silicon-dioxide layer effectively, with minimal removal
of either the under lying silicon or the resist material.

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 METHODS OF ETCHING
WET ETCHING DRY ETCHING
Involves immersing the wafers in a liquid Involves the use of chemical reactants in a
solution, usually acidic. low-pressure system.
Etch in all directions of the workpiece at Have a high degree of directionality,
the same rate isotropy results in undercuts resulting in highly anisotropic etching
beneath the mask material, and thus limits proles.
the resolution of geometric features in the Requires only small amounts of the reactant
substrate. gases.
Reliable etching requires both proper Dry etching usually involves a plasma or
temperature control and repeatable discharge in areas of high electric and
stirring capability. magnetic elds

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 DIFFUSION
Microelectronic devices of different electrical characteristics depends on
regions that have different doping types and concentrations introduced by
diffusion.
In the diffusion process, the movement of atoms is a result of thermal
excitation. Dopants can be introduced to the substrate surface in the form of a
deposited lm or the substrate can be placed in a vapor, containing the dopant
source. The process takes place at temperatures usually 8001200C.

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 ION IMPLANTATION
Accomplished by accelerating the ions through a high-voltage eld of
as much as 1 million electron volts, and then by choosing the desired
dopant by means of a mass separator. In a manner similar to that of
cathode-ray tubes, the beam is swept across the wafer by sets of
deection plates, thus ensuring uniformity of coverage of the substrate.
The whole implantation operation must be performed in a vacuum.
The high-velocity impact of ions on the silicon surface damages the
lattice structure and results in lower electron mobility. Although this
condition is undesirable, the damage can be repaired by an annealing
step, which involves heating the substrate to a temperature, usually
400800C (7501500F), for a period of 1530 min. Annealing
provides the energy that the silicon lattice needs to rearrange and
mend itself. Another important function of annealing is driving in the
implanted dopants. Implantation alone imbeds the dopants less than
half a micron below the silicon surface; annealing enables the dopants
to diffuse to a more desirable depth of a few microns.

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 METALLIZATION
Device fabrication-generating a complete functional IC-requires all devices must be
interconnected and this must takes place in number of levels
Interconnections are made using metals that exhibit low electrical resistance and good adhesion to
dielectric insulator surfaces. Aluminum and aluminumcopper alloys remain the most commonly
used materials for this purpose in VLSI technology today.
Reduction in size of device electron migration(process by which aluminium atom moves
physically by the impact of drifting electrons under high currents) in extreme cases leads to
severed or shorted metal lines.
solution
1.) Addition of sandwich metal layers such as tungsten and titanium.
2.) Use of pure copper-lower the resistivity; better electron migration performance than aluminium
Metals are deposited by standard deposition techniques, an operation called metallization.
Modern ICs typically have one to six layers of metallization, each layer of metal being insulated
by a dielectric. Interconnection patterns are generated through lithographic and etching processes.
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 TESTING
Test each of individual circuit on wafer.
Each chip, also known as a die, is tested by a computer-controlled probe platform, containing needlelike
probes that access the bonding pads on the die.
The probes are of two forms:
1. Test patterns or structures: The probe measures test structures, often outside of the active die, placed in the scribe
line (the empty space between dies); these probes consist of transistors and interconnect structures that measure various
processing parameters, such as resistivity, contact resistance, and electro migration.
2. Direct probe: Involves 100% testing on the bond pads of each die. The platform scans across the wafer and uses
computer-generated timing waveforms, to test whether each circuit is functioning properly.

If a chip is defective, it is marked with a drop of ink.

After the wafer-level testing is completed, back grinding may be done to remove a large amount of the
original substrate. The nal die thickness depends on the packaging requirement, but anywhere from 25
to 75% of the wafer thickness may be removed.
Diamond sawing is a commonly used separation technique and results in very straight edges, with
minimal chipping and cracking damage.
The chips are then sorted, the functional die are sent on for packaging, and the inked dice are discarded.

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WIRE BONDING
Working device must be attached to more rugged
foundation to ensure reliability, one simple
method is to fasten a die to its packing material-
2ways-1.)epoxy cement 2.)eutectic bonding
(mixture of 96.4% Al and 3.6% Si @ 370 oC)
Once chip has been attached to substrate it must
be connected electrically to the package leads by
wire bonding very thin (25 m diameter; 0.001
in.) gold wires from the package leads to
bonding pads, located around the perimeter or
down the center of the die.
The bonding pads on the die are typically drawn
at 75100 m per side, and the bond wires are
attached by means of thermo-compression,
ultrasonic, or thermo-sonic techniques.

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 PACKAGING
Determines overall cost of each completed IC
Considerations:- chip size, number of external leads, operating environment,
heat dissipation and power requirements. Example; military and industrial
application requires packages of particularly high strength, toughness and
resistance to temperature.
Produced from polymers, metals and ceramics
Metals containers are made from alloys such as KOVAR (Iron, Cobalt and
Nickel alloy with low coefficient of expansion), which provides hermetic seal
and good thermal conductivity but limited in number of leads that can be used.
Ceramic packages usually produced from aluminium oxide(Al2O3), which
provide a hermetic seal and have good thermal conductivity and have higher
number of lead count than metal packages but they are bit more expensive
Plastic packages are inexpensive, have high number of lead counts but they
can not withstand high temperature and are not hermetic

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 CONCLUSION
The microelectronics industry continues to develop rapidly, and
possibilities for new device concepts and circuit designs appear to be
endless. The fabrication of microelectronic devices and integrated circuits
involves several different types of processes.

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ANY QUIRES?

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