e-Infochips Institute of Training Research and Academics Limited

IMPLEMENTATION OF AHB
PROTOCOL USING VERILOG

Presented By: Nirav Desai(13014061003) Guided By: Rajesh Navandar

TABLE OF CONTENT

Advanced High Performance Bus

Features of AHB BUS
AMBA 2.0
Components in AHB
AHB Signals
Request / Grant Protocol
Pipelined Transactions
RTL Diagrams of all modules
Simulation Result of all modules
Advantages
References

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Advanced High Performance Bus

AHB is a new generation of AMBA bus which is intended to address the

requirements of high-performance synthesizable designs.
It is a high-performance system bus that supports multiple bus masters and
provides high-bandwidth operation.

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Features of AHB BUS

AMBA AHB implements the features required for high-performance, high

clock frequency systems
Including:
Burst transfers
Split transactions
Single-cycle bus master handover
Single-clock edge operation
Wider data bus configurations (64/128 bits).

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AMBA 2.0

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Components in AHB

Master
AHB master is able to initiate read and write operations by providing an
address and control information. Only one bus master is allowed to actively use
the bus at any one time.(max. 16)
Slave
AHB slave responds to a read or write operation within a given address-space
range. The bus slave signals back to the active master the success, failure or
waiting of the data transfer.

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Components in AHB

Arbiter
AHB arbiter ensures that only one bus master at a time is allowed to initiate
data transfers.
Decoder
AHB decoder is used to decode the address of each transfer and provide a
select signal for the slave that is involved in the transfer. A single centralized
decoder is required in all AHB implementations.

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AHB Response Signals

Response signals
HREADY
Transfer done, ready for next transfer
HRESP[1:0]
OKAY transfer complete
ERROR transfer failure(ex: write ROM)
RETRY higher priority master can access bus
SPLIT other master can access bus

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AHB Arbitration Signals

Arbitration signals
HGRANTx
Select active bus master
HMASTER[3:0]
Multiplex signals that sent from master to slave
HMASTLOCK
Locked sequence

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Master Signals

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Arbiters Signals

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Slave Signals

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Request / Grant Protocol

Request
IP Block #1
CPU #1

IP Block #2
CPU #2
IP Block #3

IP Block #1
IP Block #4

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Request / Grant Protocol

Request
IP Block #1
Grant
CPU #1

IP Block #2
CPU #2
IP Block #3
IP Block #1

IP Block #4

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Request / Grant Protocol

Request
IP Block #1
Grant
CPU #1
Transaction
IP Block #2
CPU #2
IP Block #3

IP Block #1 IP Block #4

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Request / Grant Protocol

Before a transaction a master makes a

request to the central arbiter

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Request / Grant Protocol

Before a transaction a master

makes a request to the central Eventually the request is granted
arbiter

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Request / Grant Protocol

Then the
transaction
proceeds

Before a transaction a master

makes a request to the central Eventually the request is granted
arbiter

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Request / Grant Protocol

Performance Impact

Then the
transaction
proceeds

Before a transaction a master makes a Eventually the request is granted

request to the central arbiter

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Pipelined Transactions

To help improve bus efficiency the transactions on

the bus can be pipelined

This is really a simple implementation of multiple

outstanding transactions

The address for one transaction can be presented

before the data from the previous transaction has
been completed

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Pipelined Transactions

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Pipelined Transactions

Transaction A Starts

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Pipelined Transactions

Transaction A Starts Transaction B Starts

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Pipelined Transactions

Transaction A Completes
Transaction A Starts Transaction B Starts

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Connections of AHB masters

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Connection of AHB slaves

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Arbiter RTL

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Arbiter Simulation Result

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Decoder RTL

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Decoder Simulation Result

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MUX Slave To Master RTL

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MUX Slave To Master Simulation Result

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MUX Master to Slave RTL

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MUX Master to Slave Simulation Result

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MUX peripherals to bridge RTL

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MUX peripherals to bridge Simulation Result

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Advantages

Relatively easy to add new blocks

Still has the familiar bus structure
Low hardware cost
Bus arbitration solves many ordering problems

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Disadvantages
Busses that require arbitration:
must route signals to the arbitration logic and back
must find a fair way to share the bus
slaves are not always available => backpressure
difficult to provide performance guarantees...

Still potentially a bandwidth bottleneck

Still doesnt scale well when blocks are added

Multiple outstanding transactions not handled well -

no ordering information

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References

[1] AMBA Specification, Rev. May, 2.0, 1999.

[2] High-Speed Single-Port SRAM (HS-SRAM-SP) Generator User Manual,
Artisan Components Inc., Release 4.0, Aug. 2000.
[3] Debussy User Guide and Tutorial, NOVAS Software Inc., Sept. 2002.
[4] Compatibility of Network SRAM and ZBT SRAM, Mitsubishi LSIs
Application Note (AP-S001E), Rev. C, Renesas Tech. Corp., Sept. 2002.
[5] DesignWare AHB Verification IP Databook, ver. 2.0a, Synopsys Inc., July
2002.
[6] VMT User Manual, Release 2.0a, Synopsys Inc., July 2002.
[7] Vera User Guide, ver. 5.1, Synopsys Inc., June 2002.
[8] SolidAMBA, Averant Inc., Dec. 2003.

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 Thank you

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