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7 Theoretical Framework
This section will provide an overview of the major blocks used in the study and also its

specifications and theories of operation. This section will also present the technology being used

in the entire project:

Figure 1.2: openMSP430 design structure.

1.7.1 openMSP430 Microcontroller core

The openMSP430 core is a synthesizable 16-bit microcontroller core compatible

with Texas Instruments MSP430 family. It is based on a Von Neumann architecture, with a single

address space for instructions and data. Depending on the selected configuration, this design can

either be [5]:

FPGA friendly: the core doesnt contain any clock gate and has only a single clock

domain. As a consequence, in this mode, the Basic Clock Module peripheral has a

few limitations.
ASIC friendly: the core contains up to all clock management options (clock muxes

and low-power modes, fine grained clock gating,..) and is also ready for scan


The design architecture shown in Fig. 2 consists of the following blocks:

Frontend this module performs the instruction Fetch and Decode tasks. It also contains

the execution state machine.

Execution unit contains the ALU and the register file, this module executes the current

decode instruction according to the execution state.

Serial Debug Interface contains all the required logic for Nexus class 3 debugging unit

(without trace). Communication with the host is performed with a standard two-wire

interface following the UART 8N1 or I2C serial protocol.

Memory Backbone this block performs a simple arbitration between front end,

execution-unit, DMA and Serial-Debug interfaces for program, data and peripheral

memory access.

Basic Clock Module generates MCLK, ACLK, SMCLK and manage the low power


SFR Special Function Registers block contain diverse configuration registers (NMI,

Watchdog, and etc).

Watchdog although it is a peripheral, the watchdog is directly included in the core

because of its tight links with the NMI interrupts and PUC reset generation.

16x16 Multiplier the hardware multiplier peripheral is transparently supported

by the GCC compiler and is therefore located in the core. It can be included or excluded at

will through Verilog.

1.7.2 Flash Memory

Flash memory is an electronic non-volatile computer storage memory that can be

electrically erased and reprogrammed. It offers fast read access time (although not as fast as

volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than

hard disks. Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while

working for Toshiba circa 1980. According to Toshiba, the name flash was suggested by Dr.

Masuokas colleague, Mr. Shoji Ariizumi, because the erasure pressure of the memory contents

reminded him of flash of a camera [1]. Flash memory retains data for an extended period of time

even if the power is turned off.

Flash memory evolved from erasable programmable read-only memory (EPROM) and

electrically erasable programmable read-only memory (EEPROM). Flash is technically a variant

of EEPROM but the industry reserves the EEPROM for byte-level erasable memory and applies

the term flash memory to larger block-level erasable memory. Devices using flash memory erase

data at the block level and rewrite data at the byte level (NOR flash) or multiple-byte page level

(NAND flash). Flash memory is widely used for storage and data transfer in consumer devices,

enterprise systems and industrial applications [6]. Operations of Flash Memory

A basic flash memory cell consists of a storage transistor with control gate and a floating

gate which is insulated from the rest of the transistor by a thin dielectric material or oxide layer.

The floating gate stores the electrical charge and controls the flow of the electrical current.
Figure 1.3. Cross section of a Floating Gate Flash Memory cell.

Electrons are added to or removed from the floating gate to change the storage transistors

threshold voltage to program the cell to be a zero or a one. A process called Fowler-Nordheim

tunneling removes electrons from the floating gate. Either Fowler-Nordheim tunneling or a

phenomenon known as channel hot-electron injection traps the electrons in the floating gate.

When erasing through Fowler-Nordheim tunneling, a strong negative charge on the control

gate forces electrons off the floating gate and into the channel, where a strong positive charge

exists. The reverse happens when using Fowler-Nordheim tunneling to trap electrons in the

floating gate. Electrons are able to forge through the thin oxide layer to the floating gate in the

presence of a high electric field, with a strong negative charge on the cells source and the drain

and a strong positive charge on the control gate.

Figure 1.4: Fowler-Nordheim Tunneling

With channel hot-electron injection (or hot-carrier injection), electrons gain enough energy

from the high current in the channel and attracting charge on the control gate to break through the

gate oxide and change the threshold voltage of the floating gate. Electrons are trapped in the

floating gate, whether a device containing the flash memory cell is powered on or off, because of

the electrical isolation created by the oxide layer.

Figure 1.5: Channel Hot-Electron Injection

EPROM and EEPROM cells operate similarly to flash memory in writing, or

programming, data, but they differ from flash memory in the way they erase data. An EPROM is

erased by removing the chip from the system and exposing the array to ultraviolet light to erase

data. An EEPROM erases data electronically at the byte level, while flash memory erases data

electronically at the block level [8].

1.7.3 Comparison of NOR and NAND

NOR and NAND flash memory differ in architecture and design characteristics. NOR flash

uses no shared components and can connect individual memory cells in parallel, enabling random

access to data. A NAND flash cell is more compact in size, with fewer bit lines, and strings together

floating-gate transistors to achieve greater storage density. NAND is better suited to serial rather

than random data access.

NOR flash is fast on data reads, but it is typically slower than NAND on erases and writes.

NOR flash programs data at the byte level. NAND flash programs data in pages, which are larger

than bytes but smaller than blocks. For instance, a page might be 4 kilobytes (KB), while a block

might be 128 KB to 256 KB or megabytes in size. NAND flash uses less power than NOR flash

for write-intensive applications.

Flash is the least expensive form of semiconductor memory. Unlike dynamic random

access memory (DRAM) and static RAM (SRAM), flash memory is nonvolatile, offers lower

power consumption and can be erased in large blocks. Also on the plus side, NOR flash offers fast

random reads, while NAND flash is fast with serial reads and writes.

Figure 1. 6. NAND and NOR performance comparison.

A solid-state drive (SSD) with NAND flash memory chips delivers significantly higher

performance than traditional magnetic media such as hard disk drives (HDDs) and tape. Flash

drives also consume less power and produce less heat than HDDs. Enterprise storage systems
equipped with flash drives are capable of low latency, which is measured

in microseconds or milliseconds.

The main disadvantages of flash memory are the wear-out mechanism and cell-to-cell

interference as the dies get smaller. Bits can fail with excessively high numbers of program/erase

cycles, which eventually break down the oxide layer that traps electrons. The deterioration can

distort the manufacturer-set threshold value at which a charge is determined to be a zero or a one.

Electrons may escape and get stuck in the oxide insulation layer leading to errors. Anecdotal

evidence suggests NAND flash drives are not wearing out to the degree once feared. Flash drive

manufacturers have improved endurance and reliability through error correction

code algorithms, wear leveling and other technologies. In addition, SSDs do not wear out without

warning. They typically alert users in the same way a sensor might indicate an underinflated tire.

1.7.4 NAND Flash Memory

NAND flash semiconductor manufacturers have developed different types of memory

suitable for a wide range of data storage uses cases. The following are the various types of NAND

flash memory:

Single-level cell (SLC). Stores one bit per cell and two levels of charge and has higher

performance, endurance and reliability than other types of NAND flash but is more expensive than

other types of NAND flash. It is primarily used in enterprise storage and mission-critical


Multilevel cell (MLC). Can store multiple bits per cell and multiple levels of charge. The

term MLC equates to two bits per cell. Cheaper than SLC and enterprise MLC (eMLC), and also
has a high density but lower endurance than SLC and eMLC and is slower than SLC. Commonly

used in consumer devices and enterprise storage.

Enterprise MLC (eMLC). Typically stores two bits per cell and multiple levels of charge; uses

special algorithms to extend write endurance. Less expensive than SLC flash and has greater

endurance than MLC flash. The disadvantage of eMLC is that it is more expensive than MLC but

slower than SLC. It used in enterprise applications with high write workloads.

Triple-level cell (TLC). Stores three bits per cell and multiple levels of charge. Also referred to

as MLC-3, X3 or 3-bit MLC. Lower cost and higher density than MLC and SLC but lower

performance and endurance than MLC and SLC. It used in mass storage consumer applications,

such as USB drives, flash memory cards, smartphones, and client SSDs and datacenter SSDs for

read-intensive workloads.

Vertical/3D NAND. Stacks memory cells on top of each other in three dimensions vs. traditional

planar NAND technology. Has higher density, higher write performance and lower cost per bit vs.

planar NAND but has higher manufacturing cost than planar NAND and is difficult to manufacture

using production planar NAND process. It also has lower data retention. Used in consumer and

enterprise storage.

Note: NAND flash wear-out is less of a problem in SLC flash than it is in less expensive types of

flash, such as MLC and TLC, for which the manufacturers may set multiple threshold values for a

charge. The commonly cited industry wear-out figures are 100,000 program/erase (write/erase)

cycles for SLC NAND flash, 30,000 for eMLC, 10,000 or fewer for MLC, and 3,000 or fewer for

TLC. Actual endurance figures may be higher.

1.7.5 NOR Flash Memory

The two main types of NOR flash memory are parallel and serial (also known as serial

peripheral interface). NOR flash originally was available only with a parallel interface. Parallel

NOR offers high performance, security and additional features; its primary uses include industrial,

automotive, networking, and telecom systems and equipment. Serial NOR flash has lower pin

counts and smaller packaging and is less expensive than parallel NOR. Use cases for serial NOR

include personal and ultra-thin computers, servers, HDDs, printers, digital cameras, modems and

routers [8].

1.7.6 Register Transfer Level (RTL)

In digital circuit design, register-transfer level (RTL) is a design abstraction which models

a synchronous digital circuit in terms of the flow of digital signals (data) between hardware

registers, and the logical operations performed on those signals. A synchronous circuit consists of

two kinds of elements: registers and combinational logic. Registers (usually implemented as

D flip-flops) synchronize the circuit's operation to the edges of the clock signal, and are the only

elements in the circuit that have memory properties. Combinational logic performs all the logical

functions in the circuit and it typically consists of logic gates. When designing digital integrated

circuits with a hardware description language, the designs are usually engineered at a higher level

of abstraction than transistor level (logic families) or logic gate level. In HDLs the designer

declares the registers (which roughly correspond to variables in computer programming

languages), and describes the combinational logic by using constructs that are familiar from

programming languages such as if-then-else and arithmetic operations. This level is called register-

transfer level. The term refers to the fact that RTL focuses on describing the flow of signals

between registers [9]. Using an EDA tool for synthesis, this description can usually be directly

translated to an equivalent hardware implementation file for an ASIC or an FPGA.

The synthesis tool also performs logic optimization. At the register-transfer level, some types of

circuits can be recognized. If there is a cyclic path of logic from a register's output to its input (or

from a set of registers outputs to its inputs), the circuit is called a state machine or can be said to

be sequential logic. If there are logic paths from a register to another without a cycle, it is called

a pipeline.

RTL is used in the logic design phase of the integrated circuit design cycle. An RTL

description is usually converted to a gate-level description of the circuit by a logic synthesis tool,

for example Design Compiler by Synopsys. The synthesis results are then used

by placement and routing tools to create a physical layout [9].

1.7.7 Application Specific Integrated Circuit (ASIC)

An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized

for a particular use, rather than intended for general-purpose use. Application-specific standard

products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like

the 7400 or the 4000 series. As feature sizes have shrunk and design tools improved over the years,

the maximum complexity (and hence functionality) possible in an ASIC has grown from
5,000 gates to over 100 million. Modern ASICs often include

entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and

other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers of

digital ASICs often use a hardware description language (HDL), such as Verilog or VHDL, to

describe the functionality of ASICs [10].

1.7.8 ST M2540

The M25P40 is a 4Mbit (512k x8) Serial Flash memory with advanced write protection

mechanisms, accessed by high speed SPI-compatible bus. The memory can be programmed 1 to

256 bytes at a time, using the Page Program Instruction.

The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The

whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the

Sector Erase instruction. Figure 1.7 shows the memory schematic and Table 1.1 explains the pin


Figure 1.7. M25P40 Table 1.1. Memory Pin Description