I / O INTERFACE

Accessing I/O Devices

Processor Memory

I/O Device 1 I/O Device 2

 Parallel I/O
I/O devices connect to processor through PORTS
Ports are:
registers (part of the I/O interface)
8, 16, or 32 bits wide
Addressed Range
Accessed using instructions
 Modes of I/O Instructions
Direct I/O the port address is one of the operands.
Indirect I/O the port address is preloaded into one
of the registers
String I/O allows data to pass directly through the
accumulator (from I/O device to memory)
 Memory-Mapped I/O
I/O Devices and memory share the same
address space.
Each I/O Device is assigned a unique set of addresses.
When the processor places a particular address on the
address lines, the device recognizing this address
responds to the commands on the control lines.
The processor requests either a read or a write
operation, and the requested data is transferred over the
data lines.
Any machine instruction that can access memory can
be used to transfer data to/from I/O devices.
Ways to Drive Hardware Devices
using Parallel Buses
Programmed I/O through I/O ports

Interrupt I/O using (hardware) interrupts

Direct Memory Access

 Programmed I/O
(driving Hardware devices through I/O ports)

External devices are almost always connected not

directly to the system bus but to an INTERFACE.
Registers in the interface allow for a wide range
of possibilities for the designer to determine how
it is to interface to the bus.
Peripheral interface chip registers are usually
referred to as PORTS.
 Interface Ports
Typically consists of three registers
Control Port - the setting of which will determine if the
interface is to send or receive.
Data Port for the data element to be transmitted or to
hold a data element received.
Status Port used to obtain information such as
printer out of paper, dont send any more data or, for
a serial transmission, all the bits of the data element
havent yet been received
Simple interfaces may have status and control
combined into one port; sophisticated ports may have
multiple control and status ports.
 I/O Interface for an Input Device
Address Lines
Data Lines
Control Lines

Address Control Data and

Decoder Circuits Status Registers

I/O Interface

Input Device
 I/O Device Speeds
Processors can operate at speeds that are vastly
different than I/O speeds.
When a human is entering characters on a keyboard,
the processor can execute millions of instructions
between successive character entries.

So, how does the processor handle I/O inputs..

 Three types of I/O Strategies
Polled I/O

Interrupt Driven I/O

DMA I/O
Polled IO versus Interrupt Driven I/O
Polled IO processor continually checks IO
device to see if it is ready for data transfer
Inefficient, processor wastes time checking for ready
condition
Interrupt Driven IO IO device interrupts
processor when it is ready for data transfer
Processor can be doing other tasks while waiting for
last data transfer to complete very efficient.
 I/O Interfacing
A lot of handshaking is required between
the CPU and most I/O devices.
All I/O devices operate asynchronously
with respect to the CPU. The events that
determine when an input device has data
available or when an output device needs
data are independent of the CPU.
 Must be capable of data rates fast enough to
keep up with the demands of the device, but
must not be allowed to transfer data faster
than the device can process it.
Polled waiting loops
Interrupt-driven I/O
Direct memory Access (DMA)
 Synchronization
The CPU must have some way of checking
the status of the device and waiting until it
is ready to transfer
 Transfer Rate
A measure of the number of bytes per
second transferred between the CPU and an
external device.
Maximum transfer rate a measure of the
bandwidth capability of a particular method
of doing I/O.

 Comparison of transfer rates
Polled waiting loops provide data rates that are a
bit slower, but still quite reasonable.
Interrupt-driven I/O requires overhead of saving
and restoring the machine state (significantly
degrades data rates unless more than one byte can
be transferred per interrupt.
DMA has fastest transfer rates (additional
hardware complexity needed.
 Latency
Measure of the delay from the instant that
the device is ready until the time the first
data byte is transferred. Latency is
equivalent to the response time
 Comparison of Latency
Polled Waiting Loops latency can be very
high (the computer may not even be
checking the device for new data when it
arrives).
Interrupt-driven I/O dramatically lower
than polled, but still imposes a software
overhead.
DMA very low (lower than the others)
 Polled Waiting I/O
Use software to test the status of a
device,before transferring each data byte.
Continuously checking the peripherals
BUSY/READY flag
Ties up the CPU no other tasks can be
performed.
 I/O Systems
interrupts
Processor

Cache

Memory - I/O Bus

Main I/O I/O I/O

Memory Controller Controller Controller

Disk Disk Graphics Network

There are several ways of interfacing I/O devices to the CPU

Either through the cache, the memory bus or through a separate
I/O bus. In the figure this is a low-cost option the memory bus is
the I/O bus.
 I/O Interface
CPU Memory
Independent I/O Bus memory
connected through bus
the cache

Interface Interface Seperate I/O instructions

Adv: less state-data problem
Peripheral Peripheral Disa: slow

CPU
common memory
& I/O bus

Memory Interface Interface

Peripheral Peripheral
 Example of an Interface
Interface to system bus
data registers
control/status registers
I/O logic used for decoding commands from the processor such as
read, write, scan, address recognition, status reporting etc.
External device interface (data, status, control)
function of the interface:
control and timing
processor communication
device communication
data buffering
error correction
Next how does the CPU address an I/O device to send or receive data?
 Memory Mapped I/O
CPU
Single Memory & I/O Bus
No Separate I/O Instructions
ROM

Memory Interface Interface RAM

Peripheral Peripheral

I/O

In this mode, there is a single address space for memory locations and
I/O devices. Each I/O device will have unique addresses for its data and
status registers which are treated just like any other memory location.
The bus will contain data and address lines and some I/O command lines
The command line specifies whether the address refers to a memory
location or an I/O device.
The alternative solution is isolated I/O address space and I/O opcodes.
In this case I/O ports are only accessible by special I/O instructions.
 Programmed I/O (Polling)
1. The CPU
CPU periodically
checks status
bits to see if
there is I/O
Memory IOC operation.

device 2. busy wait loop

3. The CPU ends
up doing all 4.Not an efficient way to
the work! use the CPU
unless the device
is very fast!
The problem with this method is that the processor has to
wait for a long time for the I/O module of concern to be ready
for either reception or transmission of data. The processor
while waiting must repeatedly interrogate the module.
 Interrupt Driven Data Transfer
CPU add
sub user
(1) I/O and program
interrupt or
nop
Memory IOC (2) save PC

(3) interrupt
device service addr
read
store interrupt
... service
User program progress only halted during (4) rti routine
actual transfer memory
to deal with different I/O devices, interrupt
mechanisms have several levels of priority. These
priorities indicate the order in which the processor
should process the interrupts.
 Direct Memory Access Controllers

A solution to that is the DMA:a mechanism for

off-loading the processor and having the device
controller transfer data directly to or from memory
without involving the processor.
The interrupt mechanism is still used by the I/O
device to communicate with the processor but
only on completion of an I/O transfer.
DMA is implemented with a specialized controller
that transfers data between an I/O device and the
memory independent of the processor.
 Direct Memory Access Controllers
Step 1: CPU sets up the DMA by
supplying the identity of the device, the
operation to perform, the memory address,
and the number of bytes to transfer.

Step2: DMA starts operation and arbitrates

for the bus, and transfers the data.

Step3: Once DMA transfer is complete, the

controller interrupts the processor.
 Direct Memory Access

CPU sends a starting address,

direction, and length count to
DMAC. Then issues "start".

CPU

Memory DMAC IOC

device

DMAC provides handshake signals for Peripheral

Controller, and Memory Addresses and handshake
signals for Memory.
 Input/Output Processors
CPU IOP D1

main memory D2
Mem bus . . .
Dn
I/O
bus
CPU
(1) (4) issues instruction to IOP
IOP interrupts when done
(2)

(3) memory

Device to/from memory

transfers are controlled
by the IOP directly.

IOP steals memory cycles.

 I/O, Exceptions and Interrupts

Handling I/O efficiently is a key requirement

Exceptions (& interrupts) allow processors to handle
events that occur which are not directly related to
the user program
Exceptions typically caused by unexpected run-time
errors in user code (e.g. division by 0)
Interrupts special case of exception caused by
hardware conditions that require processor action e.g.
I/O service: completely independent of user code
 Hardware for I/O - Overview
I/O devices communicate via memory-mapped registers
DMA & Interrupts are optional

other
Memory devices
I/O device I/O device

Interrupt
Databus controller
Address bus

Direct Memory
CPU Access (DMA)
IRQ FIQ Controller
other devices
 Method 1: Polling
CPU repeatedly reads status bit from serial port (bit 31 of
PORT_STATUS here) to determine if new data is available
When needed it reads data from PORT_DATA(7:0)
Polling is simple, requires no additional hardware
Requires 100% CPU use, inefficient, inflexible
IO_SERVICE_CODE
ADRL R10, SER_PORT ; R10--> SERIAL_PORT
ADR R11, BUFFER ; R11-> array of bytes read
POLL_LOOP ; example of polling I/O
LDR R0, [R10,#PORT_STATUS];input status
CMP R0, #0
BPL POLL_LOOP ; wait till port is ready b31=1
LDRB R0, [R10,#PORT_DATA] ; input data
STRB R0, [R11], #1 ; store data in memory
B POLL_LOOP ; repeat
 Method 2: Interrupt

CPU executes user code independently of I/O

I/O device raises interrupt line when it requires
service
CPU receives interrupt, suspends current execution,
handles device in an interrupt service routine, then
returns to previous execution as though nothing had
happened
Interrupt is invisible to executing code except is
small loss of speed
 Interrupt Hardware for ARM

other
Memory devices
I/O device I/O device

Interrupt
Databus controller
Address bus

ARM has two interrupt inputs: IRQ & FIQ

CPU Optional Interrupt controller allows more
IRQ FIQ I/O devices to use 2 interrupt lines
 Anatomy of an interrupt exception
The interrupt causes user code
to suspend and a branch to a User Mode: Exception
fixed hardware determined
memory location - so-called MOV
interrupt "vector" (labelled ADD
IRQ_VEC here) IRQ_VEC B IRQ_SUB
MOV
CPU enters IRQ mode BEQ
The vector contains a single LDR
branch to a software-determined ADD
interrupt service routine
STR
IRQ_SUB return
When the interrupt has been IRQ_SUB ; handler code
dealt with the ISR makes an ; .
interrupt return SUBS pc, r14, #4
Interrupt
User code continues execution service
as though interrupt had never
routine IRQ Mode
happened - no register is
disturbed
 ARM Operating Modes
The ARM processor can work in one of many operating
modes. So far we have considered user mode, which is the
"normal" mode of operation.
The processor can also enter "privileged" operating modes
which are used to handle exceptions and SWIs
The Current Processor Status Register CPSR has 5 bits [bit4:0] to
indicate which mode the processor is in:-

Mode bits
 Shadow Registers Clever Feature of ARM
ISA enables Exceptions
As the processor enters an exception mode, some new registers are
automatically switched in to avoid overwriting user regs:-

(FIQ Mode): MOV R6, R8

(User Mode):MOV R6, R8

 Shadow Registers Key points

For example, an external event (such as movement of the

mouse) occurs that generates a Fast Interrupt (on the FIQ
pin), the processor enters FIQ operating mode.
It sees the same r0 - r7 as before, and a new set of shadow r8
- r14
By swapping to the new registers, it is easier for the programmer to
preserve the state of the processor.
For example, during FIQ mode, the FIQ versions of r8 - r14 can be used
freely. On returning back to user mode, the original values of r8 - r14 will
never have changed.
The shadow r8-r14 preserve their values across FIQ
interrupts and can be used to store persistent FIQ state.
 What happens when an exception occurs?
ARM completes current instruction as best it can.
It departs from current instruction sequence to handle the
exception by performing the following steps:-
1. It changes the operating mode corresponding to the particular
exception.
2. It saves the current PC in the R14 corresponding to the new
mode. For example, if FIQ occurs, the PC value is stored in
R14(FIQ). This will be the return address
3. It saves the old value of CPSR in a special register of the new
mode.
4. It disables exceptions of lower priority
5. It forces the PC to a new value corresponding to the exception.
This is effectively a forced jump to the Exception Handler or
Interrupt Service Routine.
 Exception vector addresses

Each vector (except FIQ) is 4 bytes long (i.e. one instruction) at

a fixed position in low memory.
You put a branch instruction at this address, e.g.:
B svc_exception_handler
 Exception Return
Once the exception has been handled (by the exception handler), the user
task is resumed.
The handler program (or Interrupt Service Routine) must restore the user
state exactly as it was before the exception occurred:
1. Any user registers saved on the exception handlers stack must be
restored from it
2. The CPSR must be restored from the appropriate SPSR (done by
processor automatically).
3. PC must be changed back to the instruction address in the user
instruction stream
Steps 1 and 3 are done explicitly by exception handler code
Restoring registers from the stack (and saving them initially) would be the
same as in the case of subroutines
Restoring PC value is more complicated. The exact way to do it depends
on which exception you are returning from.
 Direct Memory Access vs Interrupt & Polling
DMA controller shares memory bus cycles with the processor - a
technique known as cycle stealing. The CPU notices only a
slightly slower memory system.
DMA controller manages transfers
 Direct Memory Access vs Interrupt & Polling
DMA controller shares memory bus cycles with the processor - a
technique known as cycle stealing. The CPU notices only a slightly
slower memory system.
DMA controller manages transfers
other
Memory devices
I/O device I/O device

Interrupt
Databus controller
Address bus

Direct Memory
CPU Access (DMA)
IRQ FIQ Controller
other devices
 Direct Memory Access (contd)

DMA is initiated by a processor. The following information

must be sent by the processor to the DMA module (AKA
DMA controller):
I/O device Read or Write is required?
Memory address of the I/O device involved in the transfer
The starting location in memory to read from or write to
The number of word to read or write
Once DMA is initiated, the processor can continue with other
work.
Processor can work concurrently with transfer between I/O
device and memory.
Data transfer without interrupt overhead
 Techniques for Inputting a Block of Data: DMA

DMA

Polling Interrupt