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This document provides a quick reference guide for VHDL including definitions of common terms like identifiers, signals, variables, data types, operators, and statements. It lists keywords, syntax, and examples for features like entities, architectures, processes, if/case statements, and port mapping.
This document provides a quick reference guide for VHDL including definitions of common terms like identifiers, signals, variables, data types, operators, and statements. It lists keywords, syntax, and examples for features like entities, architectures, processes, if/case statements, and port mapping.
This document provides a quick reference guide for VHDL including definitions of common terms like identifiers, signals, variables, data types, operators, and statements. It lists keywords, syntax, and examples for features like entities, architectures, processes, if/case statements, and port mapping.
Category Definition Example Identifer Names Can contain any letter, digit, or q0 underscore _ Prime_number Must start with alphabetic letter lteflg Can not end with underscore or be a keyword Case insensitive Signal Values 0 = logic value 0 1 = logic value 1 Z = high impedance X = unknown value Numbers and <base>#xxx# 35 (default decimal) Bit Strings B = binary 16#C# = 1100 X = hexadecimal X3C = B00111100 O = octal O234 = B010011100 Generic Associates an identifer name with a generic ( N:integer := 8); statement value that can be overridden with the generic map statement generic map Assigns a value to a generic parameter generic map (N => 16) Signals and signal (used to connect one logic signal d : std_logic_vector(0 to 3); signal led: std_logic; Variables Types element to another) variable q: std_logic_vector(7 variable (variables assigned values in downto 0); process) variable k: integer; integer (useful for loop control variables) Program library IEEE; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all; structure entity <identifier> is entity Dff is port( port( <port interface list ); clk : in STD_LOGIC; end <identifier>; clr : in STD_LOGIC; D : in STD_LOGIC; architecture <identifier> of q : out STD_LOGIC ); <entity_name> is end Dff; begin process(clk, clr) architecture Dff of Dff is begin begin {{concurrent_statement}} process(clk, clr) end<identifier>; begin if(clr = '1') then q <= '0'; elsif(rising_edge(clk))then q <= D; end if; end process; end Dff; Logic operators not z <= not y; and c <= a and b; or z <= x or y; nand w <= u nand v; nor r <= s nor t; xor z <= x xor y; xnor d <= a xnor b; 190 Appendix E
VHDL Quick Reference Guide (cont.)
Arithmetic operators + (addition) count <= count + 1; - (subtraction) q <= q 1; * (multiplication) / (division) (not synthesizable rem (remainder) Relational operators =, /=, >, <, >=, <= if a <= b then if clr = 1 then Shift operators shl (arg,count) c = shl(a,3); shr (arg,count) c = shr(a,4); process [<id>] process(<sensitivity list>) process(a) variable j: integer; {{process declaration}} begin begin j := conv_integer(a); {{sequential statement}} for i in 0 to 7 loop end process [<id>] if(i = j) then y(i) <= '1'; else y(i) <= '0'; end if; end loop; end process;
if statement if(expression1) then if(clr = '1') then
q <= '0'; {{statement;}} elsif(clk'event and clk = '1') then {{elsif (expression2) then q <= D; {{statement;}} }} end if; [[else {{statement;}} ]] end if; case statement case expression is case s is when "00" => z <= c(0); (( when choices => {sequential when "01" => z <= c(1); statement;}} )) when "10" => z <= c(2); {{ }} when "11" => z <= c(3); when others => {sequential when others => z <= c(0); end case; statement;}} end case; for loop for identifier in range loop zv := x(1); for i in 2 to 4 loop {{sequential statement} zv := zv and x(i); end loop; end loop; z <= zv; Assignment operator := (variable) z := z + x(i); <= (signal) count <= count + 1; Port map instance_name component_name port M1 : mux21a port map( a => c(0), b => c(1), map s => s(0), y => v); (port_association_list);