2016 2nd International Conference on Control, Instrumentation, Energy & Communication (CIEC)
QPSK Modulation and Demodulation Implementation on
CEVA XC-321 DSP for IEEE 802.11b Wi-Fi Phone
Application
Somnath Mondal, Santu Sardar and K. Ananda babu
Scientist, ANURAG, DRDO, Hyderabad, India
{somnath, santusardar, kababu}@anurag.drdo.in
AbstractThis work aims to design and implement
Quadrature Phase Shift Keying (QPSK) baseband modulation-
demodulation (MODEM) system on the CEVA-XC321 xed point
digital signal processor (DSP) and to compare its performance
with industry standard DSP processors and FPGA based
implementations. The modem function was developed in Vec-C
language by utilizing two Vector Computation Units (VCU) of
CEVA and veried on CEVA-XC321 based emulation platform.
The implementation of the modem functions includes sampling,
NRZ encoding, QPSK modulation, data packet formation using
payload and packet header, receiver matched ltering, QPSK
demodulation and decision device. We have considered additive
white Gaussian Noise (AWGN) channel to analyze the effect of
the channel on the transmitted data packet. The implementation
results and the theoretical results are consistent and ascertained
the correctness of this design. The modem parameters are
selected in accordance with IEEE 802.11b Wi-Fi standard. We
have tested the QPSK modem implementation in conformance
to 802.11b Wi-Fi performance metrics and established its
applicability in Wi-Fi phone system. The results showed that
the proposed DSP based QPSK implementation can greatly
improve the performance efciency with less development time
and cost for high data rate wireless local area network (WLAN)
applications.
Keywords - AWGN, CEVA, DSP, FPGA, modem, QPSK, VCU,
Vec-C, Wi-Fi.
I. I NTRODUCTION
During early deep space program, phase shift keying (PSK)
was developed and still being widely used in military and com-
mercial applications [1] because it offers lowest probability of
error. QPSK and Binary PSK (BPSK) are two variants which
offer low power and low BER data transmission rate, primary
requirements of wireless and satellite communications. At
same Bit Error Rate (BER) and xed bandwidth, QPSK can
transmit twice the data rate compared to BPSK. Therefore,
it is more spectrally efcient. In addition, QPSK requires
less transmitter power than Quadrature Amplitude Modulation
(QAM) to achieve same BER [2] and therefore it is more
power efcient scheme as well. With applications of WLANs
in various elds, there is an increasing demand for reliable,
higher data rate WLAN at low cost ( [3][5]). The IEEE
802.11 standards committee published 802.11b standard in
2.4 GHz (2.4 to 2.4835 GHz) ISM band [4], which provides
WLANs Medium Access Control (MAC) and Physical Layer
(PHY) specications.
978-1-5090-0035-7/16/$31.002016IEEE 476
Application Specic Integrated Circuit (ASIC) chips are
used in WLANs to meet requests of reliability, low power
consumption and low cost. In literature [6], a chip is realized
in 0.25 m, 40 GHz BiCMOS technology for the WLANs
standards 802.11a/b/g. A ip chip single die WiFi FEM is
developed using (HBT+EID-PHEMT) technology for smart
phone application in [7]. In [8], an ASP (application specic
processor) with 512-bit SIMD (Single Instruction Multiple
Data) and 192-bit VLIW (Very Long Instruction Word) archi-
tecture optimized for wireless baseband processing was imple-
mented in 130nm CMOS technology. This baseband processor
provides 100 GOPS computing ability at 117.6MHz. But these
chips dont have sufcient programming features and their
functionality cant easily be changed or improved once the
product is realized. Also they incur a huge development time-
cycle. FPGAs may be an alternative ( [9][11]) but they are not
used in performance and power critical mobile applications.
They can only be used for testing in pre-assessment phase
[12].
In this paper, we present an optimized DSP based im-
plementation of QPSK baseband MODEM based on IEEE
802.11b specications [13] and its implementation on CEVA-
DSP processor [14] with the aim to achieve optimum data-
rate as required by Wi-Fi phone application. CEVA-XC321
is a xed point DSP processor core which is being used
to develop a System on Chip (SoC) [14] by ANURAG. In
this SoC, CEVA core will be used for DSP intensive digital
baseband operations. Compared to work done on FPGAs in
[9] or DSP chips in ( [6][8], [15]), proposed design in DSP
core has advantages of ease of programmability, portability
and short development life cycle, which are inuential to
the performance and capabilities of MODEM. Power aware
features in the design and exibility to operate the chip at
higher operating frequency has made the SoC suitable for Wi-
Fi hand-held applications.
Rest of the paper is organized as follows. Section II gives
the functional description of CEVA-XC321 DSP. The details
of QPSK baseband MODEM and its implementation method-
ology on CEVA-DSP are presented in section III. Results are
provided in section IV and concluding remarks are given in
section V.
 2016 2nd International Conference on Control, Instrumentation, Energy & Communication (CIEC)

equation (1), where E= Bit Energy, T= bit time and S(t) stands
for symbol and is the carrier angular frequency.

2 2E
S(t) = cos(t + (t)) (1)
T
Here (t) is the phase as a function of information content,
and can have values of 45o , 135o , 225o , and 315o . And the
value of (t) is:

(t) = atan[sin(t + Im )/cos(t + Re )] (2)

where Re is the initial phase of the real channel and Im is
initial phase of the imaginary channel.
The QPSK baseband system requirements are evolved in
Fig. 1: CEVA XC321 Architecture Block Diagram accordance with IEEE 802.11b Wi-Fi standard (table I) and
as per Wi-Fi phone modem functions [13]. The design was
carried out for a carrier frequency of 11 MHz to achieve 2
II. F UNCTIONAL D ESCRIPTION OF CEVA DSP Mbps target data rate. The block diagram of QPSK modulation
CEVA-XC DSP is a fully programmable solution, which and demodulation system is shown in gure 3. Input binary
supports multiple air interfaces in software. It is a mix of data is generated as a pseudo-random (PN) sequence. In
VLIW and SIMD [17] architectures. The functional block dia- modulator, the baseband data is converted into even and odd
gram of the DSP is shown in gure 1. CEVA-XC321 combines unipolar data streams which are changed into bipolar by using
a General Computation Unit (GCU) with two Vector Compu- non return to zero (NRZ) encoding technique. This NRZ
tation Units (VCUs). Each GCU consists of: one 16x16-bit encoded data is combined with the carrier generated from
signed and unsigned multiplier, one 40-bit arithmetic unit, one (Digital Data Synthesizer) DDS and resulting in-phase (I) and
40-bit logical unit, one 40-bit bit-manipulation unit, including quadrature-phase (Q) data are added to generate QPSK signal.
a full barrel shifter and an exponent unit, one 40-bit data A BPSK modulated known symbol sequence of 24 Bytes, as
pack and unpack unit and eight 40-bit accumulators. Vector header, was appended in the beginning of the waveform for
Arithmetic (VA) unit, Vector Bit-manipulation (VB) unit, phase recovery and detection of start of data at the receiver.
Vector Move and Pack data (VM) unit, Vector register le
and optional vector maximum likelihood detector (VD) unit TABLE I. Specications of QPSK Modem
Sl. Parameter Value
are provided in each VCU. 1 Input Character (ASCII) used 32 - 128
CEVA provides speed-ups up to 1025x over pure-software 2 Input Length (Digital) used 256 - 1024 Bits
implementations. It can support WiFi, WiMAX, LTE and W- 3 Frequency Band 2.4 GHz
CDMA [19]. Tensilica ConnX Baseband Engine [20] and 4 MODEM Technique QPSK
5 Number of bit per symbol 2
NXP CoolFlux [21] are also licensable fully synthesizable 6 Targeted Bit Rate 2 Mbps
DSP cores for baseband processing. In comparison, Ceva uses 7 Channel Model AWGN
single-core to reduce design complexity. A single Ceva-XC 8 Channel Bandwidth 2 MHz
core can support next-generation 4G/LTE phones up to LTE 9 Samples/bit 8-12
10 Filter Type Low pass (LPF)
CAT5 (300Mb/s) [22]. 11 Filter taps 129
12 Filter cut-off frequency 4KHz (Speech Signal)
III. P ROPOSED QPSK BASED C OMMUNICATION S YSTEM 13 Matched Filter length 1200
14 Header Length 24 Bytes
QPSK uses equi-spaced four points around a circle on the 15 Payload Length 64 - 1518 bytes
constellation diagram and can therefore encode two bits per 16 Output Length (digital) 32 - 128
symbol as shown in gure 2. The bit-error probability of the 17 Output Character (ASCII) 256 - 1024 Bits
QPSK signal is:
 The modulated waveform is then passed through a channel
1 Eb
Pb = erf c[ 2 ] model ( [23], [24]) which injects AWGN noise with different
2 N0
signal to niose ratio (SNR) values and then fed to the demod-
In this equation, Pb stands for probability of bit-error, ulator to demodulate the modulated data.
erf c(.) is complementary error function, Eb is energy per bit The received signal at the demodulator is initially passed
and N0 is noise power spectral density (PSD). on to the matched lter of length 1200 to detect the start
QPSK can be seen as viewed as two independently mod- of the frame and extraction of the payload. The extracted
ulated quadrature carriers each being BPSK modulated [15]. symbols are sent sequentially to demodulation block. Here,
The four waveforms of different phases are obtained using the symbol sequence is rst given to I and Q channel of

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the demodulator to multiply with locally generated carriers.
The mixed outputs are then passed through a low pass lter
of 129 taps to reject high frequency components. We have
selected lter cut-off frequency of 4KHz to utilize it for
speech communication also. We used nite impulse response
(FIR) lter due to its linear phase characteristics within pass-
band. The recovered waveform is then passed to the decision
device. In the transmitter all the input values were sampled
twelve times. Therefore, at the receiver, decision is performed
for all the sampled values and then aggregated to form the
nal output. This procedure reduces the bit-error rate (BER)
compared to the case of without sampling. I and Q channel bits
are concatenated after the decision block to get the recovered
bit stream.
SNR values, the constellation diagram at the Receiver along
with the Constellation diagram at the transmitter are shown
in gure 5. It can be observed from the constellation diagram
that, as the SNR value decreases, more and more phase error
gets accumulated at the receiver. We plotted the eye diagram
also for the above situations in gure 6 since eye diagrams
make it easy to nd the worst-case signaling conditions at the
receiving end. To maximize noise margins we must select the
best sample point at the widest point in the eye and pick the
best digitization threshold as half-way across width. The eye is
more open in case higher SNR values which means that lower
BER will be obtained for higher SNR. ISI effect is reduced
here because after every 12 samples the next symbol starts and
therefore one symbol is not affecting the next one [9]. Figure
7 shows the plot of BER versus Eb /N0 for the QPSK system.
The red curve is the theoretical BER and the blue curve is
the obtained BER for our implementation. The theoretical and
practical values of BER are close to each other which veries
the functionality of the QPSK MODEM implementation.

Fig. 2: Constellation Diagram of a QPSK Modulated Carrier

The modulation and demodulation functions are imple-

mented in xed point and achieved 9.27x performance im-
provement compared to corresponding oating point imple-
mentation on the DSP because CEVA is a xed point DSP.
We have used Vec-C language to implement the FIR lter.
Complex lter input is considered where the real part is
considered as the I value and the imaginary part is the Q
value. Accordingly the real lter output is the ltered I output
and imaginary output is the ltered Q output because the
lter coefcients are all real values. Vec-C implementation Fig. 4: (a) Transmitted Signal at the Transmitter, (b)
achieved 19786.7x less clock cycles compared to correspond- Received Signal at the Receiver for SNR = 35 dB, (c)
ing C implementation. This is due to the fact that, Vec- Received Signal at the Receiver for SNR = 20 dB, (d)
C implementation utilizes the 2 VCUs, optimized for DSP Received Signal at the Receiver for SNR = 1 dB
operations whereas C implementation uses only the GCU.
We have taken measures to optimize the code in terms of
cycle count and code size. For CEVA compiler, level 04 cycle
count optimization and level 03 code size optimization are
used. To overcome stack overhead, global variables were used.
Moreover, we minimized loop content by removing any non-
dependent contents from loops. Memory accesses that dont
change throughout the loop are copied to local variables and
copied back if necessary. Known limits to loops are used by (a) (b) (c)
copying loop limit to local variable. Simplied conditions are
used inside the loops. To optimize the code memory and data
memory, similar loops are merged together and minimized the
usage of if else statement. Large functions are split into
small and simple ones.
(d)
IV. R ESULTS Fig. 5: Constellation Diagram: (a) At the Transmitter, (b)
The transmitted waveform at the transmitter is shown in Received Signal for SNR = 35 dB, (c) Received Signal for
gure 4(a). The received signal at the receiver for SNR value SNR = 20 dB, (d) Received Signal for SNR = 1 dB
of 35 dB after AWGN noise insertion by the channel, is shown
in gure 4(b). The received signal for SNR of 20dB and 1 The baseband SoC will be used for running Wi-Fi stack
dB are shown in gure 4(c)and 4(d) respectively. For these based on IEEE 802.11b standards where PHY layer will

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 2016 2nd International Conference on Control, Instrumentation, Energy & Communication (CIEC)

Fig. 3: Block Diagram of QPSK based MODEM

in the form of cycle count, is calculated. The CEVA-XC

emulation platform is based on Altera Stratix-4 Device (Al-
tera EP4SE530F43C4) with 256KB Internal Program, 512KB
Internal Data in 4 Blocks and it uses 80% of the device
(a) (b)
logic 8. The board provides a standalone minimal system for
software development. It includes 6 Hi-Speed connectors to
interface with other CEVA emulation platforms or base boards.
The CEVA-XC operates using 50 MHz DSP clock with 256
KB L1 program memory and 512 KB L1 data memory. The
emulation platform contains 8 MB external FLASH memory
(c) (d) CEVA- XC JTAG, Altera JTAG conguration port, LEDs and
Fig. 6: Eye Diagram for the I and Q components of the Dip-switches. The emulation platform is connected to JBOX2
QPSK signal: (a) At the Transmitter, (b) Received Signal for which is useful for real-time emulation support and supports
SNR = 35 dB, (c) Received Signal for SNR = 20 dB, (d) ethernet and USB connection to host PC. It will be used on
Received Signal for SNR = 1 dB nal SoC with JTAG interface to the DSP.
The input length to the QPSK modulator is taken as 3072
bits and accordingly the output length after QPSK modulation
becomes 1536 symbols. The results are summarized in tableII.
As the DSP core estimated operating frequency is 400 MHz in
the SoC, module execution time needs 110.32 s. Therefore,
the achieved data rate is 13.9231 Mbps. The QPSK demodu-
lation requires 221531 clock cycles i.e. completes in 553.8275
s achieving a data rate of 2.9901 Mbps. The selected param-
eter values and the measurements indicate that the CEVA-
XC321 Core could handle the baseband QPSK MODEM
functionality and deliver acceptable real-time performance for
Fig. 7: BER versus Eb/N0 IEEE 802.11b Wi-Fi applications.

be implemented in CEVA core. According to IEEE 802.11b

specications QPSK can be used for modulation-demodulation
to achieve 2 Mbps data rate [12]. Also the payload size in a
transmission packet varies between 32 bytes to 2048 bytes, 30
to 32 bytes being most common ( [25], [26]). In our case, we
have considered a payload size of 384 bytes.
The CEVA core is operating at 400 MHz in the SoC RTL
simulation model and targeted the chip to work at the same Fig. 8: CEVA emulation platform Board
frequency. We have ported and veried the proposed QPSK
MODEM on CEVA-XC emulation Platform using the CEVA Compared to licensable DSP cores, CEVA is most suitable
integrated development platform (IDE). CEVA-proler tool in for Wi-Fi applications in terms of computation efciency,
the CEVA-IDE is used to prole the design and performance, speed and power ( [14], [17], [20], [22]). Compared to TI DSP

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 2016 2nd International Conference on Control, Instrumentation, Energy & Communication (CIEC)
TABLE II. QPSK Modem Implementation Results
No. of Clock Cy- Processing Data Rate
Sl. Module
cles Required time (s) Achieved (Mbps)
1 Modulator 44128 110.32 13.9231
2 Demodulator 221531 553.8275 2.9901
core, in [27], Angelis et. al. implemented QPSK transmitter
on TMS320C6711DSP, which can operate at a maximum
frequency of 200 MHz and achieved a maximum data-rate
of 1840 kbps.
QPSK modulator is implemented on FPGA devices( [28],
[29]). In [28], 512 Kbps data-rate is achieved using Actel
ProASIC 3000 kit whereas in [29] attained data-rate is only
500 Kbps on Xilinx FPGA. In contrast, we have achieved more
than 2 Mbps for QPSK MODEM.
CEVA Integrated Development Environment (IDE) supports
high level language for application development [17]. This
feature facilitated us to develop parameterized design in ANSI-
C language, which shortened the development life-cycle. The
parameterization makes the code reusable for other applica-
tions as well. This CEVA emulation platform can be used for
developing multiple hi-end applications [19]. This reduces the
development cost since we dont need to incur high equipment
expenditure to migrate from one generation to next [16].
V. C ONCLUSION
We have proposed a QPSK based transmitter and receiver
and implemented it on CEVA-XC321 DSP. CEVA is selected
due to its superior performance among other licensable soft
DSP cores as discussed in this paper. We have utilized Vec-
C programming language to use the VCU of CEVA for
better performance as demonstrated. AWGN channel model is
developed in Matlab for exhaustive verication of the system
for a range of SNR values. We analyzed the constellation plot,
eye diagram as part of performance evaluation of the system.
The MODEM was implemented in the CEVA-XC321 based
emulation platform connected to JBOX2, useful to interface to
the DSP in the nal SoC. The proposed system improves the
developing efciency, shorten developing period and reduce
costs. We established the applicability of this modem for IEEE
802.11b Wi-Fi phone application. The performance of this
system is compared with other COTS based implementations
as published in literature.
In the future work, this proposed system will be ported on
to the baseband SoC evaluation board. To further improve the
performance, we can model and use assembly optimized Vec-
C functions. Error correcting capability will be included in
the modem system to improve the BER performance. Spread
Spectrum (SS) can be used in this system to increase the
security of the system.
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