2226
12, DECEMBER 2004
A Direct-Conversion CMOS Transceiver for the
802.11a/b/g WLAN Standard Utilizing a Cartesian
Feedback Transmitter
Laurent Perraud, Marc Recouly, Christophe Pinatel, Nicolas Sornin, Jean-Louis Bonnot, Frederic Benoist,
Myriam Massei, and Olivier Gibrat
AbstractA fully integrated dual-band transceiver is im-
plemented in 0.18- m CMOS and is compliant with the IEEE
802.11a/b/g standards. The direct-conversion transceiver occupies
12 mm2 in a QFN-40 package. A fractional- synthesizer operates
at twice the channel frequency, covering continuously bands from
4.9 to 5.9 GHz, as well as the 2.4-GHz band. The 5- and 2.4-GHz
receivers achieve a sensitivity level below 73 dBm in the 54-Mb/s
mode and below 93 dBm in the 6-Mb/s mode, while consuming 230
mW. A fast RSSI-channel power-detection system allows to power-
down signal processing in the listen mode. The 5- and 2.4-GHz
transmitters implement a wideband Cartesian feedback loop for
enhanced EVM performances and improved spectrum masks com-
pliance. The transmitters deliver 2-dBm average power with an
EVM of 3% in the 54-Mb/s mode while consuming 300 mW.
Index TermsCartesian feedback, class-AB amplifiers, di-
rect conversion, dual-band, fractional- synthesizer, IEEE
802.11a/b/g, phase rotation, received signal strength indicator
(RSSI), WLAN.
I. INTRODUCTION
I NNOVATION in WLAN transceiver design has been driven
during many years by the new signal processing challenges
of the ever-evolving IEEE 802.11 standard. More recently, with
the success of WiFi applications, the focus of WLAN system
design became the optimization of cost, performances, and new
types of WiFi applications, i.e., WLAN for PDA or cell phones.
These three criteria together created a new emphasis on integra-
tion, production yield, battery-compatible power consumption,
as well as sustained performances, when other communications
systems (GSM or WCDMA) are present on the platform.
The transceiver presented in this paper offers the integration
of the 802.11a/b/g standards, with extended frequency coverage,
from 4.9 to 5.9 GHz, to comply with any worldwide WLAN
frequency allocations. It uses a single 1.9-V power supply.
The transceiver features a fractional- frequency synthesizer
operating at twice the signal frequency, i.e., up to 12 GHz while
achieving below 1 of typical rms phase noise. The fractional op-
eration enables the support for any platform reference frequency
between 26 and 52 MHz as well as built-in fine frequency tuning.
The dual-band direct-conversion OFDM/CCK receiver im-
plemented in the chip exhibits a total noise factor (NF) of 4.5 dB.
A mixed-signal dc offset correction scheme, together with a
Manuscript received April 18, 2004; revised July 12, 2004.
The authors are with NewLogic Technologies, Sophia Antipolis, France
(e-mail: laurent.perraud@newlogic.fr).
Digital Object Identifier 10.1109/JSSC.2004.836332
0018-9200/04$20.00 2004 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO.
highly linear passive mixer, is used to solve critical dc offset
removal for OFDM signals when large frequency offsets are
present [1]. An analog received signal strength indicator (RSSI),
used during frequent listen-mode operation, allows power-down
analog-to-digital converters (ADCs) as well as all-signal pro-
cessing in the baseband companion chip.
The dual-band transmitters implement a Cartesian feedback,
enabling the use of less linear class-AB RF drivers while
transmitting OFDM 64-quadrature-amplitude modulation
(QAM) signals. The main challenge of this architecture, when
it is applied to wideband signals, is the loop stability. It has
been overcome using a new phase rotation and a per-packet
phase alignment scheme, which always provide the optimal
stability conditions. This transmitter architecture permitted a
new optimization of current drain and a reduced sensitivity to
process and temperature variation. These transmitters also fea-
ture a single-ended output 50- matched with direct interface
to a power amplifier (PA). They do not require any factory
calibrations.
Complementary system analyses have been conducted to
analyze power supply rejection requirements and RF front-end
filtering for co-location within cellular platforms (GSM or
WCDMA). The fully differential receive paths, the unique
power supply rejection of the transmitter due to the Cartesian
feedback (output level controlled by higher power supply rejec-
tion ratio (PSRR) baseband blocks), and a careful design of the
synthesizer allows this chip to withstand larger power supply
drops during the asynchronous operation of GSM transceivers
and PAs.
As the overall system analysis is not the purpose of this paper,
the next section describes how the system requirements outline
above where translated into design challenges for the synthe-
sizer, then for the receiver and finally for the transmitter. A block
diagram of the first version of the transceiver is given in Fig. 1.
The second version of this transceiver allowed us to consoli-
date some of the performance measurements while offerin g the
integration of the IQ Codec, the front-end digital filtering, the
AGC/CCA algorithm, as well as a digital interface to the base-
band companion chip.
II. BLOCK-LEVEL ARCHITECTURE
A. 10-GHz Fractional- Synthesizer
Due to the direct-conversion scheme of the transceiver, the
synthesizer has to generate the in-phase and quadrature local
PERRAUD et al.: A DIRECT-CONVERSION CMOS TRANSCEIVER FOR THE 802.11a/b/g WLAN STANDARD
Fig. 1. Transceiver block diagram.
oscillator (LO) signals at 2.4 and 5 GHz at the same frequency
as the TX or RX signal carrier. To avoid pulling issues be-
tween the power amplifier and the synthesizer, and to achieve
native low-quadrature-mismatch LO signals, the voltage-con-
trolled oscillator (VCO) operates at two or four times the LO
frequency; its effective operation range must be from 9600 to
11 800 MHz. Fig. 2 shows the phase-locked loop (PLL) block
diagram.
The fractional- synthesizer architecture allows higher PLL
bandwidth (240 kHz), thus reducing lock time and in-band cou-
pling effects. The PLL reference frequency is 40 MHz in our
application. However, any crystal frequency can be chosen be-
tween 2652 MHz. To reduce pulling effects between the pre-
power amplifier (PPA), the mixers, and the PLL, the synthesizer
is placed in the diagonally opposed corner to the PPA and mixers
(Fig. 22). Two differential microstrip lines at 5 and 10 GHz are
used to drive, in a current mode, the quadrature dividers-by-two.
No voltage reconstruction of 12-GHz signals was required in
2227
parts of the chip where the substrate could be modulated by the
transmitter signals.
Modulation and demodulation of OFDM-64-QAM signal re-
quired a residual index lower than 1.5 rms (jitter of 400 fs at
11 GHz), integrated into the single sideband width of the signal
(10 MHz). The RX blocker rejection also requires a phase noise
lower than 137 dBc/Hz at 50 MHz from the carrier. These per-
formances are achieved by an optimal choice of the loop band-
width (240 kHz) that should high enough to decrease the VCO
contribution above the PLL bandwidth and that should be small
enough to filter the fourth-order sigma-delta contribution above
2 MHz. During the design, special attention was given to the
charge pump current noise, since simulations show that its con-
tribution is of the same order of magnitude as the VCO contri-
bution. Simulations of a proprietary noise model show that the
contribution of the loop-filter resistors is negligible, and the di-
viders are not dominant due to the low division ratio resulting
from the high reference frequency (40 MHz).
2228
Fig. 2. Synthesizer block diagram.
The first version of the sigma-delta modulator used for
fractional- operation was a MASH-4. It is composed of four
cascaded first-order sigma-delta modulators. The quantization
noise of the stage ( ) is applied at the input of the stage
. In addition a coefficient is introduced
to reduce the maximum output codes to 16. Dithering was
added at the first-stage accumulator to force the least significant
bit to zero.
Therefore, the sigma-delta transfer function expressed below
shows a gain of for the dc input and a fourth-order
high-pass transfer function for the noise of the fourth stage:
The VCO frequency is then defined as:
, in which is the 40-MHz ref-
erence frequency, and are the integer and fractional
parts of the division ratio. An input is also provided to
permit a fine-tuning of the synthesizer frequency. The PLL res-
olution is then 2.44 kHz, which is low enough to compensate
for the 10-ppm crystal tolerance. If it the 802.11a/g standards
do not permit to decorrelation of the frequency offset and the
timing offset while transmitting, a proprietary algorithm, imple-
mented in a future version of our companion baseband chip, will
maximize the OFDM demodulation performance of a packet re-
ceived from an access point, when the application is used in
IBSS mode.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
The MASH-2-2 improved architecture was designed for the
second version of the transceiver to improve the spectral purity
of the first design. It is composed of two second-order sigma-
delta modulators using three-state quantizers. Dithering is added
at the input of the first quantizer through a feedback of the
output signal. The output spectrum of the MASH-2-2 is shown
in Fig. 3. Its reduced rms output code spread is improving the
noise level of the sigma-delta modulator itself as well as de-
creasing the contribution of the charge pump during its dead-
zone mode of operation.
1) 12-GHz VCO: The 12-GHz VCO was designed to keep
its tuning range maximal in order to cover the 960011 800 MHz
band. The VCO schematic is shown in Fig. 4. It is composed of
a cross-coupled differential pair M1 and M2 providing a neg-
ative resistance in parallel with an LC resonator digitally pro-
grammable through a bank of binary weighted varactors. Two
additional varactors are used for analog tuning.
The measured of the resonator is 18 at 12 GHz [2]. The
resonator inductance L1 is kept low (240 pH) in order to get
the LSB of the capacitor sufficiently high (10 fF) compared to
the parasitic capacitors. The capacitor structure uses differential
NMOS transistor into an N-well. The N-well bias is digitally
switched between 0 V and a high voltage of 2.9 V, which is
provided by a switched capacitor circuit; this allows switching
the varactors between full accumulation mode and full depletion
mode. The bias circuit uses a PMOS current source M3 and a
feedback loop composed of the transistors Q1 and Q2 (lateral
NPN) and a sense resistor R1. The geometry ratio between Q1
and Q2 is 8, so the nominal bias current of the VCO is:
.
PERRAUD et al.: A DIRECT-CONVERSION CMOS TRANSCEIVER FOR THE 802.11a/b/g WLAN STANDARD 2229

Fig. 3. MASH-2-2 maximum-hold output spectrum across all codes.

A high-power mode allows increasing the bias current to

16 mA by decreasing R1. This feedback structure offers the
advantage of reducing the effect of the flicker noise of M3
below 1 MHz due to the open-loop gain. This biasing scheme
together with the control scheme of the VCO banks gave a
typical pushing figure of 1 MHz/V from 1.2 to 2.0 V of power
supply.
Fig. 4. Schematic of the 10-GHz VCO.
The curve in Fig. 5 shows the measured VCO half-frequency
versus the digital code. It shows that the nominal frequency on
our first transceiver version is slightly lower than the target, and
the 26% tuning range is large enough to cover the application
range. The next version of the design includes a second VCO to
cover the highest frequency range and the process variations.
The analog tuning is applied to two additional varactors of 10
and 20 fF through an analog switch to ensure a programmable
tuning gain of about 40, 80, and 120 MHz/V. The plots of
Fig. 6(a) and (b) shows the VCO half-frequency and VCO
gain versus the loop filter tuning voltage. The center frequency
calibration is performed using a hardware timer and counter
and a software algorithm running in the baseband companion
chip. The curve in Fig. 7 shows the resulting loop filter voltage
after the calibration is completed.
2) Dividers, Phase-Frequency Discriminator, Charge Pump, Fig. 5. VCO half-frequency versus digital code.
and Loop Filter: The phase-frequency discriminator (PFD) is
based on an RS-flip-flop circuit, which delivers Up and Down Down commands. In addition, a rail-to-rail opamp operates
pulses according to the phase difference between the 40-MHz as a follower on the loop filter voltage and ensures that the
reference and the loop divider output. The minimum pulse drainsource voltage of the current sources remains constant
width is set through a programmable delay line on the flip-flop when switching the current sources. The noise floor of the
reset inputs and is programmable between 300 ps and 2.5 ns. A current source is simulated at 20 pA/ Hz when the current is
longer delay increases the charge-pump linearity and reduces nominally at 1 mA.
the folding of the high-frequency sigma-delta noise in the PLL. The third-order loop filter is fully integrated with NMOS in
A shorter delay reduces the spur level of the reference oscillator. N-well capacitors. The total capacitor value is 1.1 nF, resulting
Therefore, an optimum value has been experimentally found. in a loop filter area of 0.27 mm . Fig. 8(b) shows the mea-
The charge pump and loop filter schematic is shown in sured lock time at less than 20 s. The on-chip crystal oscillator
Fig. 8(a). The charge pump is made of nine identical current can work with external crystal between 2652 MHz, and our
sources, providing a programmable current between 400 A chip was tested using a 40-MHz crystal with 20-ppm tolerance.
and 1.8 mA for flexibility in the PLL bandwidth. The current The phase noise measurement of our 40-MHz reference shows
sources M1-M2-M7-M8 are cascoded and use large transistors a noise floor of 150 dBc/Hz and a corner frequency at 1 kHz.
for reasons of accuracy and to work at low supply voltages. Two The 2.3-mm-long differential microstrip lines are driven
dummy switches drive the differential switches M3-M4-M5-M6 by NMOS transconductors and propagate the 5- and 10-GHz
symmetrically to reduce the spikes when switching the Up and signals to the quadrature dividers-by-2. They also propagate
2230
Fig. 6. VCO half-frequency and tuning gain versus tuning voltage.
Fig. 7. Loop filter voltage after VCO calibration.
the dc current of the CML dividers where the bottom current
sources was removed to reduce the power consumption and
to increase voltage headroom. The line transconductors are
differentially back-gate biased to create a dissymmetry on the
duty cycle and perform fine tuning of the quadrature. The
dc bias is applied through a 5-b digital-to-analog converter
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
(DAC), providing a resolution of 0.3 on the quadrature. Fig. 9
shows a measurement of the effect of the DAC code on the
quadrature of received signals. This would allow building
an independent phase-mismatch calibration algorithm within
the transceiver. The divide-by-2 noise floor was measured at
150 dBc/Hz above 1 MHz. The 7-b divide-by- operates
between 24002950 MHz with single-ended CMOS levels.
3) PLL Measurements: Fig. 10 shows the PLL spectrum,
measured at the PA output after mixing with a constant
signal. The spurs level is below 64 dB during fractional op-
eration. The synthesizer phase noise plotted in Fig. 11 shows an
in-band phase noise of 101.5 dBc/Hz when the synthesizer is
locked in the lower frequency band. Spurs in the plot are unfor-
tunately due the PN9000 phase-noise equipment (indicated as
such by the equipment). When locked in the higher frequency
band, 510 dB of degradation is observed, but the phase noise
is nonetheless within the 1.2 specification for the typical case.
The jitter measured at the 5-GHz PA output and integrated over
10 MHz is below 400 fs.
B. Receiver
The dual-band direct-conversion front-end architecture is
shown in Fig. 12.
1) Wideband LNA: In order to achieve a noise figure
of 4.5 dB for the whole receiver chain, both LNAs exhibit
a measured 1.5-dB NF at 20-dB gain. A fully differential
common-source cascoded architecture is used to achieve a
better reverse isolation. To maintain a constant gain and NF at
5 GHz over a 1-GHz range, the output load of the LNA is a
trimmable LC-tank with a minimum factor of 8 at 5 GHz.
A low-gain mode (0 dB) is implemented while maintaining
good linearity and optimum LNA input matching. The whole
LNA architecture with the 20-dB gain step is shown in Fig. 13.
For high-gain operation, the cascode transistor M3 is switched
on. For low-gain operation, nine tenths of the branch currents
are steered to V . This technique keeps constant the input
impedance of the LNA.
2) Mixer and Baseband Strip: The RF-to-baseband conver-
sion is implemented using a single multimode passive mixer
arrangement driven from fully differential RF amplifiers, fea-
turing a power-down mode with high RF output impedance.
Such architecture provides a measured 61-dB reverse isolation
from the mixer switches to the antenna and sufficient linearity
especially for 5-dBm RF input level. Since mixers are
shared between the 2.4- and 5-GHz paths, area is reduced and
LO signal routing is made easier. LO signal multiplexing has
been implemented on the LO-microstrip-line drivers (current
mode).
and down-mixer switches are driven in parallel for
reduced mismatches. High-speed current conveyors with
low-baseband input impedance are then used for better lin-
earity. The mixers feature a programmable gain ranging from
2 to 14 dB (current steering within the current conveyor block)
in 6-dB steps while presenting a fixed load impedance to the
post LNA.
After the mixers and its current conveyor, the received signals
first need to be filtered for interferer suppression and then to be
PERRAUD et al.: A DIRECT-CONVERSION CMOS TRANSCEIVER FOR THE 802.11a/b/g WLAN STANDARD
Fig. 8. (a) CP and LPF schematic. (b) PLL impulse response.
Fig. 9. Quadrature tuning law.
amplified. While featuring completely different signal charac-
teristics, a single filter is used for both CCK and OFDM sig-
2231
nals. Filter parameters are optimized for OFDM signals (more
stringent); CCK signals will then need extra interferer suppres-
sion. Multimode 8-b analog-to-digital converters (ADCs) (SNR
requirement for OFDM signals) are used for signal quantization
in the baseband chip. This provides sufficient dynamic range to
handle residual CCK interferers and allow their suppression in
the digital domain.
The multimode baseband receive path then features two
fifth-order 0.1-dB Chebyshev filters and high-speed 3-dB-step
programmable-gain amplifiers.
The filter is split into a third-order section and a second-
order section. The third-order low- section is driven directly
by the mixer current conveyor for better linearity. As interferers
are scaled down, a first AGC gain stage is inserted, then re-
laxing noise requirements on the high second-order section. A
second AGC gain stage is then necessary to meet the 27-dB gain
requirement. Filter parameters need to be only 5% accurate be-
cause their cut-off frequency is 12 MHz; this higher cut-off fre-
2232
Fig. 10. Synthesizer spectrum. (a) Spanning 25 MHz. (b) Spanning 400 MHz.
quency also insures that OFDM stringent requirements on
phase and gain mismatches are met.
Filter sections are then implemented using Sallen-and-Key
active RC configurations based on fully differential current
feedback amplifiers. Such amplifiers (Fig. 14) are perfectly
suited for high-speed, medium linearity performances (50 dB).
In order to improve gain/phase mismatch, any secondary poles
were moved above 100 MHz.
Since the RC time constant needs to be trimmed, metalin-
sulatormetal (MIM)-based capacitor banks were used. The
RC time constant is measured during an on-chip calibration at
start-up only. Filter cut-off frequency is almost insensitive to
temperature.
Gain stages are based on current feedback amplifiers also.
The second gain stage acts also as an output chip buffer. The
output common-mode voltage of the analog interface is
regulated to 0.7 V to be compatible with 0.18- m/0.13- m
baseband chips.
The whole baseband strip exhibits a measured input referred
noise of 23 nV/sqrt(Hz) at maximum gain and better than
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
Fig. 11. PLL phase noise (a) at 4600 MHz and (b) at 5800 MHz.
50-dB third-order harmonic distortion at maximum signal.
Total power consumption is 20 mA.
Due the zero-IF nature of the receiver, output dc offset needs
to be cancelled for accurate in-band power measurement and im-
proved ADC dynamic range. Since no dc block could be inserted
for maximum group delay reason (802.11a/g requirement), 8-b
current-steering DACs are used to remove the offset. The DACs
could be driven directly from the baseband chip through the se-
rial interface. For OFDM packet detection and AGC loop set-
tling during preamble processing, a fast offset correction loop
is absolutely needed. Two dc offset cancellation loops ( and
) are then built in the radio chip using the DACs, low-reso-
lution quantizers, and digital integrators. Maximum offset re-
moval time is 800 ns. This ensures that, if the gain needs to be
changed during the preamble time, the dc offset could be can-
celled a second time.
To reduce the overall system power consumption, the in-band
signal power can be monitored in the radio chip using an RSSI
block. This allows having the baseband chip powered down
(e.g., ADCs and digital filters) while listening to the
media for signal detection. The OFDM packet must be detected
(power) and correlated in less than 4 s. The whole input signal
dynamic is then divided into two ranges (high gain/low gain) to
allow a power measurement in two shots.
The RSSI detector (Fig. 15) features a 40-dB dynamic
range from 50 to 10 dB V . Due to the high gain and
accuracy requirements for weak input signals, high-precision
converters are used to drive two differential full-wave rec-
tifiers. Rectified currents are then reconstructed in a nonlinear
resistor. The nonlinear element operates as a resistor for low
signal magnitude and allows some kind of log compression
as the signal level increases. The main design challenges were
the process/temperature dependence of the compression circuit.
The rectified/compressed signal is then filtered to extract rms
value. A third-order Bessel filter was chosen for fast settling
PERRAUD et al.: A DIRECT-CONVERSION CMOS TRANSCEIVER FOR THE 802.11a/b/g WLAN STANDARD
Fig. 12. Simplified schematic of dual-band LNAs and RX downmixers.
Fig. 13. LNA complete schematic for 2.4 and 5 GHz.
Fig. 14. Simplified schematic for a current feedback amplifier.
time while preventing unwanted signal detection. A fully dif-
ferential active RC Rauch filter with a trimmed 500-kHz cut-off
frequency is implemented.
2233
Fig. 15. RSSI block diagram.
The analog RSSI output is then converted to 5 b using a flash
ADC clocked at 10 MHz. The whole RSSI section consumes
7 mA, including the analog buffer and the ADC.
A general state machine in the radio chip manages the AGC
coarse gain setting, the RSSI, and the dc offset loop. Once a
packet is detected, a wake-up signal is sent to the baseband chip
and dc offsets are held.
Fig. 16 shows the RSSI analog output while receiving a
83-dBm OFDM packet. Signal detection and correlation is
performed during short preamble processing. Fig. 17 shows
the SNR and EVM performances of the receivers while Table I
summarizes the overall performances of the two receivers.
The SNR performance differences between the two bands of
operation, illustrated in Fig. 17, are due to different on-board
front-end losses and are not due to unequal NF performance of
the receive chains.
C. Transmitter
The transmitter block diagram is shown in Fig. 18. The trans-
mitter is based on a direct-conversion architecture and is fully
integrated. From the baseband chip, and DAC output signals
are first converted to current using high-speed high-linearity
converters. A fourth-order Butterworth filter is used for
60-MHz replica attenuation. Two Sallen-and-Key active RC sec-
tions are implemented using current feedback amplifiers, poly
2234
Fig. 16. RSSI analog output, rf =2480 MHz, 64-QAM OFDM packet,
0
P 83 dBm.
Fig. 17. Overall performances of the receivers.
resistors, and trimmable capacitors. Then the output signal is
upconverted to the RF frequency and amplified by a PPA. A
feedback technique called Cartesian feedback loop is used to
linearize the RF output signal while using class-AB RF stages.
The last stage of the PPA features an integrated wideband trans-
former to provide differential to single-ended conversion. The
RF output is 50 matched and can be directly connected to an
external PA.
1) Cartesian Feedback Design: The Cartesian feedback
loop consists of using a negative feedback, with frequency
down-conversion, around the upmixingamplifying RF path
to reduce the linearity and AMPM constraints of this same
upmixing path.
The forward path (U) is composed of differentiators, base-
band amplifiers (gain G), filters (setting the dominant pole of
the loop), upmixers, and RF gain stages preceding the PPA. The
feedback path is created by the downmixers. For a more detailed
description of the Cartesian feedback loop, please refer to [6].
If the forward gain is large enough, the overall transmitter
gain becomes the inverse of the downmixer gain. Similarly, if
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
the baseband block distortion is sufficiently low, the linearity of
the transmit path is limited by the linearity of the downmixers.
The gain and linearity of the downmixers can easily be made
independent of the process, temperature, and frequency of op-
eration, allowing a robust transmitter design.
However, previous implementations of a Cartesian feedback
all suffer from a central design issue. The circuit section encom-
passing the upmixers, RF components, and downmixers intro-
duces an arbitrary phase rotation between its and input and
output [3]. This rotation is created by the combination of the
following effects:
phase shift between the LO signal driving the upmixers
and downmixers;
phase shift introduced by the RF transfer function of the
RF gain stages.
An a priori condition to insure the stability of the loop is to
compensate for this phase shift. This enables to decouple the
and loops. When the phase shift is perfectly corrected, we
have two identical feedback loops running in parallel without
cross coupling: one for the channel and one for the channel.
A common method to perform the phase-shift cancellation is to
introduce the opposite phase shift between the LO driving the
downmixers and the upmixers. However, this phase shift still
has to be continuously adjusted to track process, temperature,
and frequency of operation-induced drifts.
Even when perfectly decoupled, the overall loop delays
limit the maximum modulation bandwidth and/or gain to keep
the loop stable. For a 10-MHz modulation bandwidth, the delay
should practically be kept below 10 ns, including the baseband
blocks of the loop.
2) Stability, Automatic Phase Alignment, and LO Leakage
Calibration: A phase shift between the input and the output of
an RF amplifier is equivalent to a baseband signal rotation by
an angle introduced between the downmixers outputs
and the upmixers inputs (the signal can be considered a complex
vector ). The phase-shift compensation can theoret-
ically be performed anywhere in the loop (in baseband or RF).
We chose to perform this compensation in the baseband section
for the simplicity of the analog circuit implementing the rota-
tion function.
The circuit (Fig. 19) performs a transconductance operation
and an arbitrary phase rotation as follows:
with varying from 0 to . The quadrant is selected by the
bits b0 and b1. A 4-b DAC creates the and currents by
steps of 5.6 . This transconductor directly feeds the upmixer RF
switches. This circuit is not a very linear structure (linearity of a
differential pair). By placing it after a linear gain (baseband am-
plifier G), its nonlinearity contribution can be made negligible.
Due to this baseband implementation, the same LO buffers
drive both the upmixers and the downmixers LO, which ensures
a simpler LO generation.
PERRAUD et al.: A DIRECT-CONVERSION CMOS TRANSCEIVER FOR THE 802.11a/b/g WLAN STANDARD
TABLE I
RECEIVER PERFORMANCE MEASUREMENTS SUMMARY
Fig. 18. Transmitter block diagram.
TABLE II
TRANSMITTER MAIN PERFORMANCE MEASUREMENTS
Like any feedback loop, a dominant first-order pole has to
be set for stability reasons. This is done by introducing a low-
pass filter after the amplifier G. The other poles and zeros are
generated mainly by the RF resonant tanks and the upmixer
low-pass characteristic. LC tanks used as loads in the RF gain
stages (PPA) act as a second-order pole around the center fre-
quency and, once downconverted to baseband, act as a low-
pass second-order pole. In the application, the total loop gain
is maintained around 36 dB by an algorithm not described here
by adjusting the PPA bias current. The dominant pole is set at
10 MHz to guarantee a flat response across the modulation band-
width. All of the blocks (except the filters) must reject their poles
above 300 MHz. This effect limits the cumulated of the three
2235
RF gain stages below 15. However, AM/PM distortion also in-
creases with the quality factor and can cause loop instability
above 30 , practically limiting the cumulated below 10.
To find the correct phase alignment, an automatic calibration
algorithm was implemented. Every 802.11 packet is preceded
by a pure sine ramp-up lasting 2 s. During this period, the DAC
rms voltage (0 V) is applied on the ( ) channel. The Carte-
sian feedback channel is opened after the differentiators, and
this output is monitored with a comparator. If positive, the dig-
ital phase is incremented by 5.6 , else . This algorithm
finds the for which the downmixer output is null, which is
a sufficient condition for the loop to be aligned. From any be-
ginning phase, the maximum number of steps taken to converge
corresponds to an angle or to 32 steps. With a 40-MHz clock,
this is done in less than 1 s in the worst case. Then the Carte-
sian feedback channel is closed, and the Cartesian feedback
starts it operation with the preamble.
The Cartesian feedback loop also offers a very simple method
to calibrate the LO leakage. First the Cartesian loop is turned
on, but the RF gain stages are turned off. The and DACs are
turned on with code 0 at their inputs. The offset voltages at the
outputs of the baseband amplifiers are monitored with compara-
tors and zeroed with two simple current DACs. This algorithm
compensates for any offset in the downmixers, DACs, , and
baseband amplifiers. Any remaining offset in the upmixers is
screened by the amount of baseband gain. The 802.11 carrier
leakage constraint of 17 dBc can therefore be met even with
severe mismatches.
3) Block-Level Description: The downmixers are the most
critical components of the loop. They set the overall linearity
performance as well as the noise floor. It is preferable to put
switchable gain at the RF to maximize their dynamic range.
When working at the PPA saturated power, the amplitude of
the downmixer inputs is around 4-V peak-to-peak differential.
Due to transistor breakdown voltage, no direct switching of this
input signal is possible. Therefore, each of the 6-dB gain step
is implemented as shown in Fig. 20 with only the resistor value
changing. This structure is inherently very linear with a
gain, which can be matched to an equivalent resistance in the
baseband section to make the gain process independent. The
switches S1 provide additional isolation between the ON stage
corresponding to the selected gain and the four OFF stages acting
as parasitics. The switch S2 protects the OFF structures from
2236
Fig. 19. Channel I rotator transconductor circuit and RF switches.
Fig. 20. Channel I downmixer transconsductor and RF switches.
breakdown for the biggest input voltages. The downmixer cur-
rent consumption is 2 mA.
A linear converter is placed after the Sallen-and-Key
filter, consuming 0.5 mA. The current-mode output of the down
mixer is subtracted to the reference current flowing from the
converter, and the resulting currents drives the baseband
amplifier input. The Cartesian feedback, if stable, maintains a
near-zero differential voltage at its inputs; therefore, the output
of the downmixer is a differential virtual ground node helping
the linearity.
A high linearity baseband amplifier of gain dB fol-
lowed by a dominant pole (10 MHz) follows the downmixers.
The amplifier provides a process-independent gain for in-band
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
signals and presents a transmission zero for high frequencies.
This transmission zero increases the overall Cartesian-feedback
loop phase margin. This amplifier consumes 0.5 mA.
The upmixers have two transconductors in parallel. One is the
phase-rotating transconductor described above. The other one
is a highly linear transconductor used when the output power is
below the minimum level sustainable by the Cartesian feedback
loop. Cartesian feedback is used for the upper 24-dB range and
the open-loop structure for the lowest 18 dB.
Two RF paths are implemented in parallel for the
4.95.9-GHz band and the other for the 2.4-GHz band.
They both consist of three stages of RF gain working in the AB
class with the last stages embedding an on-chip differential to
a single-ended balun. The primaries of the balun are connected
to the input of the down mixer for the 5- and 2.4-GHz bands.
The secondary provides a 50- single-ended output. The
5-GHz path has a 3-b tunable central frequency using capacitor
switching of a resonant LC-tank load. The targeted modulated
power is 0 dBm for 802.11a ( 2 dBm for 802.11g), meaning a
saturated power of at least 12 dBm (10 dBm).
4) Measurements: Fig. 21 shows the spectrum mask com-
parison between open-loop operation and closed-loop operation
at the same output power. Table II summarizes the measure-
ment results. The output power variation with temperature from
20 to 85 is less than 1 dB and is flat across the whole band.
The 5-GHz RF gain stages suffer from a design mistake (insuffi-
ciently attenuated common-mode oscillation) and exhibit higher
power consumption than expected and lower output power.
Overall, this architecture is extremely promising and will
allow an easier integration of CMOS power amplifiers, with re-
duced compromises on power consumption and performances.
This architecture will be more efficient than any scheme of
envelope feedback [2], [4].
PERRAUD et al.: A DIRECT-CONVERSION CMOS TRANSCEIVER FOR THE 802.11a/b/g WLAN STANDARD
Fig. 21. Transmitter output spectrum mask: Cartesian
improvements.
Fig. 22. Die photograph.
III. CONCLUSION
The first 802.11a/b/g CMOS transceiver utilizing a Cartesian
feedback transmitter has been described. The transceiver also
offers the smallest die size, the widest frequency coverage,
and the highest level of integration Fig. 22 reported today for
802.11a/b/g compliant devices without compromising perfor-
mance ( 73-dBm receive sensitivity in the 54-Mb/s mode,
EVM of 3% in the 54-Mb/s mode at 2-dBm output power).
The transceiver was also designed to support colocation of
other communication standards on mobile platforms and is a
great candidate for a wide range of new WLAN applications.
The next version of this transceiver already incorporates the
Codecs, the AGC/CCA algorithm, digital front-end filtering,
and a digital interface to its baseband companion chip.
ACKNOWLEDGMENT
The authors would like to thank J.-M. Glasser and E. Donelly
for their contribution to the design phase. The contribution of
2237
P. Gattel, A. Troubat, and F. Pourchet was greatly appreciated
during the physical design phase. Collaboration with the signal
processing team of NewLogic was also a key to the success of
the transceiver.
REFERENCES
[1] A. R. Behzad et al., A 5-GHz direct-conversion CMOS transceiver uti-
lizing automatic frequency control for the IEEE 802.11a wireless LAN
standard, IEEE J. Solid-State Circuits, vol. 36, pp. 22092220, Dec.
2003.
[2] M. Zargari et al., A single-chip dual-band tri-mode CMOS transceiver
for IEEE 802.11a/b/g WLAN, in Proc. ISSCC Conf., 2004, p. 96. paper
5.4.
[3] J. L. Dawson, Automatic phase alignment for high bandwidth cartesian
feedback power amplifiers, in Proc. IEEE Radio and Wireless Conf.,
Sept. 2000.
[4] L. Perraud et al., A dual-band 802.11a/b/g radio in 0.18 m CMOS,
in IEEE ISSCC Dig. Tech. Papers, 2004, p. 94.
[5] L. Perraud et al., Fully-integrated 10 GHz VCO for multi-band WLAN
feedback applications, in Proc. ESSCIRC Conf., Sept. 2003.
[6] N. Sornin et al., A robust cartesian feedback loop for a 802.11 a/b/g
CMOS WLAN transmitter, in Proc. RFIC Conf., June 2004.
Laurent Perraud received the engineering degree
from the Ecole Polytechnique, Paris, France, in 1998
and the electrical engineering degree from the Ecole
Nationale Suprieure des Tlcommunications de
Paris, France, in 2000.
He joined IBM, La Gaude, France, where he
contributed to the development of GSM/WCDMA
chipsets. In 2002, he joined NewLogic Technologies,
Sophia-Antipolis, France, to contribute to the devel-
opment of WLAN synthesizers and to RF system
analyses.
Mr. Perraud received the Physics Department Prize of the Ecole Polytech-
nique for his patented work on PECVD new material for advanced CMOS.
Marc Recouly received the engineering degree
in electronics from the Ecole National Suprieure
dElectronique (ENSEEIHT), Toulouse, France, in
1977.
He has worked with Thomson, Alcatel, Setsys,
and Sagem, as a Research and Development System
Engineer in the field of radio communications. His
main focus has been the development of mobile
phones. With the high level of integration of these
devices, he carried on as an RF System Engineer in
the microelectronics field. He joined IBM in 2001
and then NewLogic Technologies, Sophia Antipolis, France, in 2002, where he
is in charge of the RF system of WLAN solutions.
Christophe Pinatel received the M.S.E.E. and Ph.D.
degrees in monolithic GaAs HBT power amplifiers
for cellular communications from the University of
Paris XI, France, in 1996.
He joined STMicroelectronics, Grenoble, France,
in 1996, where he led the design of GSM and CDMA
RFIC front-ends. In 2000, he joined IBM, La Gaude,
France, to manage the GSM/WCDMA transceiver
development team. In 2002, he joined NewLogic
Technologies, Sophia Antipolis, France, to manage
the RFIC team and lead the WLAN transceiver
project.
2238
Nicolas Sornin received the engineering degree
from the Ecole Polytechnique, Paris, France, in
1998, and the M.S.E.E. degree from the Ecole
Nationale Suprieure des Tlcommunications de
Paris in 2000.
As a student, he worked closely with the WLAN
development team of Radiata. In 2000, he joined
IBM, La Gaude, France, where he contributed to the
development of GSM/WCDMA RFIC Front-end.
In 2002, he joined NewLogic Technologies, Sophia
Antipolis, France, to contribute to the development
of WLAN transceivers and lead the development of Cartesian feedback
transmitters.
Jean-Louis Bonnot received the engineering degree
from the Ecole Nationale Suprieure des Mines de
Douai, France, in 1983 and the M.S.E.E. degree from
the Ecole Nationale Superieure des Telecommunica-
tions de Bretagne, France, in 1985.
He joined ST Microelectronics, Grenoble, France,
where he contributed to the development of analog
and mixed-signal chipsets (SLICS, CT0). He also
contributed to the development of synthesizers for
GSM transceivers. He joined VLSI in 1998 to start
the RF CMOS activity and developed a fractional-N
Bluetooth synthesizer. He joined NewLogic Technologies, Sophia Antipolis,
France, in 2002 to contribute to the development of WLAN transceivers and
lead the development of the synthesizers.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
Frederic Benoist received the engineering de-
gree in microelectronics from the Ecole Nationale
Suprieure dElectronique et de Radioelectricite de
Bordeaux, France, in 1994.
He joined ATMEL Corporation, Rousset, France,
in 1995 as an Analog Design Engineer, where he
designed various general-purpose CMOS analog
circuits and mixed-mode functions including GmC
filters and voice Codecs. He joined IBM, La Gaude,
France, in 2001 as a Senior Analog Design Engi-
neer. He worked on low-noise current-mode and
switched-capacitor circuits for 2.5 G/3 G wireless applications. He is currently
a Principal Engineer of analog design with NewLogic Technologies, Sophia
Antipolis, France, where he is in charge of analog baseband block development.
Myriam Massei received the engineering degree
and predoctoral degree in microelectronics from the
Institut Suprieure dElectronique de Mediterrane,
France, in 2000.
She joined IBM, La Gaude, France, where she
contributed to the development of GSM/WCDMA
chipsets. In 2002, she joined NewLogic Technolo-
gies, Sophia Antipolis, France, to contribute to the
development of WLAN transceivers and especially
to the development of Cartesian feedback transmit-
ters.
Olivier Gibrat received the Ph.D. degree in multi-harmonic load-pull PA char-
acterization from the Ecole Nationale Suprieure des Tlcommunications de
Paris, France, in 2000.
In 2000, he joined IBM, La Gaude, France, where he contributed to the devel-
opment of GSM/WCDMA RF front-end technology. In 2002, he joined New-
Logic Technologies, Sophia Antipolis, France, to contribute to the development
of WLAN transceivers and especially to the development of the RF receiver
front-end technology.