A/D CO}iVERTE,RS

9.1 Objectives....-. ""' 9-1

9,2DiscussionOf Fundamenials"' ' ' "''9-1

9.3 Equipnrents Required.... " 9-1C
9.4 Experimenis Anci Records' ' " " i- 1 0

Expeiment 9-1 ADC0804 Converier

Experiment 9-2 ADC0809 Converter
o-'1 6
9.5 Quesiions... ..
Unit 9
v! l.= -=:

9.1 OBIECTT\ES

4
. un.irsiar..iing the operation of an analog-io-digitai converter.
2. Understanding the characteristics of ADC0g04 and ADC0g09
J Understanding the applcaiions of ADC0B04 and ADC0809.

9.2 DISCUSSIONT OF FTNDAMENTALS

Analog{o-dgital converters (ADC's or A/D converters) translate frorn analog

measurements, which are usually continuous voltages or currents, to digital
words used in computing, data transmission, information processing and
storage, and control systems. we do this conversion, because digital signals
are easy to store, debug {using a wide variety of encoding techniques), and are
almost free from noise.

The Operation of Analog-to-Digital Converter

Fig. 9-1 shows the transfer characte'istic of an ideal 3-bit ADC. The anaiog
input range, from 0 to 1V, is quantized by dividing ths contjnuum into 8 discrete
ranges. All analog values wiihin each given range are represented by the same
digital code, which corresponds to the nomlnal midrange value. Therefore there
is an inherent quantization uncertainty or quantization error of t1/2 least
significant bit (LSB) in the analogto-digital conversion process. The only way to
reduce this quantization unceriainiy is to increase the number of bits.

The Q, quantization value or quantum, is the smallest anaiog difference whio:

can be resolved or distinguisheci by the A.DC. lt can be expressed by

tu trt1 I
1a 1 1n

9-1
 ,

Unit 9 I

A/D Convet:rs I

(
Digital output
(

(
t/ (

I
(
st8 (
(
ideal tanstion
(
3/8 011 Nominal quantized value t
(
2/8 010 t
1/8
I
{
I
6/8 7/8 C
FS
I Analog
rnput t
t
Fig.9_1 ldeal 3_bitADC transfer characteristic !
I
where Fs is the furi scare range
lvhich is equar to [(2,-1)r2n1, and
t
resolution determined by digital
output bts n. Thus the greater
2n is the
t
higher the resoluton' ln general,
the n value, the a
ADC manufacturers indicate the
the unit of bits, for exampre, the resorution
resolution n t
on technical manual.
of ADC0g04 s expressed by g
bits I
I
a
There are a great number of circuit designs for fuD
converters: such as a
digital-ramp, successive approximation,
frash and tracking types. The a
successive approximation is the
onry type of ADC used in our
experiments, we
a
therefore introduce the operation
of successive-approximation ADC a
as foilows.
a
Fig' 9-2 shows the brock diagram a
normar operation proceeds as foirows.
of g-bit successive approximation
ADC. The
The sample_and_hord (s/H or s&H)
a
circuit is used to retain the analog I
input voltage Vr that was present
at a giver: J
a
a
a
time before the conversicn stas, and mainiain it consi::: ..:
during the conversion period. The control logic seis i-= -.:s:
(MSBi D, cf r"eg.stertc i. ,vith ali cther bits ic C. T:e j:;:= -.:
=

(DAC or D/A) converts the binary codes inio an analog cui:_:

can be evaluated by

f {D) = 2n-i * Q:
=
')"-1 *U : ln
1're;'
.

:"

The DAC output V(D) is just a half of the reference voitage ,.,.=. - -
=
compares the V(D) with the analog input Vi. lf V > V(D) ihe ' -.- =

Vi < V(D), the 'l is removed from Dz, and it is tried in ihe nex .-:s: s

D6. Thus a 1 is tried in each bit of register outputs until at the e.: :
the binary equivalent of Vi is obtained.

Sampie & Hold

Registe:

qD-D-DD:,
ViSB
Digitai oit:

Fig.9-2 Block diagram of a successive approxin:a::cr : *- l

9-)
Unit 9 AiD Converters

Analog-to-Digital Converter -- ADC0804

The ADC0804, whch is a 20-pin dua!-in-line package, is an 8-blt ADC r,vhich

operates on the successive approximation principle. lts major characteristics

include single 5V power supply, 0V to 5V analog input voltage range, 15 mW
power dissipation, and 100 ps conversion time. Since the resolution of
ADC0804 is B bits, the analog input is divided into 28, or 256 discrete ranges.
Wth 5V reference voltage, each range represents 51256=0.A1953V. Thus the
digital output code 00000000 (00H) corresponds to an analog input voltage of
0.00V, and 11111111 (FFH) represents 4.9805V. The unadjusted error, which
contains full-scale, offset and nonlinearity errors, is t1 LSB or 0.01953V

CS I \---l 20 Vcc
RD 219 CLK R
!VR 3 i8 D0(rsB)
CLK IN 417 D1
INTR 5 16 D2
Vw (+) 615 D3
VN G) 714 D4
A GND 813 D5
Yvr;r 12 912 D6
D GND i0 11 D7(MSB)

Fig.9-3 ADC0804 pin configuration

The connection dagram of ADC0804 is shown in Fig. 9-3. When data is to be

read from the output port Do - Dz, the combinaiion of both CS and RD being
low will enable the 3-state output latches to provide the 8-bit digital outputs.
Either of CS or RD is high, the outputs Ds to Dz will be floating. The
ADC0804 conveder is started by having CS and WR simuftaneously low.

9-4
Unii 3

WR goes io high, the conveer s== :-

This resets the B-bit register. When
converson process. The CLK lN (pin 4) is the input pin of clock pulses v,1c

irequency can be from '100 to 800kHz. The INTR pin remains high during ihe
conversion anO lvil make a high-to-iow transition if the conversion is completed.
The analog differential input voltage is applied to the pins Vln(+) and V,(-). lf a
{\
3
single-end input s desired, the V"(-) should be connected to ground. The
AGND is the ground for analog signal and the DGND is for digital signal. Notice
that the reference voltage is either a half of the voltage which is applied to the
V"" pin, or is equal to the voltage which is externally forced at the V,"/2 pin.

CI,K R

Fig.9-4 lnternal clock generator of ADC0804

The clock for the ADC0B04 can be derived from an e*ernal source connected
io CLK lN (pin 4), or an external RC network can be added to provide
self-clocking. As shown in Fig. 9-4, an et'iernai RC network is connected io the
pins CLK R (pin 19) and CLK lN (pin a) to provide ihe clock for the ADC. The
clock frequency can be found by

i--,=
JLL!-
1
tHz) I Y--.
1.1 RC

9-5
 A/D Ccnveilers
Unlt 9

Fig.9-5ShoWSananalog-to-digitalConverierwiththeADC0Bo4.Theanalog
inputsignalisconnectedtoVn(+)inputandtheamplitudeiscontrolledbythe
VRrAnotherinputV"(-)isConnectedtoground.Thereferencevoltagetcthe Rr' Rz and
is provided by +5V with the voltage divider containing
V,"/2 (pin 9)
VRl.TheCombinationofclandRgdeterminestheclockfrequency.Thes
enable the ADC
RD (pin 2) are directly connected to ground to
(pin 1) and
(pin 5) are wired to the switch
For convenience,iheWR (pin 3) and R
signal in our experiment late'
SWr to simulate the control

Rr 6
2k C2 0.1 1F
7
VRr
500
8 13

VRz 10k = g12

& 10 11
a1.
olpFr
Fig.9-5 ADC0804 ADC circuii

o_
Analog to Digitai Conveer -- ADC0809

The 4DC0809. which is a 28-pin dual-in-line pacKa!. s =- :-:'

operates on the successive approximation technique,.,,:- i-:-.--=
It operates in the conditions of single 5 V power sup.,. : .

voltage range and '15 mW power dissipation. The ADCl3ll e

inputs due to the B-channel multiplexer circuit. Since ihe r=s:

is B bits, the analog input is divided into 28, or 256 dis:-::=
-eference voiiage, eaeir rarrge represents 5Vi256=0.C :::
output code 00000000 (00H) corresponds to an analog :::-
and 11111111 (FFH) represents (2551256) x 5V = 4 98:,
error including full-scale, offset, nonlinearity and multipiexe' =

0.01953V. The clock, 10 kHz to 1280 kHz, is required to c:

operation. The typical conversion time at the clock of 64Ck: =

Fig. 9-6 shows the connection dragram of ADC0809. Pins ; : : - :

and 26 are the anaiog inputs IN7 to lNo; and pins 21 ,2A 't? '1 : 'a
are ihe digitai outputs Dz to Do, respectively. Pin '10 is clocr -:-:
the power input V"" (pn 11) and the reference voltage incu, ,.=' - :-
be tied together for convenience. Notice that this arrangerne-: ,',

accuracy of the ADC ifthe powersupply has a bad stabiiity .:. ==:
channel is seiected by controlling the states of the address ::::.
ADDA (pin 25), ADDB {pin 24), and ADDC (pin 23). For exarrc
=
to the inputs ADDA, ADDB and ADDC select the analog inoui :-:--= ,.

9-1
 A/D Converters
Unit 9

IN; i 28 IN:
IN.l 27 iNi
7
INs 26 IN
3

Ir'k 25 ADD A
4
II.h )7- ADD B
5

START !) ADD C
6
tra /./ ALE
7
21 D1
D3 8
20 D6
OUTPUT ENABLE 9
f'\ -
CLOCK 10 19
18 D,
i1
V*r(-) 17 Do
12
GND l3 76 V"(-)

D1 15 D2
14

Fig.9-6 ADCO809 Pin configuration

interface with a microprocessor or

The ADC0B09 has been designed to directly
eliminates the need for a
system. The 3-state output capability of the ADC0809
(end-of-conversion), oE
peripheral device. The control lines START, EoC
are usually connected to the
(output enable), and ALE (address iatch enable)
control lines' the ADC0809
standard control-bus lines of cPU. Through these
data between them' As soon
can easily communicate with the cPU to transfer
aS the ADC0B09 has completed the
conversion, the EoC signal is enabled to

interrupt the cPU. When the cPU is ready

to receive data from the digital
reads the digital data and then
outputs, the cPU enables the oE signal and
ADC0809 for the next conversion'
enables ALE and START signals to restart the
encoder inputs
of course, if multiple channel inputs are used, the address
should be selected during the restart cycle'

9-8
i- r

iNo V"" Dc

INr D1

IN: Dz

rN I)
IN D+

liri D5

iNa De

iNz Dr

Y"(+) ADD c

Y"(-) ADD B
OE ADDA
CLK GND

ALE START
EOC

Fig. 9-7 ADC0B09ADC circuit

r-e * : -
A praciicalADC circuit with the ADC0809 is shown in Fig. 9-7 -- =

directly connecied to ihe START pin. This uses the EOC outcl: s:-= :- :--
the ADC0B09. The clock pulses is applied to ALE and CLK p :s :: :r-:-:
ADC operation. The magnitude of the analog voitage to lN:1.c-: s ::-:--
by adjusting the VR1, whereas those of other inputs (lN1 to IN- a-=
by the voltage divider network (Rr to R,). The analog char':
selected by the states of SWl, SW, and SW3. The LED disca.'
staies of digital outputs.

9-9
 Iq
(
(
Unit 9 A/D Converters I
(
(
9.3 E Qr.IIPllEi.m REQUIRED I
(
(
1 - Module KL-92001
(
2 - Moduie KL-94001 (
3-DMM (

9.4 EXPERIMENTS Ai\D RECORDS (

Experiment 9-1 ADC0804 ND Converter

I

f 1. Locate ADC0804 Analog{o-Digital Converter circuit on Module

KL-9400'1. Power on the power supply.

f2. Using tne ijn, measure the'voltage atY,u12 input (pin 9) and s]1wtV
, \,
adjust the VR.r until the rilasred volti:ge reaches 2.5V. This sets the
ADC0804 analog voltage input fhge from 0V to 5V.

N1.\,.
13. Measure the analoE input (pin 6) and slowly adjust the VRz until the
rr., li.', 1
measurd voltage reaches 0V.
\l

E4 tnsert the connect plug in J1. rhis wi ;iil;tiiitri'outprts observe

dr r-r a.{.'
LED display states and record the results in Table 9-1.
:- l
lr', ..
5. Remove the connect plug from J1. The digital output will vary with the
change of analog inPut.

.\ ,r''
16. Carefully adjust the VR2 to get other analog input voltages listed on
Table 9-1, and repeat steps 4 and 5. Complete Table 9-1.

9-10
Experirnent 9-2 ADC0809 A/D ConverTer

l l 1. Locate ADC0B09 Analog-t.r-f)i3itat Con',:::-

KL-9400'i. Power on the power supply.

a.,r,, \ 1,
[]2. Connect a 120k1z, 2.5V square rave wiih

low=OV) to the clock input (CLK).

Il3. Set the switches SW, S\l/z and SWr

signal will come to the Ns input port.

[.]4. Carefully adjust the VRr to get individual anaiog voliag:

9-2.

15. Observe LED display states for each analog ino":

results in Table 9-2.

l'',
16. Caiculate the lnput voltage at input ports lNr to iN-
results in Table 9-2.

tr?," ' t
7. St the positions of switches SWg, SWz and SWr iisrec :-
.-". i; ' . /
assrEn an input port (lN1 to iNz) as the analog input ea:-

[8. Observe LED display states and recoro ihe results ir -== = :- :

9- i1
 A/D Converters

Table 9-1

Digital OutPut
.Ar::log
Voltage
lnput ll-
(v) Binary Hexa-decimal Binary Hexa-decimal

0.0

0.5

1,0

1.5

2.0

2.5

3.0

?tr

4,0

4.5

5.0
U:il- 9

Table 9-2

Digital Outpui

Calculaied Value

Hexa-decimal

>" -_1
 AJD Conveters

Table 9-3

I
Analog lnPut Digital utPut
(Calculated Value) (Measured Value)

sw3 I ,*, SW1

Hexa-
lnput Port Voltage Binary decimal

GND GND +5V lNr

+5V GND lNz

GND

GND +5V +5V lNa

+5V GNE GND lN

+5V GND +5V lNs

+5V +5V GND !No

+5V +5V +5V lNz

Unit I A,'J Ccnvede,'s

9.5 QUESTTONS

1. Comment on ihe function of R and Cr in ADC084 ADC crr:r,: :' = ;

g-5- ''.'-..1., I .,i'., ,'. i.l, ,.' -''J','lt ' "'" u '' L' i.v';'' ';'
1..- {,-. 'ri
l
i' ' '' t' Jtl
q
2. Comment on the function of switches SWi, SWz and SW3 in ADC08']3
ADC circuit of Fig. 9-7.

3. Name the unadjusted error of ADC0B04.

4. Name the unadjusted error of ADC0809. . L ,

!. : 1" I
I \ .{,, i lvY(,v 'i'
' 1\l
'{ _.

l, r\ 1 '' ,'u
b,i

9-15
 L

gi,*fi,hrj0
T}iA CChIVERTER.S

10.1 Objeciives..
10.2 Discussion Of Fundamenials '
1 0.3 EquiPments Required.

10.4 Experimenis And Records.., " "

Experiment 10'1 DAC0800 Untpc'a' ': ':'
ExPeriment 10-2 DAC0800 BiPoiar '::t::
10.5 Questions..
Unit 10

Io I OBIECTnTS

'1. Understlndi:g ihe operation cf a digltal-tc-analcg cc^

2. Understanding the operation of DAC0B00.
3. Studying how to generate unipolai'and bipolar ouiputs

i0.2 DISCUS S ION- Or: FLD\TDAME ITAI S

The digital-tc-analog converters (DAC's or D/A convel=-:

transforming the digiial signals of transmitteC data, store: :-
results of computation back to analog signais for conirol, incr.. =:
furlher analog processing.

DAC Operation

ln short, D/A conver-ters are the devices by which digital sys:e-

with outside world. A DAC converts digital input states to ana':g
or currents. The schematlc symbol of a 4-bit DAC is shown ir = :

f\"
U)
DigitalD:
input
'Do Di

(a) Schematic symbol

n
u3 D2
0000 0 00
0001 1

0010 a

.1
rJt
0011 01
0100 4 4n

.ln
t,
0101 5 lv

0110 6 11
0111 7 11
(b) Truth table
Fig.i0-1 4-bit DAC

t0- l
 D/A Conve-ters
Unit 10

the register output o a

The digital inputs De, Dz, Dl and Do are usually driven by
digital system. Fig. 10-1(b) shows the truth table of ihe
4-bit DAC' Each input
value. over the ouipui
a
binary word produces a single. discrete analog output C
range of the converter, 2a or 16 different voltage values are
produced including
with input.
t
zero, and the output has a one.to-one correspondence a
a
I
I
I
I
Digitally Analog
(
controlled voltage I
switches output
{
Analog
curfent {
output I
Fig.1O-2 DAC block diagram (

Fig. 10-2 provides a DAC block diagram. The DAC includes a precision

resistor network, and an

reference voltage source, digitally conirolled switches,
controlled
oP AMP. Each resistor in resistor network is connected to a digitally
vl.*1. The other end of
switch, which connect the resistor to the reference voltage
The digital nput
each resistor is connected to the summing point of oP AMP.
converts the DAC
states determine the states of switches and the oP AMP
output current lo,1to the output voltage Vo6'

There are two

Resistor network is the major configuration of DAC circuit'
network' The
popular types: weighted-resistor network and R-2R ladder resistor
weighted-resistor method can be considered that the
value of each summing
bit actuating the
resistor is inversely proportional to the weight of the digital
advantages of simplici
series switch. The weighted-resistor technique has the
DAC designs is
and high speed. A dfficul in implementing higher resolution
value resistors cause
that a wide range of resistors is requred, and very high
10-2
Unit 10

probiems with both temperature siability and si/,:c- -: s:==-

u/ere to be manuactured in integrateo circuit (lC) fcr- s--- i
iotaliy impractical. The advantage of the R-2R iacce' *= -: -
values (R and 2R) of resistors are required, with tne 'es- '.=-'
=
or trimming.

Rp:R Rc:R R":R R. :I

I
1

D3 D1

09
T _1_
-=

Fig.10-3 4-bit R-2R ladder DAC

Fig. 1C-3 shows a 4-bit R-2R ladder DAC circuit. The resis::- -.:,,:-. ::-: s:
--=
of series resistors of R and shunt resistors of 2R. Cbse-,.
='.:' :' ----=
ladder configuraiion reveals that at any of points A, B, C, anc I :-: -:: s:- - - :
=
2R looking to the righi; therefore the reference inpr,rtic::= =-:='-:s.
resstance of R. According to this property, the output curre: .?- :: :=- ^=:
from the foilowing:

T
1 n
- Y_tC_t/ r\
-r'-^,

lD-1/ -

f^:I-lr / :) =I t
a(
t

i 0-j
Unit 10 D/A Conve:-s

is =I/ 2:1 I 8

Iu :ls/ 2 =I I 16

, D1 , D,
D, -1------T-- Dn) J
Io,u:Io+1"+Ir+1, -,( \2 : ll-
4 8 16)
|
J
J
J
where Ds, Dz, Dr and Ds ma! be either "1" or "0" depended on the positions of
I

switches.
I
I
I
lnput Weight
I
For a DAC each digital input bit has its own weght whch is the analog output
I
{
value when the bit s 1. Consider the 4-bt DAC of Fig. 10-1(a)' lf Do - 1 and I
Dr

=Dz= Ds =0, the analog output value of 1V is the weight of Do' Similarly, the I
weghts of Dr, Dz and Ds are 2V,4V and BV, respectively. To obtain the resultant I
analog output, it is simple by adding these weights up. For example, the analog
output voltage Vo,t should be 4+2+1= 7Y for the digital input 011 1.


Resolution and SteP Value

The resolution of DAC is defihed as the smallest difference of the analog output

(
when the digital input changes a unit count. lt is usually a LSB weight. Referring
to Fig. 10-1(b), the Vou, increases an analog value of 1 V for each unit count fed
J

to the digital input. Thus the resolution of this DAC is 1V'

(




e
I
I
10-4
t
t
t
 DAC
__ir_-rl- cilnicr i D, o tir'
Clock
resolution
1V

Resoiutior:ii :p \,'dur1 v
OV
I -----------) Time

Fig.10-4 Staircase-ramp DAC

The resolution is aiso calied the siep value or the step height. Constder the 4-bi.i
staircase-ramp DAC shown in Fig. '1C-4. The output voltage increases by 1V for
each unit count fed to the input. The output difference between steps, called the
step heighi, is exactly 1V.

DAC 08CI0 Digital-to-Analag Converter

The DAC 0800 is an inexpensive monolithic B-bit DAC including the reference
voltage source, R-2R ladder and transistor switches. Fig.'10-5 shows the pin
configuration of DAC0800.

10--
 D/A Corvece-s
Unit 10

Threshoi,l..
conoL
vrc Compensatton

Vref (-)

Vref (+)

]out +v
D7 DO


D6 D1

D5 D2
D3

D4



Fig.10-5 DAC 0800 pin confguraton

+4'5 V to t18 V' Power
Power supply requirements of the DAC0800 arc
dissipation is 33mW with + 5 Vs6 power supples and the settling
time is about

g5 ns. wth complementary current outputs Ioo, (pin 4) and ,*, $,n 2), the
DAC0800 can be used in either unipolar or bipolar output'

Fig. .10-6 shows the unipolar voltage output DAC using the DAC0800 with


pA741. The V,"(-) pin is grounded through the resistor Rz. The
positive

reference source +5 V is applied to V,"d+) pin through series resistor a
Rr

Therefore the reference current l* flowing through Rr is found to be a

C
V"
reJ ( 10-l C
I ,., )
=+

R1 e
C
e
The output current lo s
C
C
- L',n,Dr . D6, Dr,D., Dr, D=
!a'r-r,\,
=-' -Dr_Do.,' ( 10-2 ) t
I 8 16 32 64 128 256 I
I
i0-6
t
(
I(
(
. ? ,1:1

1
- 1L
a\ Yr

Cz
0.01rF I\l +./ N

----"Y VV ---
I ref +5V
Yef Iout
+5V
---;> R1
1tl
ta
<_ l
n 1 l- DACOSOO
rsB
lIlsB
'- s 6 7 B 9 10 11 12 I
R2
4.1k
Do Ds D D3 D2 Dl Do

Digital input

Fig.10-6 DAC0B00 unpolar voltage output circuit

This Io,,, , the current flowing out of the converter, is then converted to an output
voltage by the yA741 The voltage output Vout ct'l be given by

Vn,t = Iou,R, ( i0-i )

The bipolar voltage output circuit of DAC0800 is shown in Fig. 10-7. The T

pin is connected to the nonnverting nput of pA741 nstead of to ground tn

10-6. lhus the p4741 ouiput voltage can be evaluated by

f,/ _f f
f nr, - \1 or,, -
r
1
\D
oru )l\1 ( 10-r )

where Iou, and Ir* are complementary current outputs. By definition, the full

scaie curreni can be expressed as I., = Iou, + [* , and the L it

I
- okt - _
I
-)
--I
^ ot
( iO-s )

10-7
Ut 1O D/A ConverEs

-12V +12Y
(-,
vl Cz
0.1 pF 0.0i,;F 0.1.rF

-r-l r_L
I

-=
Iref
Vef =- t4 31613 -l
+5V Rr
lJsl
4.7 k DAC0800 4

I { lvlsB LsB 2- 4
'" 5 6 7 B g tolll2 i
R3 -5V
4.7 k
D7D6 D5 DqD3DzDl Do *
Digital input

Fig.l&7 DAC0800 bipolar voltage output circuit

Substituting Eq.(1G5) into Eq. (10-4), we obtan

Y*,=21 *,R4-IrrRu ( 10-6 )

10-8
tinit 10

a
!
1 0.3 EOUIPMEII=| REQIllRED

1 - Module KL-92001

2 - t'Jodule KL-94001
3-DMM

10.4 EXPERI},IENTS AND RECORDS

Experment 10'1 D.A1OSOO unipolar Voltage Output

on
f-lr
1,,] r Locate DAC0B00 unipolar Digital-to-Analog converter..circuit
Module KL-94001. lnserri the connect plug in J1 to connect
the

DAC0B00 output lout (pin 4) to the p'A741input (pin 2)'

in Table 10-1'
a)2. Calculate and record the step value
i'
f 'r:rr .

L_.1r. st input switches D0 through D7 to correct positions 0000 0000.

(.0'=GND,"1"=+5V)
4,. i,, l-i '

[4,UsingEqs.(10-2)and(10-3),calculateandreccrdtheoutpr-r'.current
lout od output voltage Vout in Table 10-1 '

[5.RemovetheconnectplugfromJl.MeasuretheloutbYconnectingthe
DMM current meter between DAC0800 output and p'A741 input'
Record the result in Table 10-1.
i . ,

Remove the DMM and reinsert the conneci plug in J1'

Measure the
[6.
outputvoltageVo,tt:,A741output(O/P)usngtheDMMvoltnreterand
record the result in Table 10-1'

Foliwing the digital codes listed in Table 10-1 , change the

switches i-
17.
toDoandrepeaistepsSand6sequentially,Reccrdthej.esLl:s
Table 10-1 .

i 0-9
lJnit 10 D/A Converers

Experiment 10-2 DAC0800 Bipolar VoltaEe Output

n 1. Locate DAC0800 Bipolar

KL-e4001. lnsert
"ffi.%lfti,ss
Digital-to-Analog Converter
in J1 and J2.
on Module
Id
G
f]2. Calculate and record the step value in Table 10-2. a4
a
13. Sei input switches D0 through D7 to correct positions 0000 0000. ( " 0 ' C
=GND;"1"-+5V) d
C
,
14. Using Eqs. (10-2) and (10-6), calculate and record the values of voui in

Table 10-2. C
C
.-t15. Using the DMM, measure the output voltage Vout Itd record the result f
in Table 10-2. C
C
E6. Remove the connect plug from J1. Measure the output current lort bY 4
C
f8ilr%-**8. ,** in J't and record the result in Table 10-2'
C
rnulft-t.*ro
it in J1. Measure the
I
J7. Remove the connect plug from J2 and insert d
l*, d
output current
in Table 10-2.
OV connecting the DMM in J2 and record the result
II
I
18. Calculate the value of lou,+ f * and record the result in Table 10-2.
II
[, Fjr\$V]h+f" digitar codes tisted in rable 1a-z', change the switches Dz Ia
to Do and repeat steps 5 through 8 sequentially. Record the results ln
(
Table 10-2.
I(
(
(
10-10
(
(
a
(
(
Unii 10
D,'A Cc.rre":==

Table 10-1

Step Value =

Digital lnput Analog Output

Dz Do D5 D4 De Dz Dr De
I ou,

Calculated Measured Calculated Measured

r\ 0
0 0 0 0 0 0
n n n n n n n
I

0 0 n 0 001 0

0 0 0 0 0 II
0 0

0 0 0 0 1 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 1 0 0 CI
n 0 0

1 0 0 0 0 0 0 0

1 I 1 1 I 1 1 1

Voltaqe in
Current in mA

t0-1i
Unit 10
D/A Conven= -s

Table 10-2

Step Value =

Digital lnput Analog Output

Dz Do Ds D D Dz D., Do
Calculated I neasured Value
Vort Vou, Io,o I ou, Iout * Iout

00000000
00000010
0 0 0 010 0 0

001A0000
01111111
10000000
't 0000010
10001000
10100000
11000000
11111111
Voltage in V
Cunent n mA

10-t2
lI!-i -

i0.5 QUESTTONS

in Fig. 10-6, i ihe digitai iriputs are i/ 4a4^1f

\J r L,l I \,/ U. -.-l^,.1.
UqiLLr,daii
L^ \^
r iri UU i- -.

voltage by ihe weight of bit.

2 From a point of view of the step size or the output range, cornpare the
unpolar output with the bipolar outpui.

According to the results of Table 10-2, comment on the relationship

between Io,,, and T
l oui

i0-i3
 z
Y
r''1

!
t

G@ffffi
FSK MODULATORS

13.1 Objectives.
tJ-t
13.2 Discussion Of Fundamentals
1 3.3 Eouipments Requrreci.

13.4 Experiments And Records

Experiment 13-1 FSK Modulators
13.5 Questions
rJ-
c l:i 13 iS{ S: L a:c i:

i3.l OB,ECTI\rES

'1. Uncjersirnding iiie rrncple oi frequency-shifi i<eying (FSK) mocjuiation

2. Measuring FSK signais.
3. Implementing an FSK modulator with LM566.

13.2 DISCUS SION OF F{.INDA}IENTAIS

ln digital iransmission repeaters can regenerate dlgital signals and improve the
ability against noise interference, and the use of encoding techniques can
provide debugging and correction functions. But digitai signals often occur
distortions due to its high-frequency components are easiiy attenuated for a
long distance transmission. To improve this disadvantage, a particular
processing (modulation) is need icr this purpose. Frequency-shift keying (FSK)
is a type of FM in which the modulating signal (digital signal) shifts the output
between two predetermined frequences - usually termed the mark and space
frequencies. The relationship between FSK and digital signals is shown in Fig
'13-1. The FSK frequency f1 corresponds to the digital input high, and the fz

repi'esents the digital low.

FSK technique is widely used for the transmission of Teletype information. FSK
standards have evolved for the years. For radio Telepe, the frequency of
2124H2 represents mark cr 1, and 2975 Hz represents space or 0.

-3,H:fl

FSK
signal
fil\
f1 f2 f1 f1 f1 f2 f1

Fig.13-1 Reiationship between digital and FSK signais

i.)-1
Unit 13
FSK Modulators

For data transmission over telephone and landlines, the commonly used
requencies are:

space = 127A Hz
mark = 1070 Hz

and

space = 2225 Hz
mark = 2025 Hz

Notice that the frequency difference (gap) of FSK sgnar equars 200 Hz.

The FSK modulator is used to convert the digital signal (square wave) into the
analog signal having two different frequencies corresponding to t're input levels.
ln this experiment, we use the frequencies of 1O7O Hz and 1270 rlz to represent
space and mark, respectively. A voltage-controlled Oscillator (VCO) can easily
generate these two frequencies. A practical FSK modulator using the LM566
VCo is shown in Fig,13-2. ln such cases, the oscillating frequency c,f LM566
can be found by

{ _
t- (t, \
I cc -r,inl
ro- R*ql 1 1

where v"" is the power voltage applied to 1M566 pin B, and Vn is the VCo
controlvoltage appled to pin 5.

if vo is constant, proper values of Rro, cs and v6 3r determined to generate

the LM566 output frequencies fo of 1072 Hz ano 1222 Hz. ln practice, the
lmtations of using LM566 VCO are as follows:

L_\-J
 r', rl

Unit 13 FSK ilbdulators

2k1]-(R,o(20kf'
fi75<V
'i-'cc<V

/o < 500 kHz

10v<v,,,<.24v

To generate the frequencies of 1070 Hz and 1270 Hz exactly, the digital input
levels, such as TTL levels 0V and 5V must be convertecl to proper voltage
levels befo'e applying to the input of VCO. The level shifter' (Q1 and Qz)
provides this purpose. The Qr acts as a NOT gate. ln other words, when Qr
input is high (5V), then Qr conducts and the output goes to low (about 0.2V)
causing the Qz to cutoff. lf Qr input s low (0$, the Qr is OFF and its output
rses to high (5V), and thus the Qz conducts. VVhen the Qz is OFF, the input
voltage of VCO is given by

VR.
l/,:-V^
' YRr+R,

and the output frequency of VCO is/. When Qz conducts, the input voltage of
VCO is

t/& I I YR2
Yr= t'
{rn, il YR )+ Ru

l,)-)
Uir 13 FSK Modulators


I


VCO
output


Digital
input


C

Cr 0.01r
0.01r

Rz 10k R4 100k
Rr 10k Rg 100k FSK output I
L]

Cz
l00opg -12v
1000p J

Fig.13-2 FSK modulator circuit.
I


and the output frequency is [. Therefore the output frequencies
and f2
rt = 1270 Hz
= 107A Hz can be obtained by carefully adjustng the VRr and VR2 values.
a

Both U2 and U3 are the second-order low-pass filters. The fourth-order low-pass
filter formed by cascadng these filters is used to filter the high-frequency
I

harmonic components on the output of LM566 and therefore the FSK
modulated sgnal is obtained.
a
lf the FSK modulated signal mentioned above is desired to transmit by an
antenna, a rnixer is required to modulate the signal to the frequency range in RF a
band. I

I(
(

a
(
J
I
I
a
l: /

;
;
;

Unil 13
FK Iodutators

13.3 EQUTPMENT REoII{RED

1 - Mociuie KL-92001
2 - Module KL-94003
3 - Osciiloscope

13.4 EXPERIMENTS AND RECORDS

Experiment 13-1 FSK Modutator

[1. Locate the FSK modulator circuit on Module KL-94003.

S^^+-odt'"
[2. connect Svdc to digtat signar input (l/p). Using the osciiloscope,
observe the LMS66 ouiput frequency fpn eilo adjust vRz to obtain
the frequency of 11za\z, and then rerrord the result in Table 13-1.

[]3. using the oscirroscope, observe ,^d "ZBIP?n" ,.o :"-('*Lignrr in

Table 13-1.

[4. connecr dgitatsignat input (t/p) t" 5iffi? (0v) using the osciltoscope,
observe the LME66 output frequency {pin 3i arnt aUlust VRr to obtain
the frequency of 1zr1Hz, and record the result in Table 13-1.

[5, using the oscilloscope, observe and record the FSK output signal in
Tabie 13-1.
Obte,-ge
Ll6. set the output of signal generator to TTL level and the frequen cy af 2ao
Hz and then connect the output toothe signal input (l/p) using
^digital
the oscttoscope, observe SBotlfllhte input, LMs66 output (pin 3).
"no
and FSK outputsignais in Tabie 13-2,

17. change the output frequency of signal generator to SkHz and repeat
step 6.

13-5
Unit 13 FSK Modulators

Table 13-'1

lnput LM566 (pin 3) Output FSK Output Waveform

Signal Waveform

OV

5V

l3-6
Tabie 13-2

lnpui 1rln L]-

Frequency 5 kHz

inpui
Waveform

LM566
(pin3)
Ontput
Waveform

FSK Output
Waveform
 FSK Moduiaiors
a

Unir 13


F
13.5 QUESTIOI'{S
rf
1. Describe the operations of Qr' Qz and LM566' I

VR2'
I
2. Describe the functions of VRr and

than the FSK frequencY, does the
FSK
3. lf the input frequency is higher I
modulator oPerate normallY? ;
t
t
;
?
t
t
t
C
C
I
{
(
(
(
(

i 3-8
 $

w@ffi &
FSK DEMODT]LATORS

14.1 Objectives.. 11'1

14.2 Discusson Of Fundamentals.., 14-',
14.3 Equipmenis Required. ..n,1'3.

14.4 Experiments And Recards..... ......... 1'-a

Experiment 14-1 FSK Demaduiators
14.5 Questions... 't-i
Unit 14 FSK Demoduldrrrs

1.4.1 OBIECTnTES

1. Performing a frequency-shifi keying detector using Phase Locked Loop.

2. Learning how to design a voltage comparator using an OP AMp

].4.2 DISCUSSION OF FUNDAMEN'IATS

As mentioned in chaptert3, the digital sgnal is converted into the FSK signal
by the FSK modulator for long distance communications. At receiver section, an
FSK demodulator is necessary to recover the original digital signal from the
received FSK signal. A phase-locked loop (PLL) is a good choice for this
purpose. ln short, the phase-locked loop s the control system that tracks the
frequency and phase of the nput signal. Recently, the PLL s widely used as a
dernodulator n many types of analog communication systems, such as {he AM
demodulator, FM demodulatol frequency selectol and chroma subcarrier
acquisition in color TV receiver. Similarly, many digital phas+.locked foops have
been developed to track a carrier or bii synchronizing signal in digiial
communicaton systems.

Basically, a PLL includes three major sections: Phase Detector (PD), Loop Firter
(LF), and Voltage-Controlled Oscillator (VCO). Fig. 14-1 provides the block
diagram of PLL.

Input
Vin
i1,D

Fig. 14-1 PLL block diagram

14-1
 I
I
t
t
Unit 14
FSK Demodula:crs t
t
t
considerthe PLL block diagram shown in Fig. 14-1. rf Vn changes frequen:', t
an instantaneous change will result in a phase change between A and B anc t
hence a dc level change at the output. This level shift will change the frequenc. t
of the VCO to maintain lock. lf the PLL is used as an FSK demodulator and the t
FSK signal is applied to the input, the output voltages V1 and V2 will corresponc t
to the input frequencies f1 and f2, respectively. Thus an input frequency change t
has converted into an output dc ievel change. when the pLL output is t
t
connected to the input of voltage comparator having a reference between Vr
t
and V2, the output signal of the comparator is the digital signal, or the FSK
t
demodulated signal.
t
t
sv(v66)
t
vRr
i.k C: C C t
0. I LI o lp o lp
t
R3 R,, R5
Dl
t
Rr7 r0K i0K l0k
1N4004
FSK
Qemodulated
Output t
t
Iir
pA741
&
r0k t
t
Ul t
cz
LM565
t
0.05r
t
t
Fig. 14-2 FSK demodulator t
t
ln this experiment we use LM565 PLL to perform an FSK demodulator shown n t
Fig. 14-2. The LM565 PLL inctudng the phase detector, vco, and anrptifier t
operates below the frequency of 500 kHz. The phase detector operates as a t
double balanced modulator and the VCO is an integrator-schmitt circuit. Power t
supplies +5V and -5V are appled to V"" (pin 10) and Vs (pin 1), respectively. t
The FSK signal is applied to the input of the phase detector. since a frequency I
multplier is needless n our experiment, pins 4 and 5 are clireclly tied together.
I
t
The reference output (pin 6) provides the reference voltage of the comparator
t
I
14-7 t
t

(t
I
Unit 14
FSK Den::- :::=

U2. The combination of internal resistor R* and external capaciioi' C. 133-31=s

as the loop f lter. The timing components vR1 and c2 determine the free-ii-- -:
frequency o the VCo. ln hesigning with the LM565, the important paran"e:=.s
of interest are as follows:

Free-runnin g Freq uency

ln the absence of the input signal, ihe output frequency of the VCO is called the
free-running frequency,d. ln the circuit of Fig. i4-2, the free-running irequency
of LM565 is determined by the timing components c2 and vRr, and can be
found by

n
" =
1-2
4 VRt C2

-
l-ock Range

the PLL is in already-iocked state and the vco is running at some

lntially,
fi-equency. lf the input requency/is away from the VCo frequency f,,locking
may stll occur. when the input frequency reaches a specific frequency where
the PLL loses lock, the frequency difference of I and f"is called the lock range
of the loop. The lock range of LM565 can be found by

a 8fro 8f.
L -- -
l/ VC! _ T./
LL

Capture Range

lnitially, the loop is unicckeo and the vco is running ai some freqierc., , :-3
input frequency f,s ciose to the VCO frequency ,, unlocking .:a,, ---=-
B.rhen the input frequency reaches a specific frequency where::e = _ :.:.s

i4-3
 IT
q
C
Unit 14 FSK Demodulators C
t
t
the frequency difference ol I and fois called the capture range oi the loop. The C
capture range of LM565 can be found by !
t
t
t
3.6x103 xC. t
e
ln the circuit of Fig. 4-2, components Re, Ro, Rs, C, C and C5 perform the t
low-pass filter to reduce the output ripple. The digital levels of FSK t
demodulated signal are compatible with TTL levels.
t
t
t
t
I
t
t
I
I
(
t
I
(
I
(

I
(
(

1n
+f I
I
iJnit 14 trSK Dernccie::'s

14.3 E QUiPlf EIIX REQ{IIRED

'1 - Module KL-92001

2 - Module KL-94003
3 - Oscilloscope

14.4 EXPERIMENTS AND RECORDS

Experiment 14-'! FSK Demodulator

l-11. Locate the ,l

FSK Demodulator circuit on Module KL-94003. Connect the
..'r(? ! --
verii.cal Input of oscilloscope to VCO output (T1). Observe the
r
t_lr'; i ': i l- i-. it.j: . ':- . ,-.
fre-iuhning frequency of LM 565 and Adjust VRr to obtain a frequency
o'n 1170 Hz.

!2. Connect a 1070H2, 2Vp-p sine wave to the input terrninal (l/P). Set
osciiloscope vertical input to DC range and observe the output
**'C#;; and record the result in Tabie 14-'1.
[3. Change the input frequency ts 1270ts,2 and repeat siep 2.

[4. Complete the FSK Modulator circuit on Module KL-94003. Apply a '15]
.-1 i-,ri:,1"tY'' li
t'
llzTTL quare wave to the input of FSK modulator.

15. Connect the output of FSK modulator to the input of FSK demoa'-tr:'
Using the oscilloscope, observe and record the demodula:e,: c-:!-:
waveform in Table 14-2. lt the demodulated signal is nc: cb:e -e:
check the input FSK frequencies 1070 Hz and 127AHz.

tr 6. Change -the input frequency of ,FSK modulatci :c 2lJ-= Se:

C,",", * 1' ,' ril
osciiloscope vertical input to D_C - rangc anc 3ose-' = :-e cL:iJi
waveform and record the result inTabte 14-2.
 Demodulators

Table 14-1

(V,=2Vp-p)

lnput
lnput Waveform Ouiput Waveform
Frequency

1O7O Hz

1274 Hz
 FSK Denodors

iable 14-2

FSK Modulator FSK Demodulaior FSK Demodulator

(Fig.'13-2) lnput
Frequency lnput Waveform Output Waveform

150 Hz

2Q0 Hz

14-7
Unit 14 FSK Demodulaio's

14.5 QTTESTIONS

rl/hat coniponents determine ihe free-running frequency of the VCO n

1M565 of Fig. 14-2?

2. What is the purpose of p,A741 in Fig. 14-2?

3. What is the function of LM565 pin 6?

4. What is the purpose of the multisiage low-pass fliter between ihe LM565
output and the comparator input?

1 +-8
 Fffi
vrxrt{eerc ffi
ASK SYSTEM
18.1 Objectives.. 1B-1
18.2 Discussion Of Fundamentais.. 1 8- 1

18.3 Equipments Required. .. 1 8- 1 '

18.4 Experiments And Records..... i8-''
Expeiment 1B-1 ASK MoCulator
Experiment 18-2 Noncoherent ASK Demodulator
Experiment 1B-3 Manchester CVSD Sysfem
Experiment 18-4 Coherent ASK Demodulator
18.5 Questions... 'a-2-
1E.1 OB]ITCTNES

1. To siudy the principles of ASK mociulation anci cjemcc-r a:.-

2. To inrpiemeni an ASK mcdulator.
3. To implenrent coherent and noi'lcoherent ASK democulaiors

18.2 DISC US SiON OF F{IND;LME}IIAj'S

it is
when it rs required to transmit digital data over a bandpass channel
with iixeC
necessary to modulaie the incoming data onto a carrier wave
frequencylimitsimposedbythechannel'Thedatamayrepresent
audio or
digital computer output or PCM waves generated by digitizing
video signals. The channel may be a telephone channel, microwave
radio link, or a satellite channel.

of a
Modulation is defineci as the process by which some characteristic
carrier is varied in accordance with a modulating wave. ln digital
cornmunications, the modulating wave consists of binary
data or an
encoded version of it. For the carrier, it is customary to use
a
l/-ary
sinusoidai wave. with a sinusoidal carrier. the feature that is used by

the mociuiator to distinguish one signal from another is a step change

in

the amplitude, frequency, or phase of the carrier. The result of this

modulation process is ampliiude-shift keying (ASK), frequency-shifi
keying (fSK), or phase-shift keying (PSK)' which may be viewed
as

special cases of arnplitude modulation, frequency modulation, and

phase modulation, resPecirvelY.

ASK Msdulatar

An ASK modulated signai can be expressed as

X51(t)=Ai cos ( t,;.t+@o) 0<t<T, i=l,2,...,M

where the ampiiiude Ai has M possible values, the anguiar

f:ec-e::' *-
.'!-e'= l s =-
and the phase S6 re ccnstant. lf M=2 (Ar=0 and Az=A

lC 1
i L'- I
 arbilrary constant), Xnsx(t) wil be a binarv ASK modulated signal
as
shown in Figure 1B-'1. The ASK signal transmits a binary message
which
is on when the modulating daia is a logic high and off when ihe
modulaiing signal is a rogic row. lt is also cailed on-off Keyrng (ooK)
mod"laiin.

Figure 1B-'l ASK modulated signal

Figure'18-2 shows an ASK modulator. The A represents a dc bas,

the
snusoidal carrier v6(t)=A6 cos2a fgt, and the modulating sigrral
Vp(t) is a
binary data. The modulated signar V1(t) can be expressed as

V(t) = [Vo(t) +A]Ac cos}rfst

The waveforms of Vo(i), [Vo(t) + A] and V1(t) are shown in Figure

1g_3.
clearly the ASK modulated signar V1(t) consists of two revers
[Vp(t)+y,-4"
and [vp(t)+vir]Ac corresponding to V and v of the modulating
signal
Vs(t), respectvely.

Vo(t
Vr (t)

l
Vc{t)

Fgure 18-2 Block diagram of ASK modulator

t8-2
,nii 18 AS( S', s:.i-

A digi'iai ommunicaiion system is 'eferred to as coer3:ti ' = --=

reference is availabie for ciemodulaiion thai is in phase \ir:- :-=
transmitiecj cari-ier (with fixed phase shifts due io transmission c: =, =
accounted fcr). Otherwise, it is referre,J to as noncoherent. Like,lls=
if a pei-iodic signa! js available at the receivei- ihat is synohroncus '.';l:-
the transmitted sequence of digiial stgnals (reei'red to as a clock) the
system is referred to as synchronous; if a signaling techniqr-re is
employed in which such a clock is unnecessary, the system is calieo
asynchronous.

{a) V"(t)

YD(t)+A

A+yE

A+Y L

(b) vo{t)+A
Yr(t)

lA+Yr j Ac

IA+VL]Ac

(c) Vr(t)

Figure 18-3 ASK mcdulator wareforms

1 -r
 J
f
ASK Demodulator I
I
ASK demociulation is a process ihat restores the digital modulating
signal fronr the ASK signal received. Figure 1B-4 shows the operation of I
ASK demcculaton.The elect;-onic cii-cuit thai pei-form ASK democjuition J
is called ASK demodulator. ASK demodulators can be caiegorized into J
iwo types: noncoherent and coherent demodulators. J
J
J
Jj
J

Figure 18-4 ASK dernodulation

A. Noncoferent ASK Demodulator

Figure 18-s shows the functionar brocks and waveforms

of a
noncohereni ASK demodulaior. The envelope detector
removes the
high-frequency carrier and blocks the negatve half
of the received ASK
signal vp. The output of the enverope detector, vE,
is therefore the
positive envelope prus dc and sawtooth components.
The dc component
s blocked by ac-coupring and the high-frequency
sawiooth component is
rejected by the lowpass fifter.

The voltage comparator compares the LpF output vrp(0

with a fixed
threshold voltage and produces the digitar output signar
ve esuar to the
original modulating signal. .:

18-4
 r:.i Siste-

Figure 1 8-5 Block diagram of noncoherent ASK demoduiator

Figure '18-6 Block diagram of cchereni ASK demodulator

I --r
 B. Coherent ASK Dernodulator

Figure 18-6 shows the block diagram of coherent ASK demodulaior

The receved ASK signal Vp(t) is equal io the transmiited ASK signai

Vn(t) = Vr(Q = lvo(t) +A lAp cos2 zf6t C

t
C
The carrier signal vLo(t) is recovered by the carrier recovery circuit from
the Vq(t).
I
C
VLo(t) = 46 cos(2 z f6t +O)
I
lI
;
when the received ASK sgnal V(t), and the reconstructed carrier signal lI
vLo(t) are connected to the inputs of the multiplier, the multipler output t
becomes t
t!
Vx( = Vo(t) + AIAR ALo cos? tr f6t cos(2 zr f6t +<D) ;
= [(AAn ALdlZ]. cosQ + [(An ALdtzJ. cos<DVp(t) + t
[Vo(t) +A] '[(An ALdlzl 'cos(2 tr2f6t+Q) t
C
The first term of the equation is a dc component, the second term the !
modulating digital signal, and the third term is the ASK signal with a rl
frequency of Zfc, twice the carrier frequency. The dc component is t
blocked by ac-coupling and the high-frequency sawtooth component is
t
lr
rejected by the lowpass filter.
t
The voitage comparator compares the LpF output VLp(t) with a fixed
!
It
threshold voltage and produces the digital output signal ve eQual to the
original modulating signal.
t
;

;
;
;
I
d
d
{
1 8-6 q
T
 iSr Srstein

Practicai Clrcuit Description

1. ASK Moduiator
The praciicaiASK modulator is shown in Figure 1B-7. The muliipliei
peroriris the functior-i of ASK mod..iatjon.

r, ,l\
\' '
\J,'Vrl
vD Sgnal n

./l j i ,.

!'t/i VC Carrer in
--->?r"' .-' ,-,, / -.',
-,.-'

?' 'i
I --!

'j.i''

Figure 18-7 ASK modulator

The muliiplier output V(t) is expressed as

! ',7
'l
;., -''

vo(t)Yc(t)
vr(t) = +o'vc(t)
10

The avaiue is divided by VR1 potentiomeiei'. lf the ci-ii-

V5{t)=A6 cos2ii fct, Vr(t) becomes
-,
-,
-, Vr(t) : [ _I Vo(t) + a ]Accos2nfct

I
'10

I
D (1) The digital modulating signalV(t) has two voltage levels: Vu = 5V
and VL = 0V.
Vr(t)
?
-
lf V(t)= Vr = 5V then
lf Vrlt= VL = 0V then V(t)
= (0.5+ a ) Ac cos2 n f sl
e Accos2
? {2)
=
ASK modulated signal Vr{r) has iwo cjiscreie voiiages. the (0.5+
f ct

t,
-
L,
s)Ac reptesents a high and ihe other ( e Ac) represents a low.
(r) lf q,=0, two,oltage levels of V(t) are 0.5A6 and 0. fhis is also

tt cailed an On-Of Keying (OOK) modulatjon.

tr
ta
E I 8-7

E
 .-:,'-.r3 ASK Sisi:-

2. ASK Demoduiator
A. Noncoherent ASK Cemcdulator is shown in Figure '18-B

VD Sagna in AD633

x2 t1t

Y2

ln

|az z
I
rwr
LI
'f (
RE(
1oK (

Figure 1B-B Noncoherent ASK demodulator

,i
(1) Multiplier(1) operates as an ASK modulator.
),/\
I

,'{2) Envelope detecior biocks ihe negative half of vp in signal and

1
--1 ----
ii\,
-,
- ii
r- '
deiects the positive half.
(3) Lowpass filter (LPF) rejects the sawtooth component of Vg out
i tii- t i. '. \--

signal. The dc component of VE out signai is blocked by the

coupling capacitor c2 when the signal is connected to the
ln(ac) terminal.
{4) comparator shapes the LPF output signal (Vp out) to a digital
signal with two voltage levels 0V and 5V.

B. Coherent ASK demodulator is shown in Figure '18*g.

1 8-8
-i,,,ti ASK S js:=-r-

)*
?,"
=
R8.
10r< '

PLL T
COmP i
VCO ot

Flgure 18-9 CoherentASK demodulator

(1) Multipiier(1) opei'atcs as the ASi( moduaior that ccrrveris the

digital modulating signal into an ASK modulated signal
(2) Phase-Locked Loop (PLL) and bandpass filier (BPF) construct
a carrier recovery circuit which reconstructs the carrier signal.
The frequency of the recovered carrier signal on Vs out
terminal is equal to the original carrier in transnritter. The
phase can be synchronized to the originai carrier by turning
the potentiometer VRS.
(3) Multiplier(2) performs the multiplication of ihe received ASK
signal and ihe recovered carrier signal.
\+i Lowpass filter' {LPF) is used to reject the high-irequency
components of Multiplier(2) output signal (Vx out). The dc
component is blocked by the ac-ccupling capacitor C2.
(5) Comparaior cornpares the Vp out signal with gi'ound potentlai
and reccvei's the originai moduiaiinE lr.:nai.

1 8-9
 .S { S ;s::Ti

;'=(L-940C5 module shown in Figure 1B-1C conssts

of ASK modulaior, noncone;-3n: AS(
cemcduiaior, and coherentASK demodulaior.

.4 SK *iodulaor/emad ulolor

x1 w J lll
x2 i'1
Yl L] l2

12s z
o)
roox

JI,
t-i
It

\/R?

I
lt Rs R6
5
2.711 uI *r*,1
,11&' ,*o1
ee I
'0-lu i5ox lr--

ffi-d
RA

uf-l !=!
10x
-l
F?,
br
Ir ,,, -----r I
wsl "- I

EYep OEdtr
r-
t rf]55
J1 _ 3,, ge$
- ri5 -;-_ I

d--t
t-J
v84

+5v+?2V Gy -12V
oooo

Figure 18-10 KL-94005 module

18- 10
Unit 1E
ASK System

18.3 EQUTPITENT REOUTRED

"l - Module KL-92001

2 - Moiiule KL-94005
3 - Cscilloscope

18.4 E}(PERIMENTS AND RECORDS

Experiment 18-1 ASK lWodulator

1. Locate the ASK rnodulator circuit shown in Figure 1&7 or the

KL-94005 module.

2, Connect a SC0KHz, 4Vpp sinewave to the VC Carrier in terminai_

3. connect a 2aKH4 TTl-level square wave from Function crererator

TTI-/CMOS out to the VD Signal in terrnnal_

4. Turn the VR1 fully CW to obtain a maximurn amplitude of ASK

modulated signal on VT out. iVleasure and record the ASK r:ai
waveform in Table'!8-1.

5. Turn the VR1 fully CCW to obtain a minirnurn amplitude of ASK

modulaied signal on ihe VT out. Measure and record the ASK ssnal
waveform in Table 18-'i.

6. Connect a 1KHz, TTl-level square wave from Function Generator

TTL/CMOS out to the VD Signal in terminat.

7. Repeat steps 4 and5.

8. connect a 10KHz, TTl-levei square wave from Function Generatoi'

TTLiCMOS out to the VD Signai in terminal.

18-11
 ASi., Si s:3-

9. Repeat steps 4 and 5

10. Connect a 50KHz, TTl-level square urave from Funciion Geneiai:,'
TTL/Cl/lOS out to the VD Signai in terminai.

1'1. Repeai steps 4 and 5.
I

Cr

I

I
rl



I
F
F
F


(!

I

t!
rl
I
I

tr

I

I
t!
I
;
r!
;
18-i2
a
: l;i ll ASK System

Experirnent 18-2 Noncohererf.ASK Democulalor

1. Complete the noncohei-eni ASK demociulaior shown in Figure 1B-B by

placing ihe jumpei-s in positions 2 6, and B.

2. Connect a 500KHz, 4Vpp sinewave ic VC Carrier in terminal.

a
J, Connect a ZOKHz, TTl-ievel square wave from Function Generator
TTL/CMOS out io VD Signal in terminal.

Turn VR1 fully CW to set maximum amplitude on VT oui terminal.

Measure and .record the waveforms on terminals VT out, VE out, VLF
out, and Vo out in Table 1B-2.

Connect a 1KHz, TTL-ie'el square wave from Function Generator

TTUCMOS out to VD Signal !n terminal.

b. Repeat step 4.

7 Connect a 10KHz, TTl-level square ',nrave from Function Generator

TTL"/CMOS out io VD Sgnal in terminal.

8. Repeat step 4.

9. Connect a 50KHz, TTl-level square wave from Function Geneia:cr

TTUCMOS out to VD Signal in terminal.

10. Repeat step 4.

11. Compare the waveforms on VD Signai in and Vo out terminals ancj

wriie down your comment.

I C- 1-.
 -:.: ASK Systen:

Experiment 18-3 "4S Sysfem witlz Manchester CVSD

1. Assemble KL-94004 and KL-94005 modules as shown in Figure

'18-10.

Figu;: 18-10 combines the experiments of CVSD, Manchester ASK

modulation and demoduiation.

Manchester
Muliiplier {1)
Encoder

C!-K-out CLK-in

Figure 18-10 ASK system connections

2. Place jumpers in positions '1, 3, 5, 7, and 8 on Module KL-94004.

Place jumpers in positions 2, 6, and 8 on Module KL-94005.

? Connect the ME-out terminal on KL-94004 to the VD Signal in

terminal on KL-94005.

4. Connect the Vo out terminal on KL-94005 to the MDD-in terminal on

KL-94004.

5. Connect a 500KHz, 4Vpp sinewave to VC Carrier in terminal on

KL-94005 Module.

ib-14
Unit 13 .SK Slsie.r:-r

6. Ti-irn on the power.

7. Turn the potentiomerer V,R'l on KL-94004 clock gener-ai:-

obtain a 90KHz clcck signal on CLK out terminal.

Connect a 1KHz, lVpp sine,+rave to the A-jn termina

KL-94004

9. Tr-rrn the VR1 on KL-94005 Mirltiplier(i) fL;tiy CW

10. il/easure and record ihe waveforms at the test points 1:s:=*
d 4
I O-J

11. Connect a 3KHz, lVpp sinewave to the A-in terminal 3r '.r::_

KL-94004

12. Repeat step 10.

13. Connect a 20A#2, lVpp sinewave to the A-in tei-minal c.: ,,::-:
KL-94004

'14. Repeat step 10

1rq- 1 i
 I

-T
I ASK Svsiem r{
_..-- 1

r{
r{
al
Experiment 18-4 Cof'tercnt ASK Dernadulator
d
l
Compiete the cohereni ASK demodulator shown in Figure 1B-9 by
al
placing the jumpe;'s in positions 1, 3, 4,7,8,9, 10, and 11
c

2. Connect a 500KHz, 4Vpp sinewave to VC Carrier in terminal.
d
'
3. Connect a ZOKl1z, TTl-level square wave from Function Generator
TTL/CMOS out to VD Signal in terminal.
I
l
4. Turn VR1 fully CW to obiain the maximum amplitude on VT out
terminal. The VT out waveform is an ASK modulated wave. tI
5. Turn VR4 to make the VCO OUT signal frequency equal to the carrier t
frequency 500KHz.

6. Turn VR5 to make the signals on VLO out and VT out in phase. rl

7. furn VR2 to obtain maximum signal amplitude on Vx out.

8. Turn VR3 to obtain a SVpp signal on VLP oui.


Measure and record the signal waveforms on terminals VT out, Vx out, (
VSO in, VLP out, and Vo out in Table 18-4. (

10. Connect a 1KHz, TTl-level square wave from Func{ion Generator
TTUCMOS out to VD Signal in terminal.
I


1 1. Repeat steps 6 through 9.
I
12. Connect a 1OKHz, TTl-level square wave from Function Generator
TTUCMOS out to VD Signal in terminal.

13. Repeat steps 6 through 9. I
d
I
-
.'i
i8-16 d

Unit 't 8
ASX Svste-n

1'
l-- Connect a 50KHz, TTI--level square wave ;-om Function Genera:::
TTL/CMOS oui to VD Signal in terminal.

4E, Repeai steps 6 through 9.

16. Conipare the waveforms on Vo out and VD Signal in terminals and

write down your commeni.

lo 1i
1,f-1,'
 Table-lB-i ASK modulator (VC Carrier in =500KHz,4Vpp

VD Signal in VT oui Waveform VT out Wavefo;'m

(TTL level) (VRl iully C\i) (VR1 fully CCV\|

20KHz

lKHz

10KHz

(

(

(
50KHz
(r




(
I




Unii 18

Table 18-2 hioncoherent ASK iemoduiator

(VC Carrier in=500KHz,4VPP)

VD Signal in VT out VE oirt I VLP orit I Vo out

(TTi- level) v-Vaveiorm Wav--frmiWavefoi-ml\iVaveform

i8-19
 -
ASK S.vsiar: c
c
Table 1B-3 ASK system wiih Manchester CVSD
(VC Carrier in = 500KHz, 4Vpp)
Output A-in (1Vpp sinewave)
Waveform lKHz 3KHz 2A0Hz

KL-94004
ME-out I

I
KL-94005
VT out I

I
KL-94005
VE out

{
KL-94005

VLP out
I

KL-94005

Vo out

(
(
KL-g4004 (
MDD-out

I

KL-94004 (
MDCLK-out

I(
KL-94004
DMA-out (

I
I
I
1 8-20 I
!
FD
lt,
,
,
F
D Table 1B-4 Coherent ASK demoduiaio-
E, (VC Carrier in = S00KHz, tVpp)
E VD Signai in I Vf out Vx out VSC in VLP oui
t TTL level) J Waveform Wa'eform Waveforrn i/,/aveform
i

rr
I'
I
I'
I
I'
a,
I'
I
-
,,
,,
.D
a,
.)
,,

It
'
r,
a
,
t
t
I
,
)
)
)
)
)
,
)
,
t
)
,
l
)
)
Unli i 8 ASK Systerr

18.5 QUESTIOhTS

i. ls the waveform on VT out terminal an ASK modulated signal?

2. ls the waveform on VT out terminai an OOK modulated signal?

3. Describe the function of PLL circuit.

4. Describe the function o bandpass filter.




(
5. Why the signals on VLO out and VT out terminals must be in pitase?
{

{


6. Discuss the relationship between Vx out and VLP out signals.

(


(
7. Describe the function of comparator. (





18-22
I
d,]