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ARCHITECTURE AND
ORGANIZATION
ECEG -3143
Guide Book
FACULTY OF TECHNOLOGY
Department of Electrical & Computer Engineering
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Contents
CHAPTER 01..............................................................................................................................................1
[FUNDAMENTAL CONCEPTS OF COMPUTER ORGANIZATION & ARCHITECTURE]........................................1
Chapter Description.................................................................................................................................1
1.1 Introduction.................................................................................................................................1
1.1.1. Organization and Architecture.............................................................................................1
1.1.2. Structure and Function..............................................................................................................2
1.2 Computer Evolution and Performance...............................................................................................4
1.2.1. Brief History of Computers........................................................................................................4
1.2.2. Measuring Performance............................................................................................................5
1.2.3. Performance Improvement Techniques.....................................................................................6
CHAPTER 02..............................................................................................................................................8
[A TOP LEVEL VIEW OF COMPUTER]............................................................................................................8
Chapter Description.................................................................................................................................8
2.1. Computer Components....................................................................................................................8
Program Concept.................................................................................................................................8
What is a program?..............................................................................................................................8
Function of Control Unit......................................................................................................................8
Components........................................................................................................................................8
Computer Components: Top Level View..............................................................................................8
Some basic registers inside CPU..........................................................................................................9
2.2. Computer Function...........................................................................................................................9
Instruction Cycle..................................................................................................................................9
Example of Program Execution..........................................................................................................10
Instruction Cycle State Diagram.........................................................................................................12
Interrupts...........................................................................................................................................12
Interrupts Cycle.................................................................................................................................12
Transfer of Control via Interrupts.......................................................................................................13
Instruction Cycle with Interrupts.......................................................................................................13
Instruction Cycle (with Interrupts) - State Diagram............................................................................13
2.3. Interconnection Structures.............................................................................................................14
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Computer Modules............................................................................................................................14
Memory Connection..........................................................................................................................14
Input/Output Connection..................................................................................................................15
CPU Connection.................................................................................................................................15
2.4. Bus Interconnection........................................................................................................................15
What is a Bus?...................................................................................................................................15
Bus Interconnection Scheme.............................................................................................................16
Bus Types...........................................................................................................................................16
Bus Arbitration...................................................................................................................................17
Centralised or Distributed Arbitration...............................................................................................17
CHAPTER 03............................................................................................................................................18
[COMPUTER ARTHIMETICS AND NUMBERING SYSTEMS]..........................................................................18
Chapter Description...............................................................................................................................18
3.1. Arithmetic and Logic unit (ALU)......................................................................................................18
3.2. Integer Representation...................................................................................................................18
Sign-Magnitude.................................................................................................................................18
Twos Compliment.............................................................................................................................19
Conversion Between different bit Lengths.........................................................................................20
3.3. Integer Arithmetic...........................................................................................................................20
Addition and Subtraction...................................................................................................................20
Multiplication....................................................................................................................................21
Division..............................................................................................................................................24
3.4. Floating Point Representation.........................................................................................................26
Real Numbers....................................................................................................................................26
IEEE Standard for Binary Floating-Point Representation....................................................................28
3.5. Floating Point Arithmetic................................................................................................................28
FP Arithmetic +/-................................................................................................................................28
FP Arithmetic x/...............................................................................................................................29
CHAPTER 04............................................................................................................................................32
[INSTRUCTION SETS AND ADDRESSING MODES].......................................................................................32
Chapter Description...............................................................................................................................32
4.1 Instruction sets.................................................................................................................................32
4.1.1 Introduction..............................................................................................................................32
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4.1.2 Instruction Format....................................................................................................................33
4.1.3 Instruction Types.......................................................................................................................34
4.2 Addressing modes............................................................................................................................38
4.2.1 Immediate addressing modes....................................................................................................39
4.2.2 Direct addressing modes...........................................................................................................39
4.2.3 Register addressing modes........................................................................................................39
4.2.4 Register indirect addressing modes...........................................................................................39
4.2.5 Displacement addressing modes...............................................................................................40
4.2.6 Stack addressing modes............................................................................................................40
x86 addressing modes.......................................................................................................................40
CHAPTER 05............................................................................................................................................42
[PROCESSOR ORGANIZATION & INSTRUCTION CYCLE]..............................................................................42
Chapter description...............................................................................................................................42
5.1 Processor organization.....................................................................................................................42
5.2 Register Organizations.....................................................................................................................43
Types of registers...............................................................................................................................43
5.3 Instruction cycle and Pipeline..........................................................................................................44
Instruction cycle.................................................................................................................................44
Instruction Pipelining.........................................................................................................................44
CHAPTER 06............................................................................................................................................49
[COMPUTER MEMORY].............................................................................................................................49
6.1 Computer Memory System Overview........................................................................................49
6.2 Cache Memory...........................................................................................................................50
CHAPTER 7..............................................................................................................................................53
[Input/output]............................................................................................................................................53
7.1 EXTERNAL DEVICES...................................................................................................................53
7.2 I/O MODULES...............................................................................................................................53
7.2.1 I /O steps...................................................................................................................................54
7.3 I /O techniques.................................................................................................................................54
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Table of Figure
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5
CHAPTER 01
[FUNDAMENTAL CONCEPTS OF COMPUTER
ORGANIZATION & ARCHITECTURE]
Chapter Description
Chapter 1 introduces the concept of the computer as a hierarchical system. A computer can be viewed as
a structure of components and its function described in terms of the collective function of its
cooperating components. Each component, in turn, can be described in terms of its internal structure
and function. The major levels of this hierarchical view are introduced.
The chapter also discusses about the history of computers, Measuring Computer performance and
techniques used to improve computer performance.
1.1 Introduction
Brain storming
This course is about the structure and function of computers. Its purpose is to present, as clearly and
completely as possible, the nature and characteristics of modern-day computers. This task is a
challenging one for two reasons.
First, there are various devices that are considered as computers. These devices (computers)
exhibit variety in cost, size, performance, application.
Second, the rapid pace of change that has always characterized computer technology continues
with no letup.
In spite of the variety and pace of change in the computer field, certain fundamental concepts apply
consistently throughout.
The intent of this course is to provide a complete discussion of the fundamentals of computer
organization and architecture and to relate these to contemporary computer design issues.
Computer organization refers to the operational units and their interconnections that realize the
architectural specifications.
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Organizational attributes include those hardware details transparent to the programmer, such as
control signals,
interfaces between the computer and peripherals, and
The memory technology used.
Historically, and still today, the distinction between architecture and organization has been an important
one.
This Course examines both computer organization and computer architecture. The emphasis is perhaps
more on the side of organization.
The hierarchical nature of complex systems is essential to both their design and their description. The
designer need only deal with a particular level of the system at a time. At each level, the system consists
of a set of components and their interrelationships. At each level, the designer is concerned with
structure and function:
The computer system will be described from the top down. We begin with the major components of a
computer, describing their structure and function, and proceed to successively lower layers of the
hierarchy.
Function
In general terms, there are only four basic functions that a computer can perform:
Data processing
Data storage
Data movement
Control
Structure
Figure 1.1 is the simplest possible depiction of a computer.
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Figure 1.1 the Computer
But of greater concern in this course is the internal structure of the computer itself, which is shown in
Figure 1.2.
The most interesting and in some ways the most complex component is the CPU. Its major structural
components are as follows:
Control Unit
Arithmetic and Logic Unit (ALU)
Registers
CPU interconnection
Each of these components will be also examined in some detail in chapter five Processor structure and
function.
Finally, there are several approaches to the implementation of the control unit, one common approach is
a microprogrammed implementation. With this approach, the structure of the control unit can be
depicted, as in Figure 1.2.This structure will be examined in Chapter 8.
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Figure 1.2 the computer top-level structure
There are totally five computer generations known till date. Each generation has been discussed in detail
along with their time period and characteristics. Here approximate dates against each generations have
been mentioned which are normally accepted.
First Generation
Second Generation
Third Generations
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Fourth Generations
Fifth Generation
Average number of clock cycles per instruction for a program is called clock cycle per instruction (CPI).
CPU execution time: Total time a CPU spends computing on a given task (excludes time for I/O or
running other programs). This is also referred to as simply CPU time.
Response time: Total time to complete a task, including time spent executing on the CPU, accessing disk
and memory, waiting for I/O and other processes, and operating system overhead.
To improve performance:
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Reduce response time
Increase throughput
Cache
Multiple cores
Pipelining:
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Decode Unit determines type of instruction.
Multiple core:
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CHAPTER 02
[A TOP LEVEL VIEW OF COMPUTER]
Chapter Description
This Chapter provides a brief examination of the computers components and their input-output
requirements. And it looks at key issues that affect interconnection design, especially the need to
support interrupts.
General purpose hardware can do different tasks, given correct control signals
What is a program?
A sequence of steps
A hardware segment accepts the code and issues the control signals
Components
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results out
Input/output
Main memory
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Figure 2.1 Computer components: Top level view
Fetch
Execute
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Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch
Increment PC
Execute Cycle
Processor-memory
Processor I/O
Data processing
Control
e.g. jump
Combination of above
Figure 2.3 illustrates a partial program execution, showing the relevant portions of memory and
processor registers. The program fragment shown adds the contents of the memory word at address 940
to the contents of the memory word at address 941 and stores the result in the latter location.
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Figure 2.3 Example of Program Execution (contents of memory and registers in hexadecimal)
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Instruction Cycle State Diagram
Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
Program
Timer
I/O
Hardware failure
Interrupts Cycle
Added to instruction cycle
If interrupt pending:
Save context
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Process interrupt
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2.3. Interconnection Structures
A computer consists of a set of components or modules of three basic types (processor, memory,
I/O) that communicate with each other. In effect, a computer is a network of basic modules.
Thus, there must be paths for connecting the modules.
The collection of paths connecting the various modules is called the interconnection structure.
Different type of connection for different type of unit
o Memory
o Input/Output
o CPU
Computer Modules
Figure 2.8 suggests the types of exchanges that are needed by indicating the major forms of input and
output for each module type:
Memory Connection
Receives and sends data
Read
Write
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Input/Output Connection
Similar to memory from Proccessers viewpoint
Output
Input
CPU Connection
Reads instruction and data
Usually broadcast
Often grouped
Data Bus
Carries data
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Remember that there is no difference between data and instruction at this level
Address bus
Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus
Control and timing information
Bus request/grant
Interrupt request
Clock signals
Bus Types
Dedicated
Multiplexed
Shared lines
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Disadvantages
Reduction performance
Bus Arbitration
More than one module controlling the bus
Bus Controller
Arbiter
Distributed
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CHAPTER 03
[COMPUTER ARTHIMETICS AND NUMBERING SYSTEMS]
Chapter Description
This chapter examines the functionality of the arithmetic and logic unit (ALU) and focuses on the
representation of numbers and techniques for implementing arithmetic operations. Processors typically
support two types of arithmetic: integer, or fixed point, and floating point. For both cases, the chapter
first examines the representation of numbers and then discusses arithmetic operations.
Handles integers
e.g. 41=00101001
No minus sign
No period
Sign-Magnitude
Twos compliment
Sign-Magnitude
Left most bit is sign bit
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0 means positive
1 means negative
+18 = 00010010
-18 = 10010010
Problems
Twos Compliment
+3 = 00000011
+2 = 00000010
+1 = 00000001
+0 = 00000000
-1 = 11111111
-2 = 11111110
-3 = 11111101
Benefits
One representation of zero
3 = 00000011
Add 1 to LSB +1
Result 1 00000000
-0=0
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Negation Special Case 2
-128 = 10000000
Add 1 to LSB +1
Result 10000000
So:
-(-128) = -128 X
Range of Numbers
8 bit 2s compliment
+127 = 01111111 = 27 -1
16 bit 2s compliment
+18 = 00010010
-18 = 11101110
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Take twos compliment of substahend and add to minuend
i.e. a - b = a + (-b)
Overflow rule
If two numbers are added, and they are both positive or both negative, then overflow occurs if and only
if the result has the opposite sign.
Multiplication
Complex
Example:
1011 Multiplicand (11 dec)
21
1011 otherwise zero
Execution of Example
M multiplicand Q multiplier
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Hardware implementation of Unsigned Binary Multiplication
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Booths Algorithm
Division
More complex than multiplication
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Flowchart for Unsigned Binary Division
Load the divisor into the M register and the dividend into the A,Q registers.
If M and A have the same signs, perform A-M else perform A+M
The preceding operation is successful if the sign of A is the same as before, after the operation,
* if the operation is successful or A = 0, then set Q 0 = 1
* if the operation is unsuccessful and A is = not 0 then set Q 0 = 0 and restore the previous value of A.
The remainder is in A. If the signs of the divisor and dividend is the same, then the quotient is Q, else it
is the twos complement of Q.
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3.4. Floating Point Representation
Real Numbers
Numbers with fractions
Fixed?
Very limited
Moving?
Floating Point
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Signs for Floating Point
Normalization
(c.f. Scientific notation where numbers are normalized to give a single digit before the decimal point
Accuracy
Accuracy
For comparison, Figure 3.6 indicates the range of numbers that can be represented in a 32-bit word.
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Figure 3.6 Expressible Numbers in Typical 32-Bit Formats
Normalize result
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FP Addition & Subtraction Flowchart
FP Arithmetic x/
Check for zero
Add/subtract exponents
Normalize
Round
29
Floating Point Multiplication Flowchart
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Floating Point Division Flowchart
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CHAPTER 04
[INSTRUCTION SETS AND ADDRESSING MODES]
Chapter Description
From a programmer point of view, the best way to understand the operation of a processor is to learn
the machine instruction set that it executes. So in this chapter we will study this instruction sets.
Architectural issues such as instruction set design and data types are covered.
4.1.1 Introduction
Instructions?
Instruction set
Elements of an Instruction
ADD,SUB,MUL,,,,,,,,,
Addresses (operands)
May include:
Instructions to be read by a computer contain strings of 1s and 0s (They are numbers) (Machine
instructions)
Symbolic representations of machine instructions are used for convenience (assembly language)
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Even more convenient (High-level languages)
void main()
{
Compiler Assembler main:
int a,b,c; 0567
ADD c,a,b
c = a+b;
High-level}language Assembly language Machine language
Defines the layout of the bits of an instruction in terms of its constituent fields (What does each field
represent and how many bits is it?)
1. Zero operand:
Opcode
2. One operand:
Opcode Address
3. Two operands:
4. Three operands:
Instruction Representation
In machine code each instruction has a unique bit pattern
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e.g. ADD, SUB, LOAD
Opcodes are represented by abbreviations, called mnemonics that indicate the operation.
Common examples include
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
ADD A,B
Number of Addresses
One of the traditional ways of describing processor architecture is in terms of the number of addresses
contained in each instruction
Arithmetic
Logical
Input/output
System control
Data transfer
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MOV destination, source
PUSH source
POP destination
Arithmetic
(E.g. ADD, INC, SUB, DEC, MUL, DIV)
DEC destination
MUL source
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E.g. MUL BL (AXAL x BL)
Logical
Operate on a bit-by-bit basis
Input /output
Instructions to read data from an input module and to write data to an output module
Transfer of control
Transfer of control instructions change the sequence of execution (update value of the program
counter (PC))
Jump instructions
There are two types of jump, unconditional and conditional in unconditional jump, as the instruction is
executed, the jump always takes place to change the execution sequence.
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Unconditional jump
In unconditional jump, as the instruction is executed, the jump always takes place to change the execution
sequence
Conditional jump
JZ label
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Figure 4.2 Conditional jump program sequence.
RET instruction must be included at the end of the subroutine to initiate the return
Immediate
Direct
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Register
Register indirect
Displacement
Stack
The operand is part of the instruction instead of the contents of a register or a Memory location
Advantage
Drawback
Drawback
Can address a limited number of memory locations (relatively smaller address space)
Register Address
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Most common addressing mode in most computers
Memory Address
Advantage
Can address larger number of memory locations compared with direct addressing
Main memory address is added with a displacement value to get the effective address in memory E.g.
MOV R1, [R2+100]
Displacement value
E.g. PUSH R1
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x86 addressing modes
Register, Immediate
Direct
Register Indirect
Displacement
Indexed
Based
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CHAPTER 05
Interpret (decode)
Decoding circuit Instruction
CPU contains:
Registers
ALU
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Control Unit
Internal Bus
User-visible registers
They can be directly accessed (read or written to) by programmers (instructions)
Control registers
Used by control unit to control operation of the processor
Data registers
Hold only data
Address registers
Only used for addressing
Stack pointer
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Control registers
Program Counter (PC): Contains address of next instruction to be fetched
Instruction Register (IR): Temporarily holds most recently fetched instruction
Memory Address Register (MAR): Specifies the address in memory of the word to be written
from or read into the MBR
Memory Buffer Register (MBR): Contains a word to be stored in memory or is used to receive a
word from memory
Status registers
e.g. Flag register (x86), CPSR(ARM)
Carry flag (CF), Zero flag (ZF), Sign flag (SF), Interrupt flag (IF), Overflow flag (OF)
Used by branch (jump) instructions and interrupts (CPU checks the appropriate flags when a
conditional branch instruction is encountered or when interrupt is enabled)
Fetch: Read the next instruction from memory into the processor.
Execute: Interpret the opcode and perform the indicated operation.
Interrupt: If interrupts are enabled and an interrupt has occurred, save the current process state
and service the interrupt.
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Instruction Pipelining
Review
Executiontime for a program=no .of instructions CPI clock period
Where CPI: Average clock cycle per instruction
e.g. Suppose a program has 10 instructions with the following relationship between instructions and
clock cycles required to execute each instruction
Pipelining
Instruction cycle has several stages (fetch, decode, execute)
Let instructions execute one after the other
(assume one clock cycle per stage (3 clock cycles per instruction) )
Clk
Additional hardware is required for a pipelined processor (pipeline registers between the stages)
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In practice the three stages may take different times (clock cycles): execution may take more
time than decoding. This would reduce the effectiveness of the pipeline
5-stage Pipeline
Assume:
46
Assuming one clock cycle per stage, 3 instructions would require 7 clock cycles
Pipeline Performance
Assume an instruction goes through k stages and each stage has a duration of
With pipelining
T k ,n=( k + ( n1 ) )
T =5 10=50
T k ,n=( 5+ ( 101 ) ) =14
50
Speed up factor of =3.57
14
With pipelining the program is executed 3.57 times faster than without pipelining
T nk
Speed up factor (S k )= =
T k , n k + ( n1 )
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Pipeline Hazards
Some things could go wrong on real pipelined executions
A pipeline hazard occurs when the pipeline, or some portion of the pipeline, must stall (be idle)
because conditions do not permit continued execution
Pipeline hazards:
Data hazards
Control hazards
Resource Hazards
Occur when two or more instructions that are already in the pipeline need the same resource
o e.g. Memory access
Data Hazards
Occur when one instruction depends on data value produced by a preceding instruction
o e.g.
ADD R1,R2 (R1=1)
ADD R3,R1 (R3=3)
Such hazard is termed as read after write (RAW) hazard since current instruction must wait to
read data until after a previous instruction writes the correct data
The hazard occurs if read takes place before the write operation is complete
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Other types of data hazards:
Write after read (WAR)
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CHAPTER 06
[COMPUTER MEMORY]
6.1 Computer Memory System Overview
Memory is used to store data and instructions in computers.
There are different types of memory within a computer: registers, cache, and main memory
(Primary memory), secondary memory (external memory).A computer may have all or a subset of these
memory types.
The different types of memories can be characterized by their speed, cost per bit and Capacity.
Speed: How fast can data be accessed from the memory. This is defined by the memory access time
(latency). Access time is the time from the instant that an address is presented to the memory to the
instant that data have been stored or made available for use.
The above characteristics for a certain memory type depend on the technology used to manufacture the
memory. The technologies used to manufacture the memory types mentioned above and their
characteristics is summarized below.
DRAM is made up of transistors and capacitors (1 transistor and 1 capacitor per bit)
Secondary Memory: Different types (Flash memory, magnetic disks like a hard disk, optical disks like a
CD-ROM)
They are used when large amount of data have to be stored (also when frequent access is not necessary)
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We want to have fast memory with big capacity. But as you can see, as the speed for a certain memory
type increases the price also increases. Having 100s of Gigabytes of the fastest memory only will be very
expensive. Therefore a hierarchy of different types of memory is used in computers.
Use a small array of SRAM (cache), larger DRAM (main memory) and even larger secondary memory to
fulfill the need for speed and capacity with a reasonable cost.
Secondary memory permanently holds programs and data used by the computer (it is non-volatile).
Main memory holds instructions for current programs run by the computer (it is volatile).
Cache holds a copy of portion of main memory most recently accessed by the computer. Since, according
to the principle of locality of reference, the most recently accessed memory location tend to be accessed
again soon, keeping this data in faster memory (cache) decreases the average memory access time.
The principle of locality of reference states that, if a data location is referenced, then the same location
or data locations with nearby addresses will tend to be referenced soon. This arises from natural
program structures. For example most programs contain loops, so instructions and data are likely to be
accessed repeatedly.
A processor may have a single cache or multiple levels of cache. Also there may be separate instruction
and data cache (called split caches), or a single cache to hold both instruction and data (called unified
cache).
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Fig: cache memory
When the CPU attempts to read a word from memory, a check is made to determine if the word is in
cache. If so, the word is delivered to the processor (this is called a Hit). If the data is not in cache (this is
called a Miss), a block of memory (several memory words) consisting of that data is read into the cache
and then the required word is delivered to the CPU.
Let the main memory of a computer contain 2n addressable words, with each word having a unique n-bit
address. This memory can be divided into blocks, each block containing a number of addressable words.
Let K = the number of words per block. This implies that there are 2 n/K = M blocks in main memory as
shown in the following diagram.
A cache memory consists of multiple tag/block pairs called cache lines. Let us assume a cache has L lines.
The cache structure is shown below.
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Each cache line contains control bits, a tag field used in addressing, and a block of memory data.
The number of cache lines is considerably less than the number of main memory blocks
(L<<M). At any time, some subset of the blocks of memory resides in lines in the cache. If a word in a
block of memory is read, that block is transferred to one of the lines of the cache.
Because there are more blocks than lines, an individual line cannot be uniquely and permanently
dedicated to a particular block. Thus, each line includes a tag that identifies which particular block is
currently being stored. The tag is usually a portion of the main memory address.
Memory (main memory) address is specified in instructions. A processor has to know where in cache to
look for a certain data, given the memory address. Therefore, the memory address specified in
instructions has to be translated into cache line number. This translation of memory address into a cache
line is termed as mapping.
Direct Mapping,
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CHAPTER 7
[Input/output]
In addition to the processor and a set of memory modules, the third key element of a computer system
is a set of I/O modules. Each module interfaces to the system bus or central switch and controls one or
more peripheral devices.
An external device connected to an I/O module is often referred to as a peripheral device or, simply, a
peripheral.
The major functions or requirements for an I/O module fall into the following categories:
54
Processor communication
Device communication
Data buffering
Error detection
7.2.1 I /O steps
The control of the transfer of data from an external device to the processor might involve the following
sequence of steps:
7.3 I /O techniques
There are three principal I/O techniques:
Programmed I/O, in which I/O occurs under the direct and continuous control of the program requesting
the I/O operation.
interrupt-driven I/O, in which a program issues an I/O command and then continues to execute, until it
is interrupted by the I/O hardware to signal the end of the I/O operation and
Direct memory access (DMA), in which a specialized I/O processor takes over control of an I/O
operation to move a large block of data.
When the processor, main memory, and I/O share a common bus, two modes of addressing are possible:
memory mapped and isolated.
I/O locations are isolated from memory system in a separate address space.
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User can expand the memory to its full size
Data transferred between I/O and microprocessor must be access by IN/OUT instructions
In PC, isolated I/O ports are used for controlling peripheral device
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Reference
Computer Organization and Architecture Designing for Performance: William Stallings 8 th Edition
D.A. Patterson & J.L. Hennessy - Computer Architecture
Approved by : ______________________________________________________________
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