CS211 Digital Systems/Lab

Introduction to VHDL
Hyotaek Shim, Computer Architecture Laboratory
 Programmable Logic Device (PLD)
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An electronic component used to build

reconfigurable digital circuits
Before used in a circuit,
circuit it must be programmed
SPLD (Simple Programmable Logic Device)
CPLD (Complex Programmable Logic Device)
FPGA (Field-Programmable Gate Array)

CPLD FPGA
SPLD
 Simple PLD (SPLD)
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Programmable Array Logic (PAL) Programmable Logic Array (PLA)

 Complex PLD (CPLD)
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Multiple PAL
PAL-like
like blocks on a single chip with
programmable interconnect between blocks
 Field-Programmable Gate Array (FPGA)
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An array
y of programmable
p g basic logic
g cells
surrounded by programmable interconnect

Xilinx XC4000 Configurable Logic Block (CLB).

 Hardware Description Lang. (HDL)
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Hardware Description Language (HDL)

A software programming language used to model a
piece of hardware
Verilog-HDL, VHDL, SystemC, ABEL
VHDL(VHSIC HDL)
1980 USA Department of Defence
1987 IEEE Standard 1076
Verilog HDL
1981 Gateway Design Automation
1995 IEEE Standard 1364
 VHDL vs. Verilog
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On the surface
surface, not much
Both can be used for designing ASICs and
simulating systems
Both are IEEE standards and are supported by
all the major EDA vendors
VHDL requires longer to learn and is not so
amenable to quick
quick-and-dirty
and dirty coding
Many engineers will one day be bi-lingual in
both HDLs
 Introduction to VHDL
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Designed to describe the behavior of digital

systems
Used as an input to commercial synthesis tools
(only subsets of VHDL are synthesizable)
VHDL is concurrent
HDL which provides a wide range of levels of
abstraction
Architectural, Algorithmic, RTL, Gate, Switch
VHDL has hierarchical design units
 VHDL Structure
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Circuit module
Entity declaration + architecture body
Circuit Module

Ports Entity Declaration

Architecture (Body)
Sequential,
Combinational
Subprograms

An entity
y is a simple
p declaration of a modules
inputs and outputs.
An architecture is a detailed description of modules
internal structure or behavior.
 Syntax of a VHDL entity declaration
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entity example1 is
portt ( x1,
1 x2,
2 x3
3 : in
i std_logic
td l i ; -- input
i t signals
i l
in1 : in integer ;
val1 : out std_logic ; -- output signals
Signal Name val2 : out std_logic_vector(3 down to 0) ;
end example1 ;
Mode Type
architecture sample1 of example1 is
begin
-- hello world ;
end sample1 ;

Entity-name
y
User-defined identifier to name the entity
Signal-names
g
User-defined identifiers to name external-interface signal
 Syntax of a VHDL entity declaration
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Mode : specifying
p y g the signal
g direction
In : the signal is an input to the entity.
Out : the signal is an output of the entity.
Inout: the signal can be read as an input or an output of the
entity. This mode is typically used for three-state
input/output pins.
Buffer: the signal is an output of the entity, and its value
can also be read and written inside the entitys architecture.

Upper Module
In or Inout In Inout Inout
Lower Module

Out or Inout Out Buffer Buffer

 Syntax of a VHDL entity declaration
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Signal types
library IEEE ;
use IEEE.std_logic_1164.all
IEEE.std logic 1164.all ;

std_logic(bit) : U(Uninitialized), X(Forcing Unknown),

0(Forcing 0), 1(Forcing 1), Z(High Impedance), W(Weak
Unknown), L(Weak 0), H(Weak 1), _(Don't Care)
std_logic_vector(bit vector)
for 8bit data type : std_logic_vector(7 downto 0)
integer, real, character, boolean, etc.
 Predefined Operators
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Integer Operators: Boolean Operators:

+ addition and AND
- Subtraction or OR
* Multiplication nand NAND
/ division nor NOR
mod modulo division xor exclusive OR
rem modulo remainder xnor exclusive nor
Abs absolute value not complementation
p
** exponentiation & concatenation
 Sequential Statement
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[LABEL:] if expr then [LABEL:] [while expr] loop

{sequential_statement}
[{elsif expr then
{sequential_statement}}]
[else
{sequential statement}]
{sequential_statement}]
end if [LABEL];
{sequential_statement}
end loop [LABEL];
[LABEL:] for ID in range loop
{sequential statement}
{sequential_statement}
end loop [LABEL];

[LABEL:]] case expr is

i
{when choice [{| choice}] =>
{sequential_statement}}
end case [LABEL];
 Process Statement
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Logic
g circuit description
p in architecture body
y
process
concurrent statement
sequential statement

sequential statement
concurrent statement

Consists of concurrent statement and sequential

statement
Process contains several sequential statement

Process itself is a sort of concurrent statement

Process have three different state : suspended,

suspended
active, running
 Process Statement
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Whats
What s the difference?
architecture con of drv is architecture seq of drv is
begin begin
A <= B; P
Process(B,
(B C)
begin
A <= C; A <= B
end con;; A <= C
end process;
end con2;

M l i l driver
Multiple d i
Several signal assignment to a single signal driver
Signal driver
A source which determines a value of each signal
A signal
g is updated
p by
y the driver at every
y source update
p
 Delta Delays (1/2)
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Delta time is the time between two sequential

q
events.
The time to take from assigning
g g a value till
updated
The following VHDL code makes infinite delta delay
and generates a synthesis error

architecture con of some is

begin
A_Sig <= B_Sig ;
B Sig <= A_Sig
B_Sig A Sig ;
end con;
 Delta Delays (2/2)
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Delta delays are used to order events.

 Architecture Style (1/4)
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Behavioral Style
Describes a system in terms of what it does(or how it
behaves)]
IF, CASE, FOR, mainly within Process statement

architecture BEHAVE of architecture BEHAVE of MUX41 is

COMPARE is begin
begin case sel is
process (A, B) when "00" => Z <= i0 ;
begin when "01"
01 => Z <= i1 ;
if (A = B) then when "10" => Z <= i2 ;
C <= '1' ; when "11" => Z <= i3 ;
else end case ;
C <= '0' ; end BEHAVE ;
end if ;
end process ;
end BEHAVE ;
 Architecture Style (2/4)
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Dataflow Style
Specifies the relationship between the input and output
signals
AND, OR, NOT, XOR, etc.

architecture of DATAFLOW of COMPARE is

begin

C <= not (A xor B) ;

D <= A and not B ;

end DATAFLOW ;
 Architecture Style (3/4)
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Structural Style
Describes a system as interconnection of predefined
components, hierarchical design
consists
i t off modules
d l and
d iinterconnections
t ti
Component, Port Map
architecture STRUCTURE of COMPARE is
signal I : BIT ;

component XOR2 port (X

(X, Y: in BIT; Z: out BIT) ;
end component ;

component INV port (X: in BIT; Z: out BIT) ;

end component ;
begin
U0: XOR2 port map (A, B, I) ;
U1: INV port map (I, C) ;
end STRUCTURE ;
 Architecture Style (4/4)
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Example of Structural Style U1 U2

D1
I3 Y B D1 Y
architecture structure of MUX41 is I2 Z
component MUX21 D0 D0
S
port (D1, D0, S : in std_logic;
Y : out std_logic); D1 A
I1 Y
endd component; t I0
signal A, B : std_logic; D0 S
U0
begin
U0 : MUX21 port map sel(0) sel(1)
(D0 => I0, D1 => I1, S=>sel(0), Y=>A);
U1 : MUX21 port map
(D0 => I2,
I2 D1 => I3,I3 S=>sel(0),
S=>sel(0) Y=>B);
U2 : MUX21 port map
(D0 => A, D1=>B, S=>sel(1), Y=>Z);
end structure;
 VHDL Source Code: Latch
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VHDL Code for Latch

Library IEEE;
Use IEEE.std_logic_1164.all;

Entity Latch is
Port(LE, Din : in std_logic;
Dout : out std_logic);
std logic);
End Latch;

Architecture Latch_arch of Latch is

Begin
Process (Din, LE)
Begin
If (LE=1)
(LE= 1 ) then
Dout <= Din;
End if;
End process;
p ;
End Latch_arch;
 VHDL Source Code : D-Flip Flop
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D-flip
p flop
p triggered
gg by
y rising
g edge
g
library IEEE;
use IEEE.std_logic_1164.all;

entity d-ff is
port(clk, d: in std_logic;
q : out std_logic);
_ g );
end d-ff;

architecture d-ff_arch of d-ff is

begin
process(clk) Rising_edge(clk)
begin
if(clk'event
( and clk = '1')) then
q <= d;
end if;
end if
end process;
end d-ff_arch
 VHDL Source Code : Register
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8-bit
8 bit register
architecture Reg_arch of Reg is
begin
Library IEEE; process(clk, rst)
use IEEE.std_logic_1164.all;
begin
entity Reg is if(rst = '1') then
port(clk
( lk : ini std_logic;
d l i q <=
< ((others
th =>
> '0')
'0');
rst : in std_logic; elsif(clk'event and clk ='1')
ld : in std_logic; then
d : iin std_logic_vector(7
td l i t (7 if(ld = '1') then
downto 0);
q <= d;
q : out std_logic_vector(7
downto 0)); end if;
end Reg; end if;
end process;
endd Reg_arch;
R h
 Typical Design Flow
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HDL design : behavioral or

structural description of
design
RTL Simulation verifies logic
model & data flow. The
simulation is typically
performed to confirm that the
code is functioning as
intended At this step,
intended. step no
timing information is provided.
Post-Synthesis Simulation :
SDF(standard delay format)-
timing info. of each cell in the
design.
The place and route tools are
used for layout generation.
generation
HDL Timing Simulation(Post-
Layout Sim) : after the design
has completed the PnR,
simulation with back-
annotated information.
 Synthesis
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Synthesis
y = Translation+Optimization+Mapping
p pp g
 Mapping (1/2)
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Original
g Netlist Possible Covering
g LUT Mapping
pp g from Covering
g
 Mapping (2/2)
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LUT0
LUT4

LUT1
FF1
LUT5

LUT2

FF2
LUT3
 Typical Design Flow
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HDL design : behavioral or

structural description of
design
RTL Simulation verifies logic
model & data flow. The
simulation is typically
performed to confirm that the
code is functioning as
intended At this step,
intended. step no
timing information is provided.
Post-Synthesis Simulation :
SDF(standard delay format)-
timing info. of each cell in the
design.
The place and route tools are
used for layout generation.
generation
HDL Timing Simulation(Post-
Layout Sim) : after the design
has completed the PnR,
simulation with back-
annotated information.
 Placing
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FPGA CLB SLICES

 Routing
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FPGA
P
Programmable
bl Connections
C i