Embedded Systems Purushotam Shrestha

Chapter 4: Interfacing
4.1 Communication Basics
Communication exists between various units during processing of data. Data may be acquired from I/O
devices for processing, intermediate results may be temporarily stored in memory and final results may be
sent to I/O devices. Also instructions are fetched from memory.

Some basic communication entities and terminologies are discussed below:

Wires: Wires are single conductors connecting ports/ pins of two communicating units. They may be
Unidirectional: transferring the bits in single direction or
Bidirectional: that transfers the bits in both the direction.
Bus: Bus is a set of wires with a single function/ purpose. They carry a group of bits intended for single
purpose.
Like address bus that carries address values to a memory
system.

Ports/ Pins:
Actual interface where the buses/ wires are connected to
communicating unit.
Connects bus to processor or memory.
Single port for a function or a group of ports for a
purpose.

Timing diagrams:
A timing diagram is a representation of a set of signals(control signals and data lines) in the time domain. A
timing diagram contains many rows, usually one of them
being the clock. The timing diagram provides an overall
description of the timing relationship between the
represented signals.

Timing diagrams show us what exactly is happening with

reference to time. It is a tool that is ubiquitous in digital
electronics, hardware debugging, and digital
communications.

Time is on Horizontal axis and increases to right.

Vertical Axis represents Low or High States of signals.
Separate Signals are represented by separate lines .

Assert / Dessert:
To assert is to activate something and to dessert is to deactivate. The actual signal may be logic high or low.
Bus cycle:
A bus cycle is a single transaction between system memory and the CPU.

BASIC PROTOCOL CONCEPTS

Master /slave: In communication, the master is the entity that initiates communication procedures and the
slave responds to the requests from the master.

Time multiplexing: Multiple communication devices share a single channel on a time shared basis. Each
device communicates in a particular time slot (period).

Control methods:
Strobe: There are separate lines for initiation, request. Data transfer occurs for fixed period of time. Once the
time elapses, communication stops whether the transfer has completed or not.

Chapter 4 1
Embedded Systems Purushotam Shrestha

Handshaking: Handshaking is an automated process of negotiation that dynamically sets parameters of a

communications channel established between two entities before normal communication over the channel
begins. It follows the physical establishment of the channel and precedes normal information transfer.
Signals are transmitted back and forth over a communications network in order to establish a valid
connection between two stations. An acknowledge signal indicates receipt of the data.
A "hardware handshake" uses dedicated wires such as the request-to-send (RTS) and clear-to-send (CTS)
lines in an RS-232 serial transmission. A "software handshake" sends codes such as "synchronize" (SYN) and
"acknowledge" (ACK) in a TCP/IP transmission.

ISA:
Industry Standard Architecture: It is a computer bus standard to transfer data between communicating
entities like processor and memory. There are address and data lines. A separate signal, called the address
latch enable, ALE for short, must be asserted in order for the address bits to select the locations. Also,
transfer doesnt occur until the medium is ready which is indicated by CHRDY. If the CHRDY is deserted, the
master has to wait.
ISA bus is 8 or 16 or 20 bit wide.

4.2 Microprocessor Interfacing

I/O interfacing
Port and bus based
Port based- It is also known as parallel I/O. A port can be directly read and written by the processor
instructions by reading or writing dedicated register connected to the port. The data pins of the register are
the port / pins.

Bus based: A bus is connected to all the devices that the processor needs to communicate with. The bus
consists of address lines, data lines and some control lines. A particular device is selected by providing the
address on the bus. Then the data transfer takes place in the data lines. The control lines determine the
communication parameters like read/ write.

Both topologies may be extended by use of I/O peripheral devices.

Bus based I/O may be

Memory mapped and Standard I/O

Memory mapped: Peripheral devices and memory locations are discriminated by address values from
single address space. No additional instructions are needed; memory read/write instructions will work
for I/O as well. The MOV instruction can work for both the memory locations as well as I/O devices.
The disadvantage is the number of addressable memory locations decreases.

Standard I/O or I/O mapped I/O: The I/O devices are identified using separate values/lines. Whether
the address values on the bus is for a peripheral or memory is determined by a separate control line ,
like M /IO: if M/IO is low, it selects memory else if it is high peripherals are selected. Additional
instructions are required for handling I/O. The instructions IN, OUT are different from the ones used
with the memory and identify the I/O devices. Addresses are not lost, simpler address decoding logic
is enough, but separate instructions are required. Eg: ISA

Interrupts: In order to read or write data into I/O devices the processor needs to poll them periodically. This
interaction slows down the overall performance. To overcome disadvantage of polling, the interrupt method
is used. At the end of an execution of a machine instruction, an interrupt bit is checked if any interrupt is
available. This feature is built into the controller hardware and is performed quickly. If it is asserted, the
processor stops the regular program execution and goes on to execute the interrupt service routine, which
handles the I/O. The interrupts may be used for many purposes.

2 Chapter 4
Embedded Systems Purushotam Shrestha

The interrupt service routine is located at an address called the interrupt address vector. The address is
determined by two methods:
Fixed and Vectored
In Fixed method, the address to which the program execution goes to is fixed and is built into the processor
hardware. It cannot be changed. If the space is not enough, it will contain the address where the actual ISR is
located.

In Vectored method, the ISR address is held by the peripheral device that generates the interrupt. Once an
interrupt is generated, the processor acknowledges the interrupt and requests for the interrupt vector address.
The peripheral responds by putting the address on the bus. The processor upon getting the address goes on to
execute the ISR.

A compromise may be an interrupt address table consisting of interrupt addresses against a number. The
peripheral provides the number and the processor jumps to the address pointed by that number in the table.
If a peripheral is re-assigned a different number, then the interrupt from that peripheral will cause a different
ISR to execute. This method also decreases the bus and the register width that carries the address of ISR and
brings flexibility in ISR assignment.

Interrupts may be internal or external to the processing unit. The I/O interrupt is external. The internal
interrupts may come from on board timers, arithmetic operations.
Also, the interrupts may be maskable which can be ignored by the processor or non-maskable that must be
served.
In case of multiple interrupts, a priority definition can be used to queue the interrupts.

DMA: Direct Memory Access: In case of I/O being handled directly by a processor, precious time and
computing resource is wasted. The I/O process can be assigned to a separate processor, the DMA controller, a
single purpose processor whose purpose is to transfer data between the I/O devices and memory. Now the
peripherals interact with the DMA controller, the main processor is relieved of the I/O chores.

The DMA process goes on like this:

a peripheral requests the DMA controller for data transfer(or the other way ).
Upon receiving the request, the DMA requests the main processor for the system bus.
The processor releases the use of the bus and signals the DMA with an acknowledge signal.
Once the system bus is available, data transfer begins, the transfer being handled by the DMA controller.

The transfer is generally block level moving multiple words. After the transfer is complete, the system bus is
released and processor regains the control and uses it.
The requirements are that the DMA controller must be configured with a starting memory address where the
transfer is to take place. The transfer mode, word or block must also be defined. During the transfer, the
processor cannot use the system bus. Alternatively, the processor may continue with data in cache in a
separate bus.
A DMA controller may have multiple channels to handle multiple peripherals.

4.3 Arbitration

The arbitration is the process of allocating resource when multiple peripheral devices request for the
resource. Its a process of resolving conflict when there is a contention for resources. Two or more peripherals
may generate interrupts requesting for processor time. The processor cannot service all of the peripherals at
the same time. It must be decided which peripheral device should get the service. The process of arbitration
determines the peripheral device to which the service is provided.
There are different methods for the process of arbitration.

Chapter 4 3
Embedded Systems Purushotam Shrestha

Priority Arbiter: The

arbitration process is
carried out by a special
purpose processor called
the Priority Arbiter. All the
peripheral devices are
connected to the priority
arbiter which accepts all
the interrupts from the
connected devices. In turn,
the arbiter is connected to
the processor which
actually processes the
interrupt by executing the ISR. The Priority Arbiter passes the interrupts based on the method it is using:
Fixed Priority: Each peripheral has a rank. The interrupt generated by the peripheral with the
highest ranks gets served first. This method is applicable when the peripheral devices have clear
priority.

Round Robin: There is no fixed priority for the devices. All the devices have similar or equal priority.
The service priority changes based upon service history of the device, in a round robin fashion.

It's a centralized way of arbitration. The arbiter has all the authority and acts on simple rules. Also the
peripherals do not have to implement the arbitration mechanisms. The demerit is if the arbiter crashes, the
whole system comes to a halt. Also, there is cost for an additional device; the arbiter.

Daisy Chain Arbitration:

No controller is present
for arbitration. A
peripheral is connected to
the processor and all
others are connected
upstream, one after other
in a daisy chain. The
requests of the
peripherals flow towards
the processor in
downstream. A REQUSET
is made by a peripheral and passed through all the other peripherals in the downstream to the processor.
The processor responds with a GRANT signal. The signal is processed by the peripheral that generates the
REQUSET and begins to use the bus. An indicator signal is raised that indicates the busy state of the bus and
that can't be used. The peripheral closest to the processor has the highest priority.
Compared to the Priority Arbiter method of arbitration, this method may reduce cost by not using a arbiter.
Also, any number of peripherals can be chained without having to modify the circuit.
The peripherals are required to have mechanism to handle the request and grant signal implying a more
complex hardware/ software. And, if a peripheral fails, all the peripherals in the upstream are disconnected.

Network Oriented Arbitration: A bus connecting multiple processors is referred to as network. The bus
connects intelligent devices or microprocessors located farther from each other. The bus length is longer.
Two devices may put data on the bus simultaneously without having the knowledge that the other one is also
using the bus resulting in garbled data. The devices wait for a random time and retry. CSMA-CD, ethernet, I2C
or a protocol may be built into the bus that allows a single device to use the bus at a time. CAN, Controller
Area Network uses priority based addressing scheme to allow bus use.

4 Chapter 4
Embedded Systems Purushotam Shrestha

4.4 Multilevel Bus Architecture

Multilevel bus architecture
employs separate bus for high
speed processors or memories
and low speed peripheral
devices which emphasize
portability.
System local bus for high speed
devices
wide bus
faster
Peripheral bus for peripheral
devices
Narrower
Slower

A bridge, single purpose processor, makes communication between the devices on the system local bus and the
peripheral bus
Aligns speed mismatches
Converts the data bit width
Detects addresses on either side of bus
The devices connected to either buses may not be aware that a bridge exists

Depending upon the architecture of the design, multiple levels of the buses may be integrated in a similar
fashion.

4.5 Advanced Communication Principles:

Layering
Layering refers to the hierarchical organization of communication protocols. Each layer interfaces with the
adjacent layers providing information exchange and encapsulating the required processing.

Error Detection and Correction

During transmission of information, the transmitted signal can get corrupted in the medium introducing
errors in the received signal. Mechanisms must be incorporated to detect the errors. A simple technique is to
use parity. Correction measure may be a request to retransmit. Also error correction codes can be
implemented adding redundant bits to the actual message bits.

Parallel: In parallel mode of communication the bits of a data word are transmitted at once. If the word size is
8 bits, all of the 8 bits are transferred at once. The number of data lines/channels is equal to the number of
the bits in the word which make the simultaneous transmission possible. This enables a faster data transfer.
But, on the other hand, the number of wires required is large, which increases size and cost. When the
distance is longer, inconsistencies in wire length pose in simultaneous arrival of data. Also longer and larger
number of wires increases parasitic capacitance which causes slower transfer per unit time decreasing
throughput. The applicable area is on board communication between IC's.

Serial: In serial mode of transfer, a single bit is transferred at a time. If a 8-bit word is to be transferred, a
single bit is transferred, one by one. The parameters like start and end of data transfer, word size etc are pre-
negotiated. Compared to parallel mode, it seems slower. But other factors make serial communication better.
A single wire or 2 at most are required. The less number of wires decreases size as well as cost. At longer
distances, due to less capacitance and less inconsistencies in wire length, the average throughput also
increases. It is more suitable for data transfers between separate systems.

Chapter 4 5
Embedded Systems Purushotam Shrestha

Wired Communication: The communicating devices are connected by wires and data signals travel on the
connecting wires. An optical fiber is also an option. In either of the cases, the data signals must be
appropriately conditioned so that the signal can travel through the connecting medium.

Wireless:
In wireless communication, the communicating devices are not physically connected by wire. The physical
medium that carries the signals is the electromagnetic waves that can travel through vacuum.
Infrared: It uses the infrared waves just below the red light of the visible light. Because of the high frequency,
it requires sharp Line of Sight, LoS, that the transmitter and the receiver be aligned in a straight line facing
each other.
Radio wave: The communication using radio wave uses the electromagnetic wave even below the infra red
band. A band of frequencies are allocated for communication purposes, Depending upon a particular band,
the LoS may or may not be required.

Some communication Protocols:

Serial Protocols:
I2C: Inter IC . It was developed by Philips, used to connect IC's like memory devices like RAM, EPROMs, Flash,
microcontrollers, on board. The protocol allows a rate of 100 kbps, 7 bit addressing in normal mode or 3.4
Mbps, 10 bit addressing in fast mode . It is a 2 wire serial bus: one is serial data line SDA and other is clock
wire called SCL. The wire can be long, the limit is that the total capacitance should be less than 400 pF. There
is a master and other devices are slaves. The master initiates transfers. Transfers start with a start condition
and end with a stop condition

CAN: Controller Area Network

A Controller Area Network, CAN, works with CSMA/CD+AMP.(Carrier Sense Multiple Access with Collision
Detect, AMP: Arbitration on Message Priority). The mode of transfer is serial.
The bus consists of properly terminated twisted pair of wire bus to which communicating nodes are connected.
Of the two wires, one is called the CANH and the other is CANL. Each node contains a CAN controller and a CAN
Transceiver via which a node is connected to the bus line.
The bus arbitration is achieved by use of priority identifier bits. The node that writes lowest identifier wins the
bus and goes on to using it.
All messages are of broadcast nature, any node can transmit and receive. A particular node can decide whether
to process or not a particular data. The message contains an identifier that identifies the source or content of
the message

CAN bus is characterised by:

Robust and Reliable, proven technology
Applicability in noisy area,
Long bus wires
A CAN bus may range from 1Mbps/ 40m to 256 Kbps/ 500m long.

FireWire/ IEEE 1394

The firewire is a high performance bus developed by Apple Computer Inc for transfer of very large amount of
data, not provided by LAN or WAN.
The goal of the bus is to interface independent electronic components rather than components within a
system, e.g., Desktop computer and scanner
The bus is a 6 wire system, 4 for data and 2 for power, but power is rarely used. There are 4 or 9 wire systems as
well. It allows data transfer rates of12.5 to 400 Mbits/s, 64-bit addressing, with Plug-and-play capabilities. A
good feature is it is capable of supporting a LAN similar to Ethernet.
Applications using FireWire include disk drives, printers, scanners, cameras.
The 64 bit address consists of
10 bits for network ids, 1023 subnetworks
6 Chapter 4
Embedded Systems Purushotam Shrestha

6 bits for node ids, each subnetwork can have 63 nodes

48 bits for memory address, each node can have 281 terabytes of distinct locations

USB(Universal Serial Bus)

The USB was developed foreasier connection between PC and monitors, printers, digital speakers, modems,
scanners, digital cameras, joysticks, multimedia game equipment. The bus is a 4 wire system supporting 2 data
rates:
12 Mbps for increased bandwidth devices
1.5 Mbps for lower-speed devices (joysticks, game pads)
A tiered star topology can be used in order to attach multiple devices to the bus. One USB device, called the
hub, is connected to the PC. A hub can be embedded in devices like monitor, printer, or keyboard or can be
standalone. Multiple USB devices can be connected to hub. Up to 127 devices can be connected like this.
The USB host controller residing in the host PC is responsible for managing and controls bandwidth and driver
software required by each peripheral
dynamically allocating power downstream according to devices connected.

Parallel Protocols:
PCI: Peripheral Component Interconnect
High performance bus originated at Intel in the early 1990s
Standard adopted by industry and administered by PCISIG (PCI Special Interest Group)
Interconnects chips, expansion boards, processor memory subsystems
Data transfer rates of 127.2 to 508.6 Mbits/s and 32-bit addressing
o Later extended to 64-bit while maintaining compatibility with 32-bit schemes
Synchronous bus architecture
Multiplexed data/address lines

ARM Bus:
Designed and used internally by ARM Corporation
Interfaces with ARM line of processors
Many IC design companies have own bus protocol
Data transfer rate is a function of clock speed
o If clock speed of bus is X, transfer rate = 16 x X bits/s
32-bit addressing

Wireless Protocols:
IrDA:
Protocol suite that supports short-range point-to-point infrared data transmission
Created and promoted by the Infrared Data Association (IrDA)
Data transfer rate of 9.6 kbps and 4 Mbps
IrDA hardware deployed in notebook computers, printers, PDAs, digital cameras, public phones,
cell phones
Lack of suitable drivers has slowed use by applications
Not in wide use

Bluetooth:
New, global standard for wireless connectivity
Based on low-cost, short-range radio link
Connection established when within 10 meters of each other
No line-of-sight required
e.g., Connect to printer in another room

Chapter 4 7
Embedded Systems Purushotam Shrestha

IEEE 802.11: Wireless LAN. WiFi

Proposed standard for wireless LANs
Specifies parameters for PHY and MAC layers of network
PHY layer
o physical layer
o handles transmission of data between nodes
o provisions for data transfer rates of 1 or 2 Mbps
o operates in 2.4 to 2.4835 GHz frequency band (RF)
o or 300 to 428,000 GHz (IR)
MAC layer
o medium access control layer
o protocol responsible for maintaining order in shared medium
o collision avoidance/detection

8 Chapter 4