Embedded Systems Purushotam Shrestha

Chapter 6: Control Systems

A MOSFET, Metal Oxide Semi-conductor Field Effect Transistor, is a 3 (or 4 when the substrate is isolated)
terminal voltage controlled device whose conductance is controlled by voltage applied at the gate terminal.
MOSFETs generally share following characteristics:

Every FET has a gate, drain, and source.

Current flows between the drain and source.
The gate is the control terminal.
The DC gate leakage current is negligible, Ig0, MOSFETs are voltage controlled devices.

A MOSFET can be used as switch, the application may be to control loads such as LEDs, dc motors, lamps or in
family of logic called the CMOS gates. So the MOSFETs can be found in controlling circuits as gate components
as well as load driver circuits as large switches. The sizing should be appropriately matched for specific
applications.
There are two types of MOSFETs: n channel and p-channel. The discussion here is referred to n-channel
MOSFET. But they apply to p-channel as well.

Analytic Equations for MOSFETs

The operation of a MOSFET is
controlled by the voltage applied to
the gate. In order to form a
conducting channel under the gate,
the gate voltage must exceed the
threshold voltage of transistor. The
thickness of the channel formed
under the gate at source or drain is
proportional to the voltage difference
between the voltage applied at the
source or drain and the gate
threshold voltage difference.

d, depth of channel VDS VGS VT , at drain.

the MOSFET operates in 3 main regions:

Cut Off
Linear
Saturated
Cut off Region
Initially, when the gate voltage is below threshold
voltage, VT , the channel is not formed and no
current flows, even if there is drain to source
voltage, VDS .

Linear Region
When the gated voltage exceeds the threshold
voltage, current flows in the channel. The current
is proportional to the applied VDS . As VDS is
increased, so does the current. For a different VGS (which must be greater than VT ), the channel thickness is
different and hence the channel current is different, even if VDS is same. The transistor is operating in triode
or non-saturated mode. The channel current is given by

Chapter 6 1
Embedded Systems Purushotam Shrestha

2
IDS = k 2 VGS VT VDS VDS , 0 VDS VGS VT

W
k=
2t L
which has the unit of A/V2 and

where,
= mobility of carriers
= dielectric constant of oxide insulating layer
t = thickness of oxide under the gate
W = channel width
L = channel length

Saturated Region
As the drain to source voltage, VDS , is increased such that,
0 VGS VT VDS

The channel thickness cannot increase. The channel is said to be pinched off and no more current increases. In
order for the channel thickness to increase, the difference VGS VT , must exceed the VDS .The transistor is
said to be saturated for the given conditions. The current is

IDS = k VGS VT 2 , 0 VGS VT VDS

Speed Calculations
The speed with which the devices can be turned off or turned on depends upon the process of discharging or
charging the capacitor associated with the gate. A MOSFET with charged gate cannot be turned off unless the
charge is removed. Similarly, to turn the transistor on, the gate and the associated capacitor must be charged
before it can generate the field effect that creates the channel. When transistors are in cascaded formation on a
circuit board, the stray capacitances also play role. So, the speed of switching is limited by the associated
capacitances at the cascade point,
Capacitance associated with the device, at the gate and the output stage,
Stray capacitances in the circuit

2 Chapter 6
Embedded Systems Purushotam Shrestha

The switching characteristic is defined in terms of rise and fall times.

The rise time is defined as the time required to reach 90% of the final value from 10% of the final value. This is
like taking the device from OFF state to ON state.
Similarly, the fall time is defined as the time required to reach 10% of the final value from 90% of the final value.
The less the rise and fall times, the faster the device can be turned on or off.

Lets consider two MOSFET circuits, the MOS inverters. The inverters can be used as a switch as well. The load
should be connected to the output.
The one in the left is the NMOS inverter consisting of load transistor, the upper one, and driver transistor, the
lower one. Both are NMOS transistors. The transistors are manufactured such that the k parameters for the
transistors is

>

The load transistor acts like load resistor and the driver transistor acts like the switching device that actually
causes the inverter action. When the input is high, the driver transistor is turned ON and the output goes to low
and vice versa.

The one on the right is CMOS inverter. The inverter consists of symmetrical p-(upper one) and n-(lower one)
channel MOSFETs. The design is such that

When the input is high, the lower MOSFET is turned on and upper is turned off. As a result, the output is
connected to the ground and is low. When the input is low, the lower MOSFET is turned off and upper is turned
on, the output goes to high.
For the NMOS, the rise time is given by,
Chapter 6 3
Embedded Systems Purushotam Shrestha

9CL
tr =
k L Vf
And the fall time is
1.15 CL VCM VGS + VT
tf = +
k D VGS VT kD VGS VT 2

The term CL is the total capacitance associated with the circuit.

The rise and fall times are not equal in case of NMOS inverters.
For CMOS, the parameters k L and k D are almost equal and the rise and fall times are quite comparable.

In addition, a turn-on and turn-off delay time can be included into rise and fall times respectively. A turn-on
delay time is time required to charge gate capacitance before drain current starts and turn-off delay is time
required to discharge the same after the drain current is off.

Propagation Delay

The propagation delay can be defined as the time period between the application of input and corresponding
change in the output. It can be viewed as time response of the system in consideration.

The measurement is done between the time the input signal reaches the 50% of its high value and the time the
output reaches 50% of its high value. The naming is with respect to the output. The propagation delay when the
output makes a transition from high to low is called the Propagation Delay high to low, , and the other,
from low to high is called the Propagation Delay low to high, . The average of the two is used to specify a
system.

Power Dissipation
When a MOSFET carries current from drain to source, the inherent resistance in the path causes power to be
dissipated in the device. The transistor may be driving a large load or logic gates, whichever is the case, current
flows and power is dissipated. The power dissipated in the device is given by

2
=

The current flowing in a transistor, , depends upon the mode in which the transistor is operating.

4 Chapter 6
Embedded Systems Purushotam Shrestha

The power dissipated is loss. The loss can be minimized by lowering the value of . The power is released in
form of heat. The device gets hot. The performance of a device operating in higher temperature degrades. So
the device must be cooled by using heat sinks or cooling fan.
PowerDelay Product indicates the energy efficiency of a logic gate. It is the product of power consumption,
averaged over a switching period, times the inputoutput delay. It has the dimension of energy, and measures
the energy consumed per switching event. It is also known as switching energy.

Fan Out
Fan out is the number of similar gates that a gate can drive without the logic level being misinterpreted. The
value of fan out depends upon the capability of the gate
to source current or
to sink current from the driven gate.

Higher value of fan out is always preferable. But as the gate is loaded, performance degrades. Loading
increases capacitance which increases delay
requires more current to be sourced and increases power dissipation

Noise Margins and Transfer Characteristics

Noise Margins
Noise margin represent the range of voltage in which a logic gate can interpret the logic level. While providing
an input to a gate, the voltage value represents the logic level. In both the levels, high and low, the voltage
may swing, either due to addition of noise or excessive loading. For correct operation, the voltage must be
correctly interpreted. Noise margins provide the amount of voltage that an input value may swing by.

Now lets look at the figure. Two gates are cascaded. The output of the gate on the left is connected to the
input of the gate on the right. Also given is the output and input voltage ranges. The ranges define the
logic levels, outside the range, in the intermediate region, the logic level is not defined.

VIL is the voltage which turns on the input transistor in the gate. Below this voltage, the transistor is off
and output is high. Above VIL, the transistor goes to triode region of operation and logic level is undefined.
For input to be logic low, the input voltage must not cross this value, otherwise the logic level cant be
interpreted correctly.

Chapter 6 5
Embedded Systems Purushotam Shrestha

VOL is the output voltage at logic level low, when the transistor is well into saturation. Noise may add to
this voltage or operating conditions may increase this voltage. These can be tolerated until the voltage
doesnt cross VIL. So we have safety region here called the Noise Margin Low and is given by

NML or 0 = VIL - VOL

Similarly, VIH is the minimum voltage required to drive the transistor into saturation so that the output is
low. An input voltage below this operates the transistor in triode region and logic level is undefined.

VOH is the output voltage at logic level high. Above this voltage, the logic level is defined to be 1. Noise may
decrease this voltage, but if it goes below the value of VIH, the logic is not correctly interpreted. The safety of
margin is

NMH or 1 = VOH - VIH which we call Noise Margin High.

Transfer Characteristics

The transfer characteristic gives the relationship between input and corresponding output voltage. The
transistor arrangement is referred to the NMOS and CMOS inverters.

NMOS Inverter

The abruptness and symmetry in the curve is determined by the ratio of channel width to channel length
ratio. Here,

Vout

1 < 2 < 3

1
2
3 Vin

Transfer characteristic for NMOS

The curve starts with 0 input voltage where the driver transistor remains off and output is high. As the
voltage increases the transistor goes to non-saturated region where the transistor works more as an
amplifier than a switch. As the transistor input voltage is increased driving it into saturation, the output
drops to low.

6 Chapter 6
Embedded Systems Purushotam Shrestha

CMOS Inverter

The transfer characteristics exhibits a symmetrical curve because it uses symmetrical transistors, which we
call the complementary MOSFETs.

The abrupt transition and symmetry are desired features.

Vout

Vin
CMOS transfer characteristic

A typical CMOS transfer characteristic

As shown in above figure, a characteristic curve may be useful for finding out noise margins as well.

Chapter 6 7