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ET-7LSD (7 Segment Large Serial Display)

ET-7LSD is a 7 Segment Large Serial Display (4.5 x

7) that continues to develop from ET-7SJD by ETT. We
modify its defects and improve its size, shape and
including the method to connect and control the
circuit better. So, it makes component convenient,
flexible and easy to apply for displaying result
worthily.

Specifications:
Supply Voltage : +12VDC / +5VDC
Current : 200 mA.
Current / Segment : 25 mA.
Input Active : Logic 1
Digit Size : 4.5 x 7
PCB Size : 7 x 9
LED : Super Bright Red 5 mm.

Connection
7SJD has the connective defects in a circuit
because it uses Parallel Interface Cable for
connection and controller, so it is necessary to use
many Output Ports for connection. Problem will be
happened if we connect many boards together because
we must use a lot of Output Ports. So, 7LSD is
improved in the part of the connective circuit better
because it will use Serial Interface that uses only 3
cables and can be interfaced with unlimited board.
Although, we connect many boards together, we still
use 3 cables, so it can save Output Port for
controlling and it is quite easy to write program
controlling the result display. The signals for
connection are described below;

DATA IN: It is signal of Serial DATA IN to

configure result display of 7 Segment and it uses 8
bit data per 1 digit. It controls status ON with
Logic 1 and status OFF with Logic 0. It starts
sending data with the Most Significant Bit (MSB)
first and follows by the next data bit and finally it
ends with the Least Significant Bit (LSB) to be the
last bit of the set data.
Shift Clock: It is Signal Clock Input to control
the shifting external data into internal Register of
 2

7LSD. Signal Data will access through Signal Pin DATA

IN and it uses signal Clock as 8 Periods per 1 set
data. Data will always be shifted into internal
Register every Rising Edge of Signal Clock.
Latch Clock: It is Signal Input to latch the
shifted data that has already accessed into internal
Register completely and to control the result display
through Pin Output. If we disable Latch, the shifted
data will not be affected on the display through Pin
output. Data signal will be latched every Rising Edge
of signal Latch Clock.

The relationship between 3 signals is shown in

the diagram below.

Shift Clock 1 2 3 4 5 6 7 8

Latch Clock

MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
Serial Data
( dot ) (g) (f) (e) (d) (c) (b) (a)

Figure displays Timing Diagram of signal Data Input,

Signal Shift Clock, and Shift Latch.

To control the display

The method to write program for controlling the
result display of 7-Segment is setting the preferable
data to be status ON/OFF first; in this case, we
configure Logic 1 to be in status ON and Logic 0
to be status OFF. The relationship between data and
result display is shown below.
D7 D6 D5 D4 D3 D2 D1 D0
dot g f e d c b a

In the part of writing program, we must shift the

preferable data into internal Register of panel
display and 1 data set must be shifted 8 times
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because it must be corresponding with signal Shift

Clock. When the preferable data has already shifted
into the configured position completely, we must
latch the data set and then we can use it to display
result.

In case of connecting many Boards 7LSD together, we

must interface all 3 signals with Input of the panel
display that is on the end left hand and then
interface Output of the panel display that is on the
left hand with Input of the next digit continuously
and preferably. We can write program to control the
operation by shifting data of digit that is on the
end right hand first and follows by the next digit
that is on the left side. After the end of shifting
data, we can latch all data only one time.

Example Program: Example 1 is an example connection

between 7LSD with Board Microcontroller that uses CPU
MCS-51. In this case, it describes how to control
7LSD to display result. It starts displaying result
from numeric character 0 and uses Time Delay for a
while. Then, it continues to increase numeric amount
until it reaches the last numeric character, it will
loop to re-start. For example 2 is an example
connection between 7LSD and Board Microcontroller
that uses CPU Z80. Both programs are the same as
described below;
SER_OUT : Its function is shifting 1 data set
(8 bit) into internal Register of 7LSD.
DELAY : Its function is Time Delay to display
result before changing to the new data set.
TAB_SEG : It is a Table of 16 characters that
will be displayed.
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MCS-51 CPU Z80 & 8255

Shift Shift
P1.0 PA0
Latch Latch
P1.1
Data In PA2
P1.2 Data In
+ 5V PA4
+ 5V
GND
+ 12V
GND
GND + 12V
DIGIT 1
GND DIGIT 1
+ 5V
GND + 5V
+ 12V GND
GND + 12V
GND

Figure displays the diagram of connection between

Board Microcontroller and 7LSD.

Board Control
and
Port Output

Shift Shift Shift Shift Shift

Latch Latch Latch Latch Latch
Data In Data In Data In Data In Data In
+ 5V + 5V + 5V + 5V + 5V
GND GND GND GND GND
+ 12V + 12V + 12V + 12V + 12V
GND DIGIT 1 GND GND DIGIT 2 GND GND DIGIT 3

+ 5V
GND
+ 12V
GND

Figure displays the diagram of connection between

Board Microcontroller and many 7LSD.
 1 2 3 4 5 6

U1 U2
11 15 SEG A SEG F 1 18
SHIFT CLK SRCLK QA I1 O1 SEGMENT F
12 1 SEG B SEG E 2 17
LATCH CLK RCLK QB I2 O2 SEGMENT E
14 2 SEG C SEG G 3 16
SERIAL IN SER QC I3 O3 SEGMENT G
3 SEG D SEG D 4 15
QD I4 O4 SEGMENT D
D 4 SEG E SEG C 5 14 D
QE I5 O5 SEGMENT C
5 SEG F SEG B 6 13
QF I6 O6 SEGMENT B
VCC
QG
6
7
SEG G
SEG DP
SEG DP 7
SEG A 8
I7 O7
12
11
SEGMENT DP SEGMENT A
R1 QH I8 O8 SEGMENT A
10
10K DIODE
10
SRCLR
13 9 ULN2803A
G QH' SERIAL OUT
C1 74HC595
10uF

SEGMENT F SEGMENT B

SEGMENT B,SEGMENT C,SEGMENT E,SEGMENT F CIRCUIT

+12V +12V +12V +12V +12V

150 150 150 150 330

C C

SEGMENT G

SEGMENT ?

SEGMENT A,SEGMENT D,SEGMENT G CIRCUIT

+12V +12V +12V +12V

150 150 150 150

B B

SEGMENT E SEGMENT C
SEGMENT ?

SEGMENT DP CIRCUIT
+12V
SEGMENT DP
SEGMENT D

75

A A

Title
7 Segment Large Serial Display (ET-7LSD)
SEGMENT DP
Size Number Revision
WWW.ETT.CO.TH 1.0
B
Date: 1-Nov-2006 Sheet 1 of 1
File: D:\7SEG_Large_Serial.ddb Drawn By:
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