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The APZ 212 40 is the first central processor of a new generation based on The APZ 212 40 introduces a new system
industry-standard microprocessors. It introduces a new warm-standby/hot principle. In place of the parallel synchro-
on-demand system principle: the CP has two independent sides, each of nous (lock-step) machine, we are introduc-
which contains two processors—one that serves as an instruction pro- ing a warm-standby/hot on-demand principle.
cessing unit and one that serves as a signal processing unit—which run The CP has two independent sides, A and
B, that are loosely coupled via a high-speed
as a two-way symmetrical multiprocessing computer. The APZ virtual
interconnect and a maintenance channel.
machine handles ASA execution and is the middleware that guarantees Each side contains two processors: one that
telecommunications-grade availability. serves as an instruction processor unit (IPU),
The authors describe the APZ 212 40 hardware and software, the and one that serves as a signal processor unit
warm-standby concept for high availability, and differences and similari- (SPU), running as a two-way symmetrical
ties between this and previous APZ processors. multiprocessing (SMP) computer. The
hardware and the operating system define a
two-node cluster of two-way SMP comput-
ers.
Introduction The APZ virtual machine (VM), a new
part of the system, handles the ASA execu-
Being based on industry-standard micro- tion and is the middleware required to
processors, the APZ 212 40 central proces- achieve telecommunications-grade avail-
sor (CP) is a milestone in Ericsson hardware ability. It provides recovery and repair for
implementation. The latest in a line of cen- hardware faults, software upgrades and the
tral processors, the APZ 212 40 is the first like while minimizing traffic disturbance.
central processor of a new generation, and At the same time, Ericsson is introducing
the platform for future multiprocessor solu- an industry-standard hardware equipment
tions (Figure 1). practice, cPCI, and a standard operating sys-
tem. Parts of the CP core have been re-
written in standard C++ code using com-
mercial development tools.
The APZ 212 40 will be deployed as a
high-capacity central processor for all kinds
Figure 1 of application. It offers processing capacity
APZ 212 40 central processor cabinet. Fan three times as great as the fastest
Note: CDU panel not shown. APZ 212 30, and is fully backward-
RPHM-A compatible—that is, it can run all existing
AXE application software.
CPU board from the microprocessor system (CPU board) the IPNX Ethernet switch in RPHM
• 2 high-performance (GHz) microprocessors, • Some general support functions for the CPU • Cable connection to the central display unit
each with 8 MB level 2 cache board and power module (CDU) panel at the top of the cabinet
• 8 GW (16 GB) SDRAM memory • Cable connections to the CPU magazine fan
UPB board units for monitoring and controlling the fans
RPHMI board • One 1 Gbit/s Ethernet optical fiber connection
• Cable connections to the magazines (RPHB) to the other CP side for updating The PCI interface module (PIM) card (not visible
for the A- and B-sides RPH-A and RPH-B • Two 100 Mbit/s Ethernet cable connections from the front) includes functionality for connect-
• Cable connection to the RPHMI on the other to the adjunct processor over the interplat- ing the CPU backplane with the cPCI backplane.
CP side for error information and for control form network (IPN), connected via the IPNX
of system states (WSB). Ethernet switch in RPHM Power module (in bottom left part of the CP sub-
• One 10 Mbit/s Ethernet cable connection to rack)
Base IO board the adjunct processor, a processor test bus • Duplicated –48V external connection
• Access port (connected to UPBB) for obtain- (PTB) for access with the central processor • DC/DC converters for internal system volt-
ing detailed low-level system-error information test (CPT) command interface, connected via ages
DIMM
memory
PIM
Compact
PCI back-
plane
Heat
sink
CPU
Base IO
RPHMI
Top view UPBB Front view
ABC 123
Job distributor
RPHM RPHM
APG40 APG40
Figure 9
APZ 21240 Example of a node in the future.
With its architecture and use of commercial processor systems. In a distributed multi-
microprocessors, the APZ 212 40 allows us to processor system, replicated processors can
take advantage of rapid evolution in the com- improve in-service performance and simplify
puter industry. Development will keep pace with handling when adding capacity to the node. Fig-
the mainstream computer industry and enable ure 9 shows an example of a multiprocessor
improvements in characteristics, such as system.
capacity and robustness, with limited changes A powerful duplicated processor handles
in software. The APZ central processor design job distribution between a number of repli-
is also open enough to simplify moves between cated processors (call handlers). The APG40,
different microprocessor suppliers and the for IO communication, is connected to the
operating systems they support. Gigabit Ethernet used for communication.
The introduction of the interplatform network Other equipment can be attached to the net-
(IPN) via directly connected Ethernet makes the work based on the needs of applications.
APZ 212 40 the obvious platform for future multi-