Sri Kavitha Educational Societys

KHAMMAM INSTITUTE OF TECHNOLOGY & SCIENCES

Ponnekal (Vill), KHAMMAM (Rural),KHAMMAM (Dt)
DEPARTMENT OF
COMPUTER SCIENCE & ENGINEERING
Academic Year: 2017 2018
Lesson Plan
Name of the faculty: E.GURUMOHAN rao Name of the Subject:CO
Year & Branch: II B.Tech II SEM, CSE-A&B Total Number of Periods: 74

UNIT-I
a Introduction, Block diagram of Digital Computer 2
b Definition of Computer Organization, Computer Design and Computer 1

Architecture
c Instruction codes, Computer Registers, Computer instructions, 3
UNIT-I
d Timing and Control, Instruction cycle, Memory Reference Instructions 2
e Input Output and Interrupt, Complete Computer Description. 3
f Control memory, Address sequencing 3
g micro program example, design of control unit. 2
Total Number of Periods:16
UNIT-II
a The 8086 Processor Architecture, Register organization, Physical memory 5
UNIT-II organization
b General Bus Operation, I/O Addressing Capability 2
c Special Processor Activities, Minimum and Maximum mode system and 1
timings.
d 8086 Instruction Set and Assembler Directives 4
e Machine language instruction formats 2
f Addressing modes, Instruction set of 8086 1
g Assembler directives and operators. 1
Total Number of periods:16

a Assembly Language Programming with 8086 3

b Machine level programs, Machine coding the programs 3
c Programming with an assembler, Assembly Language example programs. 2
UNIT-III
d Stack structure of 8086, Interrupts and Interrupt service routines 2
e Interrupt cycle of 8086, Interrupt programming, 1
f Passing parameters to procedures, Macros, 1
g Timings and Delays. 2

Total Number of Periods:14

a Introduction, Addition and Subtraction, 2
b Multiplication Algorithms, Division Algorithms 2
UNIT-IV
c Floating - point Arithmetic operations. 2
d Peripheral Devices, Input-Output Interface, 2
e Asynchronous data transfer, Modes of Transfer 2
f Priority Interrupt, Direct memory Access, 2
 g Input Output Processor (IOP),Intel 8089 IOP. 2
Total No. Of Periods:14
UNIT-V
a Memory Hierarchy, Main Memory, Auxiliary memory, 2
b Associate Memory, Cache Memory. 2
UNIT-V
c Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline 3
d RISC Pipeline, Vector Processing, Array Processors. 3
e Characteristics of Multiprocessors, Interconnection Structures, 2
f Inter processor arbitration, Inter processor communication, and 2
synchronization.
Total No of Periods:14

Total No of Periods: 74

FACULTY SIGNATURE HOD P R I N C I PA L